CN109300871B - 半导体器件、半导体封装及制造半导体器件的方法 - Google Patents

半导体器件、半导体封装及制造半导体器件的方法 Download PDF

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CN109300871B
CN109300871B CN201810794961.2A CN201810794961A CN109300871B CN 109300871 B CN109300871 B CN 109300871B CN 201810794961 A CN201810794961 A CN 201810794961A CN 109300871 B CN109300871 B CN 109300871B
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layer
pad
opening
top surface
lower conductive
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CN109300871A (zh
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崔朱逸
文光辰
徐柱斌
林东灿
藤崎纯史
李镐珍
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种半导体器件包括：在基板上的导电部件；钝化层，在基板上并且包括暴露导电部件的至少一部分的开口；以及焊盘结构，在开口中并且位于钝化层上，焊盘结构电连接到导电部件。焊盘结构包括：在开口的内侧壁上共形地延伸的下导电层，下导电层包括顺序地堆叠的导电阻挡层、第一籽晶层、蚀刻停止层和第二籽晶层；第一焊盘层，在下导电层上并且至少部分地填充开口；以及第二焊盘层，在第一焊盘层上并且与下导电层的位于钝化层的顶表面上的外围部分接触。

Description

半导体器件、半导体封装及制造半导体器件的方法
技术领域
本发明构思涉及半导体器件、半导体封装及制造半导体器件的方法，更具体地，涉及包括焊盘结构的半导体器件及制造半导体器件的方法。
背景技术
根据电子工业和用户需求的迅速发展，电子设备正被制造为在尺寸和重量上更小，并且用于电子设备的半导体封装已不仅需要小型轻量，而且需要具有高性能和高容量。随着朝更小更轻的半导体封装的日益增长的趋势，为了获得高性能和高容量的半导体封装，正在对包括多个堆叠的半导体芯片的半导体封装进行研究。然而，例如由于互连焊盘结构的台阶差，这样的堆叠半导体芯片的电互连会出现复杂化。在具体示例中，非导电材料的俘获和/或金属间化合物(IMC)的形成会由于这样的台阶差而发生，这会使可靠性劣化。
发明内容
本发明构思提供了包括具有高接合可靠性的焊盘结构的半导体器件、半导体封装以及制造该半导体器件和半导体封装的方法。
根据本发明构思的一些实施方式，一种半导体器件包括：在基板上的导电部件；钝化层，位于基板之上并且包括开口，其中开口暴露导电部件的至少一部分；以及焊盘结构，填充开口并且位于钝化层上，焊盘结构电连接到导电部件。焊盘结构包括：下导电层，共形地形成在开口的内壁上以及在围绕开口的钝化层的顶表面上，下导电层包括顺序地堆叠的导电阻挡层、第一籽晶层、蚀刻停止层和第二籽晶层；在下导电层上的第一焊盘层，第一焊盘层至少部分地填充开口；以及在第一焊盘层上的第二焊盘层，第二焊盘层与下导电层的位于钝化层的顶表面上的外围部分接触。
根据本发明构思的一些实施方式，一种半导体封装包括第一半导体芯片以及连接到第一半导体芯片的第二半导体芯片。第二半导体芯片包括：在基板上的导电部件；在基板之上并包括开口的钝化层，开口暴露导电部件的至少一部分；以及在钝化层上并填充开口的焊盘结构，焊盘结构电连接到导电部件。焊盘结构包括：下导电层，共形地形成在开口的内壁上以及在围绕开口的钝化层的顶表面上，下导电层包括顺序地堆叠的导电阻挡层、第一籽晶层、蚀刻停止层和第二籽晶层；在下导电层上的第一焊盘层，第一焊盘层至少部分地填充开口；以及在第一焊盘层上的第二焊盘层，第二焊盘层与下导电层的位于钝化层的顶表面上的外围部分接触。
根据本发明构思的一些实施方式，一种制造半导体器件的方法包括：在基板上形成包括开口的钝化层，开口暴露导电部件的至少一部分；通过顺序地形成导电阻挡层、第一籽晶层、蚀刻停止层和第二籽晶层而在开口的内壁上以及在钝化层的顶表面上形成下导电层；在下导电层上形成模层，模层包括与开口连通的焊盘空间；在下导电层上形成填充开口的第一焊盘层；以及在第一焊盘层上形成填充焊盘空间的剩余部分的第二焊盘层。
根据本发明构思的一些实施方式，一种半导体器件包括：在基板上的导电部件；钝化层，在基板上并且在其中具有暴露导电部件的一部分的开口；以及在钝化层上并且在开口中的导电焊盘结构。导电焊盘结构包括在开口的侧壁上以及在开口外部的钝化层的表面上的下导电层。下导电层包括顺序地堆叠的第一籽晶层、蚀刻停止层和第二籽晶层。导电焊盘结构还包括在开口中直接在第二籽晶层上的第一焊盘层、以及在开口外部直接在第一籽晶层上的第二焊盘层。第一焊盘层与第一籽晶层通过第二籽晶层、蚀刻停止层和/或第二焊盘层的部分隔开，并且第二焊盘层的顶表面基本上是平坦的。
附图说明
本发明构思的实施方式将由以下结合附图的详细描述被更清楚地理解，附图中：
图1是根据一些实施方式的半导体器件的截面图；
图2是图1是部分II的放大截面图；
图3是图2的部分III的放大截面图；
图4至14是根据一些实施方式的半导体器件的截面图；
图15A和15B是根据比较示例的半导体器件的截面图；
图16是根据一些实施方式的半导体封装的截面图；
图17是图16的部分B的放大图；以及
图18至25是根据一些实施方式的制造半导体器件的方法的截面图。
具体实施方式
现在将参照附图更全面地描述本发明构思，附图中示出了本发明构思的实施方式。
图1是根据一些实施方式的半导体器件100的截面图。图2是图1的部分II的放大截面图。图3是图2的部分III的放大截面图。
参照图1至3，基板110可以包括第一表面110S1和作为第一表面110S1的背面的第二表面110S2。虽然这里可以使用术语第一、第二等来描述各种元件，但是这些术语仅用于将一个元件与另一元件区分开，并且这些元件不应受这些术语限制。因此，第一元件可以被称为第二元件而不脱离本发明构思的范围。基板110可以包括例如硅(Si)。基板110可以包括诸如锗(Ge)的半导体元素、或诸如硅碳化物(SiC)、镓砷化物(GaAs)、铟砷化物(InAs)和铟磷化物(InP)的化合物半导体。基板110可以具有绝缘体上硅(SOI)结构。例如，基板110可以包括掩埋氧化物(BOX)层。基板110可以包括例如掺杂阱或掺杂结构的导电区域。此外，基板110可以具有各种隔离结构中的一种，诸如浅沟槽隔离(STI)结构。
半导体器件层120可以位于基板110的第二表面110S2上。被称为“在”另一元件(例如一层或基板)“上”或者“连接到”或“邻近”另一元件(例如一层或基板)的一元件可以直接在所述另一个元件上或者直接连接到或邻近所述另一元件，或者也可以存在居间元件。相反，当一元件被称为“直接在”另一元件“上”或者“直接连接”或“直接邻近”另一元件时，没有居间元件存在。半导体器件层120可以包括各种类型的多个单独器件以及层间绝缘膜。多个单独器件可以包括各种微电子器件，例如，诸如互补金属-绝缘体-半导体(CMOS)晶体管的金属氧化物半导体场效应晶体管(MOSFET)、系统大规模集成(系统LSI)、闪速存储器、动态随机存取存储器(DRAM)、静态RAM(SRAM)、电可擦除可编程只读存储器(EEPROM)、相变RAM(PRAM)、磁阻RAM(MRAM)或电阻RAM(RRAM)、诸如CMOS成像传感器(CIS)的图像传感器、微机电系统(MEMS)、有源器件和/或无源器件。多个单独器件可以形成在半导体器件层120中并且电连接到基板110的导电区域。半导体器件层120还可以包括配置为将多个单独器件中的至少两个电连接或者将多个单独器件与基板110的导电区域电连接的导电互连或导电插塞。此外，多个单独器件的每个可以通过绝缘膜与其它相邻的单独器件电隔离。
如图2中所示，半导体器件层120可以包括配置为将多个单独器件与形成在基板110中的其它互连连接的多个互连结构122。多个互连结构122的每个可以包括金属互连层124和通路插塞126。金属互连层124和通路插塞126可以包括互连阻挡膜和互连金属层。互连阻挡膜可以包括钛(Ti)、钛氮化物(TiN)、钽(Ta)或钽氮化物(TaN)中的至少一种。互连金属层可以包括钨(W)、铝(Al)或铜(Cu)中的至少一种金属。金属互连层124和通路插塞126可以包括相同的材料。或者，金属互连层124和通路插塞126的至少部分可以包括不同的材料。金属互连层124和/或通路插塞126可以包括多层结构。就是说，多个互连结构122的每个可以具有通过交替地堆叠至少两个金属互连层124或至少两个通路插塞126而获得的多层结构。
贯穿基板通路(TSV)130可以从基板110的第一表面110S1延伸到第二表面110S2并延伸到半导体器件层120中。TSV 130的至少一部分可以具有柱形。TSV 130可以包括形成在TSV 130的柱形部分的表面上的阻挡膜132、以及填充阻挡膜132的内部的掩埋导电层134。阻挡膜132可以包括钛(Ti)、钛氮化物(TiN)、钽(Ta)、钽氮化物(TaN)、钌(Ru)、钴(Co)、锰(Mn)、钨氮化物(WN)、镍(Ni)或镍硼(NiB)中的至少一种，掩埋导电层134可以包括Cu、Cu合金(例如CuSn、CuMg、CuNi、CuZn、CuPd、CuAu、CuRe和CuW)、W、W合金、Ni、Ru或Co中的至少一种。通路绝缘膜136可以插置在基板110与TSV 130之间以及半导体器件层120与TSV130之间。通路绝缘膜136可以包括氧化物膜、氮化物膜、碳化物膜、聚合物或其组合。
连接焊盘142可以位于半导体器件层120上并电连接到半导体器件层120中的多个互连结构。连接焊盘142可以通过多个互连结构122电连接到TSV 130。连接焊盘142可以包括铝(Al)、铜(Cu)、镍(Ni)、钨(W)、铂(Pt)或金(Au)中的至少一种。
第一钝化层144可以形成在半导体器件层120上以覆盖连接焊盘142的顶表面的至少一部分。第一钝化层144可以是配置为保护半导体器件层120中包括的多个互连结构122以及位于其下的其它结构免受外部冲击和湿气影响的保护层。例如，第一钝化层144可以包括无机绝缘膜或有机绝缘膜。在一些实施方式中，第一钝化层144可以包括硅氮化物。开口144H可以形成在第一钝化层144中以暴露连接焊盘142的顶表面的至少一部分。
连接凸块146可以位于连接焊盘142和第一钝化层144上。连接凸块146可以位于半导体器件100的最下表面上。连接凸块146可以是配置为将半导体器件100安装在外部基板或转接板(interposer)上或者将半导体器件100接合到另一半导体器件100的连接构件。连接凸块146可以从外部(例如外部器件)接收用于半导体器件100的操作的控制信号、电源信号或地信号中的至少一个，从外部接收将存储在半导体器件100中的数据信号，或者将存储在半导体器件100中的数据提供到外部。
在一些实施方式中，连接凸块146的每个可以包括单个层或多个材料层的堆叠结构。例如，连接凸块146可以包括含锡(Sn)、铟(In)、铋(Bi)、锑(Sb)、铜(Cu)、银(Ag)、锌(Zn)、铅(Pb)和/或其合金的焊料材料。例如，焊料材料可以包括Sn、Pb、Sn-Pb、Sn-Ag、Sn-Au、Sn-Cu、Sn-Bi、Sn-Zn、Sn-Ag-Cu、Sn-Ag-Bi、Sn-Ag-Zn、Sn-Cu-Bi、Sn-Cu-Zn和/或Sn-Bi-Zn。
在另外的实施方式中，连接凸块146可以包括连接到连接焊盘142的焊料层以及形成在柱层上的焊料层。例如，柱层可以包括镍(Ni)、铜(Cu)、钯(Pd)、铂(Pt)、金(Au)或其合金。焊料层可以包括含锡(Sn)、铟(In)、铋(Bi)、锑(Sb)、铜(Cu)、银(Ag)、锌(Zn)、铅(Pb)/或其合金的焊料材料。
再分布结构150可以位于基板110的第一表面110S1上并电连接到TSV130。再分布结构150可以包括多个再分布线152。多个再分布线152可以位于自基板110的第一表面110S1起或相对于基板110的第一表面110S1的不同的水平处，或者可以位于相同的水平处。多个再分布线152可以通过再分布通路154彼此连接。
多个再分布线152可以包括铜(Cu)、铝(Al)、钨(W)、镍(Ni)、钛(Ti)、钛氮化物(TiN)、钽(Ta)、钽氮化物(TaN)、金(Au)或其组合。再分布通路154可以包括铜(Cu)、铝(Al)、钨(W)、镍(Ni)、钛(Ti)、钛氮化物(TiN)、钽(Ta)、钽氮化物(TaN)、金(Au)或其组合。再分布通路154可以通过利用与形成多个再分布线152的工艺不同的工艺而形成。然而，在另一种情况下，再分布通路154可以通过利用与多个再分布线152相同的工艺而形成。例如，用于形成再分布线152的开口和用于形成再分布通路154的开口可以在相同的工艺期间用导电材料填充，使得再分布通路154可以与多个再分布线152中的一个成一体。
再分布绝缘层156可以形成在基板110的第一表面110S1上以覆盖再分布结构150。再分布绝缘层156可以包括多个绝缘层的堆叠结构。再分布绝缘层156可以包括光敏聚酰亚胺、硅氮化物、硅氧化物、硅氮氧化物或其组合。
第二钝化层158可以形成于再分布绝缘层156上。第二钝化层158可以包括暴露再分布线152的至少一部分的开口158H。第二钝化层158可以包括光敏聚酰亚胺、硅氮化物、硅氧化物、硅氮氧化物或其组合。第二钝化层158可以包括与再分布绝缘层156相同的材料，或者包括与再分布绝缘层156不同的材料。
焊盘结构160可以形成在第二钝化层158上并电连接到再分布线152。焊盘结构160可以包括第一焊盘层162、第二焊盘层164、盖层166和下导电层170。
如图3中所示，下导电层170可以共形地形成在第二钝化层158、开口158H的侧壁上以及在由开口158H暴露的再分布线152的顶表面上。下导电层170可以包括导电阻挡层172、第一籽晶层174、蚀刻停止层176和第二籽晶层178。
导电阻挡层172可以用作防止焊盘结构160中包括的金属材料渗透或扩散到第二钝化层158或再分布绝缘层156中的阻挡物。此外，导电阻挡层172可以用作能够提供第一籽晶层174与第二钝化层158的充分附接的附接层。在一些实施方式中，导电阻挡层172可以包括钛(Ti)、钛氮化物(TiN)、钽(Ta)、钽氮化物(TaN)、钛-钨(Ti-W)、铬(Cr)、铝(Al)或其组合。例如，导电阻挡层172可以包括钛(Ti)。在一些实施方式中，导电阻挡层172可以具有约
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的厚度，但本发明构思不限于此。
第一籽晶层174可以充当用于形成位于第二钝化层158的顶表面上的第二焊盘层164的籽晶层或模板。在一些实施方式中，第一籽晶层174可以包括铜(Cu)、铬-铜(Cr-Cu)、钯(Pd)、铂(Pt)、金(Au)或其组合。在一些实施方式中，第一籽晶层174可以包括铜(Cu)。在一些实施方式中，虽然第一籽晶层174可以具有约
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的厚度，但本发明构思不限于此。
蚀刻停止层176可以包括相对于第一焊盘层162具有蚀刻选择性的材料。例如，蚀刻停止层176可以在回蚀刻填充开口158H的第一焊盘层162的工艺期间用作蚀刻停止部。在一些实施方式中，蚀刻停止层176可以包括钛(Ti)、钛氮化物(TiN)、钽(Ta)、钽氮化物(TaN)、钛-钨(Ti-W)、铬(Cr)、铝(Al)或其组合。在一些实施方式中，蚀刻停止层176可以包括钛(Ti)。在一些实施方式中，蚀刻停止层176可具有约
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的厚度，但本发明构思不限于此。
第二籽晶层178可以充当用于形成第一焊盘层162的籽晶层或模板。在一些实施方式中，第二籽晶层178可以包括铜(Cu)、铬-铜(Cr-Cu)、钯(Pd)、铂(Pt)、金(Au)或其组合。在一些实施方式中，第二籽晶层178可以包括铜(Cu)。在一些实施方式中，第二籽晶层178可以具有约
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Figure BDA0001735771440000076
的厚度，但本发明构思不限于此。
第一焊盘层162可以在下导电层170上填充开口158H的剩余空间。第一焊盘层162可以包括铜(Cu)、铬-铜(Cr-Cu)、钯(Pd)、铂(Pt)、金(Au)或其组合。第二焊盘层164可以形成在第二钝化层158上以覆盖第一焊盘层162。第二焊盘层164可以包括镍(Ni)、铝(Al)、钨(W)、铂(Pt)、金(Au)或其组合。盖层166可以形成在第二焊盘层164的顶表面上。盖层166可以包括金(Au)、铂(Pt)、银(Ag)、钨(W)或其组合。
如图3中所示，第一焊盘层162可以沿着平行于基板110的第一表面110S1的第一方向具有第一宽度W1，第二焊盘层164可以沿着第一方向具有大于第一宽度W1的第二宽度W2。此外，第二焊盘层164可以基本上覆盖第一焊盘层162的整个顶表面。因此，第一焊盘层162可以不暴露于焊盘结构160外部。
例如，当第一焊盘层162中包括的金属材料(例如铜(Cu))被焊盘结构160的外侧壁暴露时，金属材料可以在接合半导体器件的工艺期间接触位于焊盘结构160上的焊料材料并与其反应，从而产生金属间化合物(IMC)。当产生IMC时，焊料材料中会形成空隙，并且半导体器件的接合可靠性会劣化。然而，根据一些实施方式，因为第一焊盘层162的顶表面由第二焊盘层164完全覆盖，所以可以减少或防止上述IMC的产生，使得半导体器件100可以可靠地接合到另一半导体器件。
如图3中所示，下导电层170可以包括围绕第一焊盘层162的侧壁和底表面的第一部分170a、以及位于第二焊盘层164与第二钝化层158之间的第二部分170b。下导电层170的第一部分170a可以具有导电阻挡层172、第一籽晶层174、蚀刻停止层176和第二籽晶层178的堆叠结构。相反，下导电层170的第二部分170b(例如下导电层170的位于第二钝化层158上的外围部分)可以具有仅导电阻挡层172和第一籽晶层174的堆叠结构。因此，下导电层170的第一部分170a的第一厚度t1可以大于下导电层170的第二部分170b的第二厚度t2。这里，第一厚度t1和第二厚度t2的每个可以是指下导电层170在与下导电层170延伸的方向垂直的方向上的厚度。下导电层170的第二部分170b可以由于以下事实而具有比第一部分170a更小的厚度：在通过利用蚀刻停止层176作为蚀刻停止部而回蚀刻第一焊盘层162的工艺期间，第二部分170b中的第二籽晶层178被一起去除，并且随后第二部分170b中的蚀刻停止层176也被去除。
如图3中所示，第二焊盘层164可以包括第一部分164a和第二部分164b。第二焊盘层164的第一部分164a可以与第一焊盘层162的顶表面接触，第二焊盘层164的第二部分164b可以与第一籽晶层174的顶表面接触。这可以是由于以下事实：如上所述，在通过利用刻蚀停止层176作为蚀刻停止部而回蚀刻第一焊盘层162的工艺期间，第二部分170b中的第二籽晶层178被一起去除，并且随后第二部分170b中的蚀刻停止层176也被去除。
在根据一些实施方式的形成第二焊盘层164的工艺中，在蚀刻停止层176被去除之后，第一籽晶层174可以被暴露，并且第二焊盘层164可以通过利用第一籽晶层174和第一焊盘层162作为籽晶层而形成。具体地，因为第二焊盘层164的外围部分(即第二部分164b)通过利用第一籽晶层174作为籽晶层而形成，所以第二焊盘层164的整个区域可以形成至相对一致的高度并具有基本上平坦的顶表面。
如图3中所示，第二焊盘层164的第一部分164a的底部水平LV1可以基于或相对于基板110的第一表面110S1高于第二焊盘层164的第二部分164b的底部水平LV2。此外，第二焊盘层164的第一部分164a的底部水平LV1和第二焊盘层164的第二部分164b的底部水平LV2可以基于或相对于基板110的第一表面110S1高于第二钝化层158的顶部水平LV3。除了图中所绘的取向之外，诸如“在……之下”、“在……下面”、“下部”、“高于”、“在……上方”、“上部”等空间关系术语还可以涵盖装置在使用或操作中的不同取向。例如，如果图中的装置被翻转，则被描述为“在”另外的元件或特征“下面”或“之下”的元件将被取向为在所述另外的元件或特征“上方”。
换言之，第一焊盘层162的顶表面可以在与第二焊盘层164的第一部分164a的底部水平LV1基本相同的水平或相似的水平处。此外，围绕第一焊盘层162的侧壁和底表面的第二籽晶层178的最上表面可以在与第二焊盘层164的第一部分164a的底部水平LV1基本相同的水平或相似的水平处。在形成第一焊盘层162的工艺中，在第一焊盘层162被形成以填充开口158H之后，由于回蚀刻第一焊盘层162和第二籽晶层178直到蚀刻停止层176的顶表面被暴露的工艺，第一焊盘层162的顶表面可以变成与第二籽晶层178的顶表面共面。
如图3中所示，底切区域170U可以在第二焊盘层164的外围部分(例如第二焊盘层164的第二部分164b)与第二钝化层158之间被限定在从其去除了第一籽晶层174和导电阻挡层172的边缘部分的位置处。如上所述，底切区域170U可以由于以下事实而被限定：在第二焊盘层164形成之后，在去除形成于第二钝化层158的顶表面上的第一籽晶层174和导电阻挡层172的工艺期间，第一籽晶层174和导电阻挡层172的边缘部分也可以一起被去除。在去除工艺期间，第二焊盘层164的边缘部分也一起被去除，使得台阶部分164S可以形成在第二焊盘层164的边缘部分中。
在一些实施方式中，如图3中所示，导电阻挡层172的邻近于底切区域170U的侧表面可以比第一籽晶层174的侧表面向内凹入得更多。换言之，导电阻挡层172的位于第二钝化层158的顶表面上的部分的长度可以小于第一籽晶层174的位于第二钝化层158的顶表面上的部分的长度，使得第一籽晶层174延伸超过导电阻挡层172。这可以是由于以下事实：在第二焊盘层164形成之后，在通过利用湿蚀刻工艺顺序地去除第一籽晶层174的未由第二焊盘层164覆盖的部分和导电阻挡层172的未由第二焊盘层164覆盖的部分的工艺期间，导电阻挡层172的位于第二焊盘层164的外围部分下方的部分可以被进一步去除。然而，本发明构思不限于此。例如，与图3相比，导电阻挡层172和第一籽晶层174的侧表面可以彼此对准。换言之，导电阻挡层172的位于第二钝化层158的顶表面上的部分的长度可以等于第一籽晶层174的位于第二钝化层158的顶表面上的部分的长度。
在一些实施方式中，围绕第一焊盘层162的侧壁的蚀刻停止层176的最上表面可以相对于基板110的第一表面110S1在比第二籽晶层178的最上水平(例如与第二焊盘层164的第一部分164a的底部水平LV1基本相等或相似的水平)更低的水平处。此外，围绕第一焊盘层162的侧壁的蚀刻停止层176的最上表面可以相对于基板110的第一表面110S1在比第一籽晶层174的最上水平(例如与第二焊盘层164的第二部分164b的底部水平LV2基本相等或相似的水平)更低的水平处。这可以是由于以下事实：在第一焊盘层162形成之后，在通过利用湿刻蚀工艺顺序地去除第二籽晶层178的未由第一焊盘层162覆盖的部分和蚀刻停止层176的未由第一焊盘层162覆盖的部分的工艺期间，围绕第一焊盘层162的侧壁的蚀刻停止层176的一部分可以被进一步去除。或者，与图3相比，围绕第一焊盘层162的侧壁的蚀刻停止层176的最上表面可以在与第一籽晶层174的最上水平基本相同的水平处。
图3示出第二钝化层158的开口158H暴露再分布线152的一部分并且焊盘结构160在开口158H中与再分布线152接触的示例。然而，在另外的实施方式中，再分布绝缘层156可以包括暴露TSV 130的顶表面的开口，并且焊盘结构160可以在该开口中与TSV 130的顶表面接触，使得再分布结构150不被设置在焊盘结构160与TSV 130之间。
虽然图2示出连接焊盘142包括单个层的示例，但本发明构思不限于此。连接焊盘142也可以具有与焊盘结构160相似的结构。例如，包括下导电层170、第一焊盘层162、第二焊盘层164和盖层166的焊盘结构160可以代替连接焊盘142形成在基板110的第二表面110S2上，并且连接凸块146可以形成在焊盘结构160上。
在下文中，根据一些实施方式的半导体器件100的焊盘结构160的特性将与图15A和15B的器件相比较而被描述。
图15A和15B是根据比较示例的半导体器件100X1和100X2的截面图。
参照图15A，半导体器件100X1可以包括含上焊盘层164X1和下导电层170X的焊盘结构160X1。下导电层170X可以包括导电阻挡层172X和籽晶层174X，并且上焊盘层164X1可以形成在下导电层170X上以填充第二钝化层158的开口158H。凹陷164X1_R可以被提供在上焊盘层164X1的上部中。由于第二钝化层158的顶表面与开口158H的底表面之间相对大的高度差，在用上焊盘层164X1填充开口158H的工艺期间，在上焊盘层164X1的顶表面中会出现水平差异，从而产生凹陷164X1_R。在将半导体器件100X1接合到另一半导体器件的连接凸块的工艺中，诸如底部填充构件的有机材料的残留物会被俘获在凹陷164X1_R中，从而使半导体器件100X1的接合可靠性劣化。
参照图15B，半导体器件100X2可以包括含下焊盘层162X2、上焊盘层164X2和下导电层170X的焊盘结构160X2。下导电层170X可以包括导电阻挡层172X和籽晶层174X，并且下焊盘层162X2可以形成在下导电层170X上以填充第二钝化层158的开口158H。上焊盘层164X2可以形成在下焊盘层162X2上。上焊盘层164X2可以不与下导电层170X直接接触，并且下焊盘层162X2可以被焊盘结构160X2的侧壁暴露。下焊盘层162X2可以具有相对好的间隙填充特性。因此，下焊盘层162X2可以具有平坦的顶表面而不受第二钝化层158的顶表面与开口158H的底表面之间相对高的高度差影响。因此，上焊盘层164X2也可以具有与下焊盘层162X2的顶表面的形状相符的平坦的顶表面。然而，在将半导体器件100X2接合到另一半导体器件的连接凸块的工艺中，连接凸块中包括的焊料材料可以沿着焊盘结构160X2的侧壁流动并且接触下焊盘层162X2并与其反应从而产生IMC。当产成IMC时，焊料材料中会形成空隙，并且半导体器件100X2的接合可靠性会劣化。
相反，在根据参照图1至3描述的实施方式的半导体器件100中，第一焊盘层162和第二焊盘层164可以形成在包括导电阻挡层172、第一籽晶层174、蚀刻停止层176和第二籽晶层178的下导电层170上。具体地，在制造半导体器件100的工艺中，第一焊盘层162可以被回蚀刻直到蚀刻停止层176的顶表面被暴露，并且蚀刻停止层176的暴露部分可以被去除以暴露第一籽晶层174的位于第二钝化层158的顶表面上的部分。此后，第二焊盘层164可以通过利用第一焊盘层162和第一籽晶层174作为籽晶层而形成。因此，第二焊盘层164的顶表面的整个区域可以基本上是平坦的。因此，在将半导体器件100与另一半导体器件接合的工艺期间，可以减少或防止有机材料被俘获到焊料层中。此外，因为第一焊盘层162不被暴露于焊盘结构160外部，所以可以减少或防止由焊料层与第一焊盘层162的接触所致的金属间化合物(IMC)的产生。因此，半导体器件100可以具有更高的可靠性。
图4是根据一些实施方式的半导体器件100A的截面图。在图4中，相同的附图标记用于表示与图1至3中相同的元件。
参照图4，焊盘结构160A可以包括具有不同顶部轮廓的第一焊盘层162A和第二焊盘层164A。第一焊盘层162A可以具有凸形顶部轮廓，并且第二焊盘层164A可以具有与第一焊盘层162A的顶部轮廓相符的凹形底部轮廓。例如，第一焊盘层162A的中央部分的顶部水平LV4A可以相对于基板110的第一表面110S1高于第一焊盘层162A的外围部分的顶部水平LV5A。
在根据一些实施方式的形成焊盘结构160A的工艺中，在具有连接到开口158H的焊盘空间(参照图20中的410H)的模层(参见图20中的410)形成于第二钝化层158上之后，第一焊盘层162A可以被形成以填充开口158H和焊盘空间410H，并且被回蚀刻直到蚀刻停止层176的顶表面被暴露。在这种情况下，取决于焊盘空间410H的宽度或深度或者回蚀刻工艺条件，蚀刻速率的差异可以在第一焊盘层162A中局部地发生。例如，第一焊盘层162A的外围部分可以以相对高的蚀刻速率被回蚀刻。因此，第一焊盘层162A可以具有凸形顶部轮廓。
图5是根据一些实施方式的半导体器件100B的截面图。在图5中，相同的附图标记用于表示与图1至4中相同的元件。
参照图5，焊盘结构160B可以包括具有不同顶部轮廓的第一焊盘层162B和第二焊盘层164B。第一焊盘层162B可以具有凹形顶部轮廓，并且第二焊盘层164B可以具有与第一焊盘层162B的顶部轮廓相符的凸形底部轮廓。例如，第一焊盘层162B的中央部分的顶部水平LV4B可以相对于基板110的第一表面110S1低于第一焊盘层162B的外围部分的顶部水平LV5。
在根据一些实施方式的形成焊盘结构160B的工艺中，在具有连接到开口158H的焊盘空间(参照图20中的410H)的模层(参照图20中的410)形成于第二钝化层158上之后，第一焊盘层162A可以被形成以填充开口158H和焊盘空间410H，并且被回蚀刻直到蚀刻停止层176的顶表面被暴露。在这种情况下，取决于焊盘空间410H的宽度或深度或者回蚀刻工艺条件，蚀刻速率的差异可以在第一焊盘层162B中局部地发生。例如，第一焊盘层162B的中央部分可以以相对高的蚀刻速率被回蚀刻。因此，第一焊盘层162B可以具有凹形顶部轮廓。
图6是根据一些实施方式的半导体器件100C的截面图。在图6中，相同的附图标记用于表示与图1至5中相同的元件。
参照图6，焊盘结构160C可以包括具有不同顶部水平的第一焊盘层162C和蚀刻停止层176。围绕第一焊盘层162C的侧壁的蚀刻停止层176的最上水平LV6可以相对于基板110的第一表面110S1低于第二籽晶层178的最上水平(例如与第二焊盘层164C的第一部分164a的底部水平LV1基本相等或相似的水平)。此外，围绕第一焊盘层162C的侧壁的蚀刻停止层176的最上水平LV6可以高于第一籽晶层174的最上水平(例如与第二焊盘层164的第二部分164b的底部水平LV2基本相等或相似的水平)。
图7是根据一些实施方式的半导体器件100D的截面图。在图7中，相同的附图标记用于表示与图1至6中相同的元件。
参照图7，焊盘结构160D可以包括具有不同顶部水平的第一焊盘层162D和蚀刻停止层176。第一焊盘层162D可以具有凸形顶部轮廓，并且第二焊盘层164D可以具有与第一焊盘层162D的顶部轮廓相符的凹形底部轮廓。例如，第一焊盘层162D的中央部分的顶部水平LV4D可以相对于基板110的第一表面110S1高于第一焊盘层162D的外围部分的顶部水平LV5D。
此外，围绕第一焊盘层162D的侧壁的蚀刻停止层176的最上水平LV6D可以相对于基板110的第一表面110S1低于第一焊盘层162D的外围部分的顶部水平LV5D。
图8是根据一些实施方式的半导体器件100E的截面图。在图8中，相同的附图标记用于表示与图1至7中相同的元件。
参照图8，焊盘结构160E可以包括具有不同顶部水平的第一焊盘层162E和蚀刻停止层176。第一焊盘层162E可以具有凹形顶部轮廓，并且第二焊盘层164E可以具有与第一焊盘层162E的顶部轮廓相符的凸形底部轮廓。例如，第一焊盘层162E的中央部分的顶部水平LV4E可以相对于基板110的第一表面110S1低于第一焊盘层162E的外围部分的顶部水平LV5E。此外，围绕第一焊盘层162E的侧壁的蚀刻停止层176的最上水平LV6E可以相对于基板110的第一表面110S1低于第一焊盘层162E的外围部分的顶部水平LV5E。图8示出围绕第一焊盘层162E的侧壁的蚀刻停止层176的最上水平LV6E相对于基板110的第一表面110S1高于第一焊盘层162E的中央部分的顶部水平LV4E的示例。然而，在另一情况下，蚀刻停止层176的最上水平LV6E可以相对于基板110的第一表面110S1低于第一焊盘层162E的中央部分的顶部水平LV4E。
图9是根据一些实施方式的半导体器件100F的截面图。在图9中，相同的附图标记用于表示与图1至8中相同的元件。
参照图9，焊盘结构160F可以包括第一焊盘层162F，第一焊盘层162F包括在第二钝化层158的顶表面上延伸的突起162o。突起162o可以位于第一焊盘层162F的外围部分中并在第二钝化层158的顶表面上向外延伸。导电阻挡层172、第一籽晶层174、蚀刻停止层176和第二籽晶层178可以顺序地位于第二钝化层158与突起162o之间。
下导电层170A可以包括第一部分170a、第二部分170b和第三部分170c。第一部分170a可以在开口158H的内壁或侧壁上围绕第一焊盘层162F的侧壁和底表面。第二部分170b可以位于第二钝化层158与第二焊盘层164F的第二部分164b之间。第三部分170c可以位于第二钝化层158与第一焊盘层162F的突起162o之间。底切区域174U可以形成在突起162o的外围部分下方，并且在底切区域174U中，蚀刻停止层176的侧表面可以比第二籽晶层178的侧表面向内凹入更多。
下导电层170A的第一部分170a和第三部分170c可以具有导电阻挡层172、第一籽晶层174、蚀刻停止层176和第二籽晶层178的堆叠结构。相反，下导电层170A的第二部分170b可以具有仅导电阻挡层172和第一籽晶层174的堆叠结构。因此，下导电层170A的第一部分170a的第一厚度t1和下导电层170A的第三部分170c的第三厚度t3的每个可以大于下导电层170A的第二部分170b的第二厚度t2。
如图9中所示，第二焊盘层164F的第一部分164a的底部水平LV1F可以基于或者相对于基板110的第一表面110S1高于第二焊盘层164F的第二部分164b的底部水平LV2F。
图10是根据一些实施方式的半导体器件100G的截面图。在图10中，相同的附图标记用于表示与图1至9中相同的元件。
参照图10，焊盘结构160G可以包括第一焊盘层162G，第一焊盘层162G包括在第二钝化层158的顶表面上延伸的突起162o。第一焊盘层162G可以具有凸形顶部轮廓。第二焊盘层164G可以具有与第一焊盘层162G的顶部轮廓相符的凹形底部轮廓。例如，第一焊盘层162G的中央部分的顶部水平LV4G可以相对于基板110的第一表面110S1高于第一焊盘层162G的外围部分的顶部水平LV5G。
突起162o可以位于第一焊盘层162G的外围部分中并在第二钝化层158的顶表面上向外延伸。导电阻挡层172、第一籽晶层174、蚀刻停止层176和第二籽晶层178可以顺序地位于第二钝化层158与突起162o之间。
图11是根据一些实施方式的半导体器件100H的截面图。在图11中，相同的附图标记用于表示与图1至10中相同的元件。
参照图11，焊盘结构160H可以包括第一焊盘层162H，第一焊盘层162H包括在第二钝化层158的顶表面上延伸的突起162o。第一焊盘层162H可以具有凹形顶部轮廓。第二焊盘层164H可以具有与第一焊盘层162H的顶部轮廓相符的凸形底部轮廓。例如，第一焊盘层162H的中央部分的顶部水平LV4H可以相对于基板110的第一表面110S1低于第一焊盘层162H的外围部分的顶部水平LV5H。
图12是根据一些实施方式的半导体器件100I的截面图。在图12中，相同的附图标记用于表示与图1至11中相同的元件。
参照图12，焊盘结构160I可以包括第一焊盘层162I和位于第一焊盘层162I上的第二焊盘层164I，第一焊盘层162I具有位于比第二钝化层158的顶表面更低的水平处的顶表面。第二焊盘层164I的第一部分164a的底部水平LV1I可以基于或者相对于基板110的第一表面110S1低于第二焊盘层164I的第二部分164b的底部水平LV2I。此外，第二焊盘层164I的第一部分164a的底部水平LV1I可以基于或者相对于基板110的第一表面110S1低于第二钝化层158的顶部水平LV3。
换言之，第一焊盘层162I的顶表面可以基于或者相对于基板110的第一表面110S1在比第二钝化层158的顶部水平LV3更低的水平处。此外，围绕第一焊盘层162I的侧壁和底表面的第二籽晶层178的最上表面可以相对于基板110的第一表面110S1在比第二钝化层158的顶部水平LV3更低的水平处。
在根据一些实施方式的形成焊盘结构160I的工艺中，在第一焊盘层162I可以形成为填充开口158H之后，第一焊盘层162I和第二籽晶层178可以被回蚀刻直到蚀刻停止层176的顶表面被暴露。在蚀刻停止层176的顶表面被暴露之后，第一焊盘层162I和第二籽晶层178可以被过度蚀刻多达预定高度。在这种情况下，第一焊盘层162I和第二籽晶层178可以具有相对于基板110的第一表面110S1位于比第一籽晶层174的顶表面更低的水平处的顶表面。
图13是根据一些实施方式的半导体器件100J的截面图。在图13中，相同的附图标记用于表示与图1至12中相同的元件。
参照图13，焊盘结构160J可以包括具有凸形顶部轮廓的第一焊盘层162J、以及具有与第一焊盘层162J的顶部轮廓相符的凹形底部轮廓的第二焊盘层164J。例如，第一焊盘层162J的中央部分的顶部水平LV4J可以相对于基板110的第一表面110S1高于第一焊盘层162J的外围部分的顶部水平LV5J。图13示出相对于基板110的第一表面110S1，第一焊盘层162J的中央部分的顶部水平LV4J高于第二钝化层158的顶部水平LV3并且第一焊盘层162J的外围部分的顶部水平LV5J低于第二钝化层158的顶部水平LV3的示例。或者，与图13相比，第一焊盘层162J的中央部分的顶部水平LV4J和第一焊盘层162J的外围部分的顶部水平LV5J两者可以相对于基板110的第一表面110S1低于第二钝化层158的顶部水平LV3。
图14是根据一些实施方式的半导体器件100K的截面图。在图14中，相同的附图标记用于表示与图1至13中相同的元件。
参照图14，焊盘结构160K可以具有拥有凹形顶部轮廓的第一焊盘层162K以及拥有与第一焊盘层162K的顶部轮廓相符的凸形底部轮廓的第二焊盘层164K。例如，第一焊盘层162K的中央部分的顶部水平LV4K可以相对于基板110的第一表面110S1低于第一焊盘层162K的外围部分的顶部水平LV5K。第一焊盘层162K的中央部分的顶部水平LV4K和第一焊盘层162K的外围部分的顶部水平LV5K两者可以相对于基板110的第一表面110S1低于第二钝化层158的顶部水平LV3。
图16是根据一些实施方式的半导体封装1的截面图。图17是图16的部分B的放大图。在图16和17中，相同的附图标记用于表示与图1至14中相同的元件。
参照图16和17，半导体封装1可以包括可安装在封装基板210上的缓冲芯片D0以及第一至第四半导体芯片C1、C2、C3和C4。可选地，可以省略插置在封装基板210与第一至第四半导体芯片C1、C2、C3和C4之间的缓冲芯片D0，并且第一半导体芯片C1可以直接位于封装基板210上并连接到封装基板210。
第一至第四半导体芯片C1、C2、C3和C4可以具有与参照图1至14描述的半导体器件100、100A、100B、100C、100D、100E、100F、100G、100H、100I、100J和/或100K的特性相似的特性。
第一至第四半导体芯片C1、C2、C3和C4可以是例如半导体存储芯片。半导体存储芯片可以是例如诸如动态随机存取存储器(DRAM)或静态随机存取存储器(SRAM)的易失性半导体存储芯片、或诸如相变RAM(PRAM)、磁阻RAM(MRAM)、铁电RAM(FeRAM)或电阻RAM(RRAM)的非易失性半导体存储芯片。在一些实施方式中，第一至第四半导体芯片C1、C2、C3和C4可以是高带宽存储(HBM)DRAM半导体芯片。
缓冲芯片D0可以包括缓冲基板310、第一层间绝缘膜320、缓冲TSV330、缓冲连接焊盘342、缓冲连接凸块346、第二层间绝缘膜356和缓冲上连接焊盘360。缓冲TSV 330可以从缓冲基板310的顶表面穿透至底表面并延伸到第一层间绝缘膜320和/或第二层间绝缘膜356中。多个互连结构可以形成在第一层间绝缘膜320中并电连接到缓冲TSV 330。
缓冲芯片D0可以是不包括第一至第四半导体芯片C1、C2、C3和C4的每个中包括的单独器件的虚设半导体芯片。缓冲芯片D0可以是能够通过缓冲TSV 330从外部接收用于第一至第四半导体芯片C1、C2、C3和C4的操作的控制信号、电源信号或地信号中的至少一个、从外部接收将存储在半导体芯片C1、C2、C3和C4中的数据信号、或者将存储在半导体芯片C1、C2、C3和C4中的数据提供到外部的缓冲管芯。
绝缘层370可以形成在第一至第四半导体芯片C1、C2、C3和C4之间以及第一半导体芯片C1与缓冲芯片D0之间。绝缘层370可以包括诸如绝缘聚合物、环氧树脂和/或非导电膜(NCF)的底部填充材料。第一模制层375可以围绕第一至第四半导体芯片C1、C2、C3和C4的侧表面以及绝缘层370的侧表面。第一模制层375可以包括环氧塑封料(EMC)。
封装基板210可以是例如印刷电路板(PCB)、陶瓷基板或转接板。当封装基板210是PCB时，封装基板210可以包括基板基底212以及分别形成在基板基底212的顶表面和底表面上的顶部焊盘214和底部焊盘216。顶部焊盘214和底部焊盘216可以分别由覆盖基板基底212的顶表面和底表面的阻焊层暴露。基板基底212可以包括酚醛树脂、环氧树脂或聚酰亚胺中的至少一种。例如，基板基底212可以包括FR4、四官能环氧树脂、聚苯醚、环氧树脂/聚苯醚、双马来酰亚胺三嗪(BT)、
Figure BDA0001735771440000181
氰酸酯、聚酰亚胺或液晶聚合物中的至少一种。顶部焊盘214和底部焊盘216可以包括铜、镍、不锈钢和/或铍铜。内部连接可以形成在基板基底212中以电连接顶部焊盘214和底部焊盘216。当电路互连通过用铜(Cu)箔涂覆基板基底212的顶表面和底表面并图案化铜箔而形成时，顶部焊盘214和底部焊盘216可以是电路互连的由阻焊层暴露的部分。
当封装基板210是转接板时，封装基板210可以包括基板基底212，基板基底212包括半导体材料以及分别形成在基板基底212的顶表面和底表面上的顶部焊盘214和底部焊盘216。基板基底212可以包括例如硅晶片。此外，内部互连可以形成在基板基底212的顶表面或底表面上或者在基板基底212内部。此外，配置为电连接顶部焊盘和底部焊盘的贯穿通路可以形成在基板基底212中。
外部连接端子220可以附接到封装基板210的底表面。例如，外部连接端子220可以附接到底部焊盘216。外部连接端子220可以是例如焊料球或凸块。外部连接端子220可以将半导体封装1与外部装置电连接。例如，外部连接端子220可以包括位于封装基板210的底表面中的底部焊盘216上的下导电层222、以及位于下导电层222上的焊料球224。外部连接端子220还可以包括插置在下导电层222与焊料球224之间的外部连接柱。外部连接柱可以包括例如铜(Cu)。
底部填充材料层380可以形成在封装基板210与缓冲芯片D0之间。底部填充材料层380可以插置在封装基板210与缓冲芯片D0之间并围绕缓冲连接凸块346的侧表面。底部填充材料层380可以包括例如环氧树脂。在一些实施方式中，底部填充材料层380可以是第二模制层385的通过利用模制底部填充(MUF)方法而形成的部分。
第二模制层385可以形成在封装基板210上以部分地或完全地围绕缓冲芯片D0以及第一至第四半导体芯片C1、C2、C3和C4。第二模制层385可以围绕第一模制层375，但是可以不与第一至第四半导体芯片C1、C2、C3和C4的侧表面直接接触。第二模制层385可以包括例如EMC。
在根据一些实施方式的半导体封装1中，第一至第四半导体芯片C1、C2、C3和C4的每个可以包括参照图1至3描述的焊盘结构160。例如，在将第二半导体芯片C2接合到第一半导体芯片C1的工艺中，在第二半导体芯片C2的连接凸块146安置在第一半导体芯片C1的焊盘结构160上之后，第一半导体芯片C1的焊盘结构160可以通过利用热压接合工艺或回流工艺被接合到第二半导体芯片C2的连接凸块146。因为焊盘结构160的整个区域具有平坦的顶表面，所以在接合工艺期间可以减少或防止有机材料(例如绝缘层370的一部分)被俘获到连接凸块146中。此外，因为第一焊盘层(参照图3中的162)不被暴露于焊盘结构160外部，所以可以减少或防止由连接凸块146中包括的焊接材料与第一焊盘层162的接触所致的IMC的产生。因此，半导体封装1可以具有高可靠性。
虽然图17示出参照图1至3描述的焊盘结构160的示例，但是第一至第四半导体芯片C1、C2、C3和C4中的一个或更多个可以包括参照图4至14描述的焊盘结构160A、160B、160C、160D、160E、160F、160G、160H、160I、160J或160K。
图18至25是根据一些实施方式的制造半导体器件100F的方法的截面图。
参照图18，可以准备包括再分布结构150和再分布绝缘层156的基板110。如参照图1至3所述，再分布结构150可以具有包括多个再分布线152和多个再分布通路154的多层结构，并且再分布绝缘层156可以围绕再分布结构150。
此后，绝缘层可以在再分布绝缘层156上形成，并通过利用光致抗蚀剂图案而被图案化以形成具有开口158H的第二钝化层158。开口158H可以暴露再分布线152的顶表面的部分。
在一些实施方式中，第二钝化层158可以通过利用旋涂工艺、喷涂工艺或化学气相沉积(CVD)工艺而形成。
参照图19，导电阻挡层172、第一籽晶层174、蚀刻停止层176和第二籽晶层178可以在第二钝化层158上顺序地形成以形成下导电层170A。下导电层170A可以共形地形成在第二钝化层158的开口158H的侧壁以及暴露在开口158H的底部上的再分布线152的顶表面上。在一些实施方式中，导电阻挡层172、第一籽晶层174、蚀刻停止层176和第二籽晶层178可以通过利用溅射工艺或CVD工艺而形成。导电阻挡层172、第一籽晶层174、蚀刻停止层176和第二籽晶层178的各自的厚度和材料可以与参照图1至3描述的那些相似。
这里，下导电层170A的形成在开口158H的侧壁上的部分可以被称为下导电层170A的第一部分170a，并且下导电层170A的形成在第二钝化层158的顶表面上的部分可以被称为下导电层170A的第二部分170b。第一部分170a的厚度t1可以与第二部分170b的厚度t2基本相等或相似。
参照图20，绝缘层可以在下导电层170A上形成，并通过利用光刻工艺被图案化以形成具有焊盘空间410H的模层410。在一些实施方式中，模层410可以包括光致抗蚀剂材料、光敏聚酰亚胺、紫外(UV)固化聚合物、环氧树脂、硅氧化物和/或硅氮化物。
焊盘空间410H可以与第二钝化层158的开口158H连通。例如，焊盘空间410H可以具有比开口158H更大的宽度。在一些实施方式中，下导电层170A的整个第一部分170a可以通过焊盘空间410H暴露，并且下导电层170A的第二部分170b的一部分可以被暴露在焊盘空间410H的外围部分中。
参照图21，通过利用电镀工艺或无电镀工艺，第一焊盘层162F可以在暴露于焊盘空间410H中和开口158H的内壁上的第二籽晶层178上形成。例如，当第一焊盘层162F包括铜(Cu)时，即使第一焊盘层162F的底表面具有相对较高的高度差，焊盘空间410H和开口158H也可以用第一焊盘层162F填充为使得第一焊盘层162F可以在焊盘空间410H的基本上整个区域上具有平坦的顶表面。
参照图22，第一焊盘层162F的上部可以通过利用回蚀刻工艺被去除直到蚀刻停止层176的顶表面被暴露。由于回蚀刻工艺，下导电层170A的第二部分170b(即第二籽晶层178的形成在第二钝化层158的顶表面上的部分)可以被去除。同时，焊盘空间410H的侧壁可以通过利用回蚀刻工艺被再次暴露。
此外，因为第二籽晶层178从焊盘空间410H的外围部分被去除，所以下导电层170A的第二部分170b的厚度t2可以小于第一部分170a的厚度t1。第一焊盘层162F可以具有相对于基板110的第一表面110S1位于比第二钝化层158的顶部水平LV3(参照图3)更高的水平处的顶表面，并且第一焊盘层162F可以填充开口158H的基本上整个剩余部分。
在一些实施方式中，第一焊盘层162F可以包括位于第二钝化层158的顶表面上的突起162o。这里，下导电层170A的位于突起162o下方的部分可以被称为第三部分170c。
在另外的实施方式中，与图22相比，可以执行回蚀刻工艺直到暴露于焊盘空间410H中的第一焊盘层162的顶表面、第二籽晶层178的顶表面和蚀刻停止层176的顶表面变得彼此共面。在这种情况下，参照图1至3描述的半导体器件100可以被形成。
参照图23，暴露于焊盘空间410H中的蚀刻停止层176可以被去除。根据一些实施方式，去除蚀刻停止层176的工艺可以通过利用相对于第一焊盘层162F以及第一籽晶层174和第二籽晶层178具有蚀刻选择性的蚀刻条件被执行。例如，去除工艺可以是湿刻蚀工艺或干刻蚀工艺。
作为去除工艺的结果，仅蚀刻停止层176的位于下导电层170A的第二部分170b中的部分可以被去除，并且第一籽晶层174的位于第二钝化层158的顶表面上的部分的顶表面可以被暴露。此外，因为蚀刻停止层176的所述部分从焊盘空间410H的外围部分被去除，所以下导电层170A的第二部分170b的厚度t2可以小于第一部分170a的厚度t1或下导电层170A的第三部分170c的厚度t3。
参照图24，通过利用电镀工艺或无电镀工艺，第二焊盘层164F可以在暴露于焊盘空间410H的底部上的第一籽晶层174和第一焊盘层162上形成。因为在暴露于焊盘空间410H的底部上的第一籽晶层174与第一焊盘层162F之间存在相对较小的水平差异，所以即使第二焊盘层164F包括例如镍(Ni)，焊盘空间410H也可以用第二焊盘层164F填充为使得第二焊盘层164F可以在焊盘空间410H的基本上整个区域上具有平坦的顶表面。
这里，第二焊盘层164的具有与第一焊盘层162F的顶表面接触的底表面的部分可以被称为第二焊盘层164F的第一部分164a，而第二焊盘层164F的具有与第一籽晶层174的顶表面接触的底表面的部分可以被称为第二焊盘层164F的第二部分164b。根据一些实施方式，因为第二焊盘层164F通过利用第一籽晶层174和第一焊盘层162F作为籽晶材料而在焊盘空间410H的底部上形成，所以第二焊盘层164F可以在焊盘空间410H的整个区域上形成至一致高度并具有平坦的顶表面。
此后，盖层166可以通过利用电镀工艺或无电镀工艺在第二焊盘层164F上形成。
参照图25，模层(参照图24中的410)可以被去除。此后，位于第二钝化层158的顶表面上的第二籽晶层178和蚀刻停止层176可以被顺序地去除。
参照图9和25，形成在第二钝化层158的顶表面上的第一籽晶层174和导电阻挡层172可以被顺序地去除。在去除第一籽晶层174和导电阻挡层172的工艺中，第一籽晶层174和导电阻挡层172的位于第二焊盘层164F下方的部分也可以被去除。因此，底切区域170U可以在第二焊盘层164F的外围部分(例如第二焊盘层的第二部分164b)与第二钝化层158之间被限定在从其去除了第一籽晶层174和导电阻挡层172的位置处。为了简洁，底切区域170U的形状和尺寸在图3中示出，并且本发明构思不限于图9中所示的那些。根据另外的实施方式，第一籽晶层174和导电阻挡层172可以通过利用例如定向蚀刻工艺被去除。在这种情况下，在第二焊盘层164F的外围部分与第二钝化层158之间的第一籽晶层174和导电阻挡层172可能难以被去除。因此，底切区域170U可以不被形成，或者可以具有基本垂直的侧壁轮廓。
半导体器件100F的制造可以通过利用上述方法被完成。
在根据一些实施方式的制造半导体器件100F的方法中，第一焊盘层162F可以被回蚀刻直到蚀刻停止层176的顶表面被暴露，并且蚀刻停止层176的暴露部分可以被去除。此后，第二焊盘层164F可以通过利用第一焊盘层162F和暴露的第一籽晶层174作为籽晶层而形成。因此，第二焊盘层164F的整个区域的顶表面可以基本上是平坦的。因此，在将半导体器件100F接合到另一半导体器件的工艺期间，可以减少或防止有机材料被俘获到焊料层中。此外，因为第一焊盘层162F不被暴露于焊盘结构160F外部，所以可以减少或防止由焊料层与第一焊盘层162F的接触所致的IMC的产生。因此，半导体器件100F可以具有高可靠性。
当在此使用时，单数形式“一”和“该”旨在还包括复数形式，除非上下文清楚地另行指示。术语“和/或”包括相关所列举项目中的一个或更多个的任何及所有组合。
虽然已经参照本发明构思的实施方式具体显示和描述了本发明构思，但是将理解，可以在其中进行形式和细节上的各种各样的改变而不背离所附权利要求的精神和范围。
本申请要求2017年7月24日向韩国知识产权局提交的韩国专利申请第10-2017-0093692号的权益，其公开通过引用全文合并于此。

Claims (25)

1.一种半导体器件，包括：
在基板上的导电部件；
钝化层，在所述基板上并且在其中包括开口，其中所述开口暴露所述导电部件的至少一部分；以及
焊盘结构，在所述钝化层上并且在所述开口中，所述焊盘结构电连接到所述导电部件，所述焊盘结构包括：
下导电层，在所述开口的内侧壁上以及在围绕所述开口的所述钝化层的顶表面上共形地延伸，所述下导电层包括顺序地堆叠的导电阻挡层、第一籽晶层、蚀刻停止层和第二籽晶层，
在所述下导电层上的第一焊盘层，所述第一焊盘层至少部分地填充所述开口，以及
在所述第一焊盘层上的第二焊盘层，所述第二焊盘层横向地延伸超过所述第一焊盘层以接触所述下导电层的位于所述钝化层的所述顶表面上的外围部分。
2.根据权利要求1所述的半导体器件，其中所述第二焊盘层直接在所述第一籽晶层的位于所述下导电层的所述外围部分处的部分上，所述第一籽晶层的所述部分位于围绕所述开口的所述钝化层的所述顶表面上。
3.根据权利要求2所述的半导体器件，其中所述第一焊盘层直接在所述第二籽晶层上并且至少部分地填充所述开口，并且其中所述第二焊盘层直接在所述第一焊盘层上。
4.根据权利要求1所述的半导体器件，其中所述第一焊盘层与所述第一籽晶层通过所述第二籽晶层和所述蚀刻停止层的在它们之间的部分隔开，并且其中所述下导电层的所述外围部分不具有所述第二籽晶层和所述蚀刻停止层。
5.根据权利要求1所述的半导体器件，其中所述下导电层包括第一部分和第二部分，其中所述第一部分围绕所述第一焊盘层的侧壁，所述第二部分与所述第二焊盘层接触并且位于所述第二焊盘层下方，
其中所述下导电层的所述第一部分的第一厚度大于所述下导电层的所述第二部分的第二厚度。
6.根据权利要求5所述的半导体器件，其中所述下导电层还包括第三部分，所述第三部分在所述第一焊盘层下方并且在围绕所述开口的所述钝化层的所述顶表面上，以及
其中所述下导电层的所述第三部分的第三厚度大于所述下导电层的所述第二部分的所述第二厚度。
7.根据权利要求6所述的半导体器件，其中所述下导电层的所述第二部分包括顺序地堆叠在所述钝化层的所述顶表面上的所述导电阻挡层和所述第一籽晶层，以及
所述下导电层的所述第三部分包括顺序地堆叠在所述钝化层的所述顶表面上的所述导电阻挡层、所述第一籽晶层、所述蚀刻停止层和所述第二籽晶层。
8.根据权利要求6所述的半导体器件，其中所述第一焊盘层包括突起，所述突起延伸到围绕所述开口的所述钝化层的所述顶表面上，并且所述下导电层的所述第三部分在所述突起与所述钝化层之间。
9.根据权利要求1所述的半导体器件，其中所述第一焊盘层的顶表面相对于所述基板在比所述钝化层的所述顶表面更高的水平处，以及
所述第二焊盘层的第一部分的第一底表面相对于所述基板在比所述第二焊盘层的第二部分的第二底表面更高的水平处，其中所述第一底表面与所述第一焊盘层的所述顶表面接触，并且所述第二底表面与所述第一籽晶层的顶表面接触。
10.根据权利要求1所述的半导体器件，其中所述第一焊盘层的顶表面相对所述基板在比所述钝化层的所述顶表面更低的水平处，以及
所述第二焊盘层的第一部分的第一底表面相对于所述基板在比所述第二焊盘层的第二部分的第二底表面更低的水平处，其中所述第一底表面与所述第一焊盘层的所述顶表面接触，并且所述第二底表面与所述第一籽晶层的顶表面接触。
11.根据权利要求1所述的半导体器件，其中所述第一焊盘层包括铜(Cu)，所述第二焊盘层包括镍(Ni)。
12.根据权利要求1所述的半导体器件，其中所述第一籽晶层和所述第二籽晶层包括铜(Cu)，所述导电阻挡层和所述蚀刻停止层包括从由钛(Ti)、钛氮化物(TiN)、钽(Ta)和钽氮化物(TaN)组成的组中选择的至少一种。
13.根据权利要求1所述的半导体器件，其中所述导电部件包括穿透所述基板的贯穿基板通路(TSV)或电连接到所述贯穿基板通路的再分布线中的至少一个。
14.根据权利要求1所述的半导体器件，其中所述第二焊盘层在所述第一焊盘层的整个顶表面上延伸，所述下导电层在所述第一焊盘层的整个侧壁和整个底表面上延伸，以及
所述第一焊盘层被所述焊盘结构包封。
15.根据权利要求1所述的半导体器件，其中所述第二焊盘层的顶表面基本上是平坦的。
16.一种半导体封装，包括：
第一半导体芯片；以及
连接到所述第一半导体芯片的第二半导体芯片，
其中所述第二半导体芯片包括：
在基板上的导电部件，
钝化层，在所述基板上并且在其中包括开口，所述开口暴露所述导电部件的至少一部分，以及
焊盘结构，在所述钝化层上并且在所述开口中，所述焊盘结构电连接到所述导电部件，所述焊盘结构包括：
下导电层，在所述开口的内侧壁上以及在围绕所述开口的所述钝化层的顶表面上共形地延伸，所述下导电层包括顺序地堆叠的导电阻挡层、第一籽晶层、蚀刻停止层和第二籽晶层，
在所述下导电层上的第一焊盘层，所述第一焊盘层至少部分地填充所述开口，以及
在所述第一焊盘层上的第二焊盘层，所述第二焊盘层与所述下导电层的位于所述钝化层的所述顶表面上的外围部分接触。
17.根据权利要求16所述的半导体封装，其中所述导电部件包括穿透所述基板的贯穿基板通路(TSV)或电连接到所述贯穿基板通路的再分布线中的至少一个。
18.根据权利要求16所述的半导体封装，其中所述下导电层包括第一部分和第二部分，其中所述第一部分围绕所述第一焊盘层的侧壁，并且所述第二部分与所述第二焊盘层接触并且位于所述第二焊盘层下方，
其中所述下导电层的所述第一部分的第一厚度大于所述下导电层的所述第二部分的第二厚度。
19.根据权利要求18所述的半导体封装，其中所述下导电层还包括第三部分，所述第三部分在所述第一焊盘层下方并且在围绕所述开口的所述钝化层的所述顶表面上，
其中所述下导电层的所述第三部分的第三厚度大于所述下导电层的所述第二部分的所述第二厚度。
20.根据权利要求16所述的半导体封装，其中所述第二焊盘层直接在所述第一籽晶层的位于所述下导电层的所述外围部分处的部分上，所述第一籽晶层的所述部分位于围绕所述开口的所述钝化层的所述顶表面上，
其中所述下导电层的所述外围部分不具有所述第二籽晶层和所述蚀刻停止层，以及
所述第一焊盘层直接在所述第二籽晶层上并且通过其与所述第一籽晶层隔开。
21.一种制造半导体器件的方法，所述方法包括：
在基板上形成钝化层，所述钝化层在其中包括开口，所述开口暴露导电部件的至少一部分；
通过顺序地形成导电阻挡层、第一籽晶层、蚀刻停止层和第二籽晶层而在所述开口的内侧壁和所述钝化层的顶表面上形成下导电层；
在所述下导电层上形成模层，所述模层包括与所述开口连通的焊盘空间；
在所述下导电层上形成在所述开口中的第一焊盘层；以及
在所述第一焊盘层上形成在所述焊盘空间中的第二焊盘层，所述第二焊盘层与所述第一焊盘层接触并与所述下导电层的位于所述钝化层的所述顶表面上的外围部分接触。
22.根据权利要求21所述的方法，其中所述第一焊盘层的形成包括：
通过利用所述第二籽晶层作为籽晶材料而在所述开口和所述焊盘空间中形成第一焊盘层；以及
回蚀刻所述第一焊盘层的上部直到所述蚀刻停止层的顶表面被暴露，使得所述第一焊盘层仅填充所述开口。
23.根据权利要求22所述的方法，其中所述第一焊盘层的所述上部的回蚀刻包括回蚀刻所述第一焊盘层的所述上部直到所述第一焊盘层的顶表面相对于所述基板在与所述蚀刻停止层的所述顶表面相同的水平处。
24.根据权利要求22所述的方法，其中所述第一焊盘层的所述上部的回蚀刻包括回蚀刻所述第一焊盘层的所述上部直到所述第一焊盘层的顶表面相对于所述基板在比所述蚀刻停止层的所述顶表面更低的水平处。
25.一种半导体器件，包括：
在基板上的导电部件；
钝化层，在所述基板上并且在其中包括暴露所述导电部件的一部分的开口；以及
导电焊盘结构，在所述钝化层上并且在所述开口中，其中所述导电焊盘结构包括：
下导电层，在所述开口的侧壁上以及在所述开口外部的所述钝化层的表面上，所述下导电层包括顺序地堆叠的第一籽晶层、蚀刻停止层和第二籽晶层，
第一焊盘层，在所述开口中直接在所述第二籽晶层上，以及
第二焊盘层，在所述开口外部直接在所述第一籽晶层上，其中所述第一焊盘层与所述第一籽晶层通过所述第二籽晶层、所述蚀刻停止层和/或所述第二焊盘层的部分隔开，并且其中所述第二焊盘层的顶表面基本上是平坦的。
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US20190027450A1 (en) 2019-01-24
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