CN110660776A - 具有再分配层的半导体封装件 - Google Patents
具有再分配层的半导体封装件 Download PDFInfo
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- CN110660776A CN110660776A CN201910163905.3A CN201910163905A CN110660776A CN 110660776 A CN110660776 A CN 110660776A CN 201910163905 A CN201910163905 A CN 201910163905A CN 110660776 A CN110660776 A CN 110660776A
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Abstract
半导体封装件包括硅衬底,其包括腔体和与腔体间隔开的多个通孔;第一半导体芯片,其位于所述腔体中;多个导电过孔,其位于所述多个通孔中;第一再分配层,其位于所述硅衬底上并且连接到所述第一半导体芯片和所述导电过孔;以及第二再分配层,其位于所述硅衬底下方,并且连接至所述第一半导体芯片和所述多个导电过孔。
Description
相关申请的交叉引用
本申请要求于2018年6月29日提交的韩国专利申请No.10-2018-0075505的优先权,所公开的全部内容以引用的方式合并于此。
技术领域
根据示例实施例的设备和方法涉及包括再分配层的半导体封装件及其制造方法。
背景技术
随着半导体器件变得高度集成,已经出现了用于提高半导体芯片和安装有半导体芯片的半导体封装件的集成度并且减小其尺寸的技术。随着电子产品尺寸变得越来越小,用于将大量多功能半导体芯片安装在单个封装件中以处理大量数据的系统级封装技术受到了很多关注。通常,已经使用了用于将半导体芯片安装在印刷电路板上的半导体封装技术,但是当使用这种印刷电路板时,制造薄半导体封装件受到限制。为了解决这个问题,已经开发出扇出式晶片级封装技术,其中再分配层形成在半导体芯片下方而不是印刷电路板上。为了把半导体封装件做小,需要一种减小电连接半导体封装件中的多个半导体芯片的贯通电极之间的距离的方法。
发明内容
发明构思的示例实施例旨在提供一种半导体封装件,其中导电过孔形成在衬底中以减小导电过孔之间的距离。
另外,发明构思的示例实施例旨在提供一种制造半导体封装件的方法,其中在半导体芯片的侧表面上形成间隔件,因此不需要形成支撑晶片的载体。
此外,发明构思的示例实施例旨在提供一种高性能半导体封装件,其中通过形成待被电连接到半导体芯片的上部和下部的再分配层来形成各种短信号路径。
根据一些示例实施例,半导体封装件包括硅衬底,其包括腔体和与腔体间隔开的多个通孔;第一半导体芯片,其位于所述腔体中;多个导电过孔,其位于所述多个通孔中;第一再分配层,其位于所述硅衬底上,并且所述第一再分配层连接到所述第一半导体芯片和所述多个导电过孔;以及第二再分配层,其位于所述硅衬底下方,并且所述第二再分配层连接至所述第一半导体芯片和所述导电过孔。
根据一些示例实施例,半导体封装件包括硅衬底,其包括腔体和与腔体间隔开的多个通孔;第一半导体芯片,其位于所述腔体中;多个导电过孔,其位于所述多个通孔中;第一再分配层,其位于所述硅衬底上,并且所述第一再分配层连接到所述第一半导体芯片和所述多个导电过孔;第二再分配层,其位于所述硅衬底下方,并且所述第二再分配层连接至所述第一半导体芯片和所述多个导电过孔;以及第二半导体芯片,其位于所述第一再分配层上,并且所述第二半导体芯片连接至所述第一再分配层。
根据一些示例实施例,一种半导体封装件包括硅衬底,其包括腔体和与腔体间隔开的多个通孔;第一半导体芯片,其位于所述腔体中;第一再分配层,其位于所述硅衬底上;第二再分配层,其位于所述硅衬底下方,所述第二再分配层连接至所述第一半导体芯片;第二半导体芯片,其位于所述第一再分配层上,所述第二半导体芯片连接至所述第一再分配层;第三半导体芯片,其位于所述第一半导体芯片上,所述第三半导体芯片连接至所述第一再分配层;以及多个导电过孔,其位于所述多个导电通孔中。
附图说明
图1是用于描述根据一些示例实施例的半导体封装件的晶片的示意性平面图;
图2是用于描述根据一些示例实施例的半导体封装件的截面图;
图3A和图3B是图2的半导体封装件的示例的平面图;
图4是用于描述根据一些示例实施例的半导体封装件的信号传输路径的截面图;
图5、图6和图7是根据其他示例实施例的半导体封装件的截面图;以及
图8、图9A、图9B、图10至图12、图13A、图13B以及图14至图17是顺序地示出根据一些示例实施例的半导体封装件的制造方法的操作的截面图。
具体实施方式
在下文中,为了阐明发明构思的技术思想,将参照附图详细描述本发明构思的示例实施例。当描述发明构思时,在确定功能或组件由于不必要的细节而使发明构思模糊的情况下,不详细描述公知的功能或组件。在附图中,尽管在不同的附图中示出了各个组件,但是相同的参考符号或标记被分配给尽可能具有基本相同功能的组件。为了便于说明,设备和方法可以一起描述。
图1是用于描述根据一些示例实施例的半导体封装件100的晶片10的示意性平面图。
参照图1,晶片10可以是半导体晶片(例如,硅晶片)并且可以包括多个晶粒20。晶片10可以称为衬底10。晶粒20可以对应于根据一些示例实施例的半导体封装件100的衬底10。在实施例中,半导体芯片40可以设置在每个晶粒20上。在另一实施例中,多个半导体芯片50、60和70可以设置在晶粒20中的一个上。晶粒20可以由划片线30分开。
图2是用于描述根据一些示例实施例的半导体封装件100的截面图。
参照图2,根据一些示例实施例的半导体封装件100可以包括衬底102、腔体104、通孔106、第一半导体芯片110、导电过孔120、第一再分配层130以及第二再分配层140。半导体封装件100还可以包括第二半导体芯片150和外部连接元件160。
衬底102可以包括硅、硅锗、碳化硅或其组合。在图2所示的半导体封装件100的截面图中,衬底102的上端和下端可以分别指的是第一表面102a和第二表面102b。第一表面102a和第二表面102b可以彼此面对。衬底102可以包括腔体104和通孔106。
腔体104可以形成为沿竖直方向穿通衬底102并且可以设置在半导体封装件100的中部区域。腔体104的上端可以位于与衬底102的第一表面102a相同的水平高度处,并且其下端可以位于与衬底102的第二表面102b相同的水平高度处。第一半导体芯片110可以设置在腔体104中。在实施例中,可以设置多个第一半导体芯片110。腔体104可以是多个腔体的一部分。
可以在腔体104周围设置多个通孔106。多个通孔106可以彼此间隔设置。通孔106可以设置在衬底102的外围区域。外围区域可以包括与衬底102相同的材料,例如硅。外围区域可以形成在第一半导体芯片110的一侧,因此可以用作限制和/或防止在半导体封装件100的制造期间衬底102的翘曲或损坏的间隔件。间隔件可以包括通孔106、导电过孔120和过孔绝缘层122。
图3A和图3B是图2的半导体封装件100的示例的平面图。参照图3A和图3B,可以在腔体104的周围设置多个通孔106。如图3A所示,通孔106可以以一对线的形式布置,并且腔体104位于该对线之间。可替代地,图3B所示,通孔106可以布置成围绕腔体104。
通孔106可以从衬底102的第一表面102a延伸到其第二表面102b并且沿竖直方向穿通衬底102。通孔106的上端可以位于与衬底102的第一表面102a相同的水平高度处,并且其下端可以位于与衬底102的第二表面102b相同的水平高度处。导电过孔120可以设置在通孔106中。可以在包括硅的间隔件中形成通孔106。因此,可以以微小间隔设置通孔106。
腔体104可以具有矩形形状,并且其宽度W1和宽度W2可以具有相同的值或不同的值。通孔106的直径W3可以小于腔体104的宽度W1和W2。例如,腔体104的宽度W1和W2可以均在3mm至20mm的范围内,并且通孔106的直径W3可以在2μm至50μm的范围内。当通孔106的直径W3非常窄时,在每个通孔106中形成导电过孔120会很困难。当通孔106的直径W3大于50μm时,通孔106之间的中心距(pitch)大,因此如果直径W3大于50μm,则通孔106可能不会适当地连接到第一再分配层130或第二再分配层140。通孔106形成在硅衬底102中,因此通孔106之间的距离可以小于通过冲压模塑材料形成通孔106时的通孔106之间的距离。因为通孔106之间的距离非常小,所以可以在更狭窄的区域中形成半导体封装件100。
返回参照图2,第一半导体芯片110可以设置在腔体104中。第一半导体芯片110可以是逻辑芯片。例如,第一半导体芯片110可以包括微处理器、控制器或应用程序处理器(AP)。第一半导体芯片110的上端可以位于与腔体104和通孔106的上端相同的水平高度处。第一半导体芯片110的下端可以位于与腔体104和通孔106的下端相同的水平高度处。第一半导体芯片110的宽度可以小于腔体104的宽度。
上焊盘112和下焊盘114可以分别形成在第一半导体芯片110的上端和下端上。上焊盘112可以电连接至第一再分配层130,并且下焊盘114可以电连接至第二再分配层140。上焊盘112和下焊盘114可以通过第一半导体芯片110中的电路彼此电连接。
密封剂116可以设置在腔体104的内侧表面和第一半导体芯片110的侧表面之间,并且第一半导体芯片110可以用密封剂116密封。密封剂116的上端可以位于与衬底102的第一表面102a相同的水平高度处,并且其下端可以位于与衬底102的第二表面102b相同的水平高度处。密封剂116可以包括绝缘材料并且保护半导体封装件100中的第一半导体芯片110免受外部影响。
在实施例中,第一半导体芯片110还可以包括其中的多个贯通电极118。贯通电极118可以电连接上焊盘112和下焊盘114。贯通电极118可以包括Cu、CuSn、CuMg、CuNi、CuZn、CuPd、CuAu、CuRe、CuW、W或导电胶中的至少一种。在实施例中,可以省略贯通电极118。
导电过孔120可以设置在通孔106中。导电过孔120可以包括金属,例如铜。导电过孔120的上端可以位于与衬底102的第一表面102a相同的水平高度处,并且其下端可以位于与衬底102的第二表面102b相同的水平高度处。参照图3A和图3B,可以在第一半导体芯片110的周围形成多个导电过孔120。如图3A所示,导电过孔120可以以一对线的形式布置,并且腔体104位于该对线之间。可替代地,图3B所示,导电过孔120可以布置成围绕腔体104。
可以在导电过孔120的外侧形成过孔绝缘层122,以覆盖通孔106的内侧表面。过孔绝缘层122可以将衬底102和导电过孔120彼此电绝缘。过孔绝缘层122可以以多层形成并且包括将在下面描述的阻挡膜123和绝缘膜124。
返回参照图2,第一再分配层130以及第二再分配层140可以形成在衬底102的相对的表面上。第一再分配层130可以形成在衬底102的第一表面102a上,以电连接至第一半导体芯片110、导电过孔120和第二半导体芯片150。第二再分配层140可以形成在衬底102的第二表面102b上,以电连接至第一半导体芯片110、导电过孔120和外部连接元件160。第一再分配层130和第二再分配层140可以根据其设计执行各种功能。例如,第一再分配层130和第二再分配层140可以包括接地图案GND、电源图案PWR、信号图案S等。这里,信号图案S包括排除接地图案GND、电源图案PWR等的各种类型的信号,例如数据信号。
第一再分配层130可以包括互连图案132和过孔134。互连图案132可以电连接至上焊盘112、导电过孔120和内部连接元件156。经由开口136暴露的互连图案132可以连接至内部连接元件156。第二再分配层140可以包括互连图案142和过孔144。互连图案142可以电连接至下焊盘114、导电过孔120和外部连接元件160。经由开口146暴露的互连图案142可以连接至外部连接元件160。互连图案132和过孔134可以彼此一体地形成,并且互连图案142和144可以彼此一体地形成。过孔134和144可以电连接形成在不同层处的互连图案132和142。过孔134和144可各自具有锥形形式。互连图案132和142以及过孔134和144可以提供半导体封装件100中的各种信号路径。
可以在第一再分配层130上设置第二半导体芯片150。可以形成多个第二半导体芯片150,并且通过芯片-晶片键合将其附接至第一再分配层130。第二半导体芯片150可以是存储器装置。例如,第二半导体芯片150可以包括存储器装置,例如闪存、动态随机存取存储器(DRAM)、静态RAM(SRAM)、电可擦除可编程只读存储器(EEPROM)、相变RAM(PRAM)、磁RAM(MRAM)、电阻RAM(ReRAM)、高带宽存储器(HBM)或混合存储器立方体(HMC)。
底部填充物152可以形成在第二半导体芯片150的下表面和第一再分配层130之间。第一再分配层130和第二半导体芯片150之间的一些区域和各个第二半导体芯片150之间的一些区域可以利用底部填充物152密封。在实施例中,底部填充物152可以是非导电膜(NCF)或非导电胶(NCP)。密封剂154可以形成在第二半导体芯片150的侧表面上以及底部填充物152上。密封剂154的上端可以位于与第二半导体芯片150的上端相同的水平高度处。密封剂154可以包括绝缘材料并且保护半导体封装件100中的第二半导体芯片150免受外部影响。内部连接元件156可以形成在第二半导体芯片150的下表面上,并且连接至第一再分配层130的互连图案132。内部连接元件156可以电连接第二半导体芯片150和第一再分配层130。内部连接元件156可以是焊料球或电极焊盘。
外部连接元件160可以形成在第二再分配层140的下表面上。外部连接元件160可以连接至第二再分配层140的互连图案142。例如,根据一些示例实施例的半导体封装件100可以经由外部连接元件160安装在电子器件的主板上。第二再分配层140可以经由外部连接元件160电连接至外部器件(未示出)。因此,第一半导体芯片110和第二半导体芯片150可以电连接至外部器件。外部连接元件160可以是焊料球。
图4是用于描述根据一些示例实施例的半导体封装件100的信号传输路径的截面图。
参照图4,根据一些实例实施例的半导体封装件100可以以信号路径A、B、C、D、E和F电连接。在实施例中,第一半导体芯片110可以是逻辑芯片,并且第二半导体芯片150可以是存储器芯片,并且第一半导体芯片110和第二半导体芯片150可以在半导体封装件10中交换信号。
在第一信号路径A中,第一半导体芯片110可以与外部器件(未示出)交换信号。例如,第一半导体芯片110可以经由下焊盘114和第二再分配层140电连接至外部连接元件160。VSS信号、VCC信号和数据信号等可以经由第一信号路径A传输至第一半导体芯片110。
在第二信号路径B中,第二半导体芯片150可以与外部器件(未示出)交换信号。例如,第二半导体芯片150可以经由内部连接元件156、第一再分配层130、导电过孔120和第二再分配层140电连接至外部连接元件160。VSS信号、VCC信号和数据信号等可以经由第二信号路径B传输至第二半导体芯片150。
在第三信号路径C中,第一半导体芯片110可以与第二半导体芯片150交换信号。例如,第一半导体芯片110可以经由上焊盘112、第一再分配层130和内部连接元件156电连接至第二半导体芯片150。
在第四信号路径D中,多个第二半导体芯片150可以彼此交换信号。例如,多个第二半导体芯片150可以经由内部连接元件156和第一再分配层130电连接。可以经由第四信号路径D在第一半导体芯片110和第二半导体芯片150之间提供输入/输出信号。
在第五信号路径E中,第一半导体芯片11可以经由第二半导体芯片150与外部器件交换信号。例如,第一半导体芯片110可以经由上焊盘112、第一再分配层130、内部连接元件156、第二半导体芯片150、导电过孔120和第二再分配层140电连接至外部连接元件160。
在第六信号路径F中,第一半导体芯片110的上焊盘112和下焊盘114可以彼此交换信号。例如,上焊盘112可以经由贯通电极118电连接至下焊盘114。根据第六信号路径F,从第二半导体芯片150经由第一半导体芯片110传输至外部器件的信号可以经由第三信号路径C、第六信号路径F和第一信号路径A传输而无需经由第五信号路径E传输。
图5、图6和图7是根据其他示例实施例的半导体封装件100的截面图。这里可以省略对以上参照图2描述的组件相同的组件的详细描述。
参照图5,腔体104还可以包括粘合剂117。粘合剂117可以形成在第一半导体芯片110的侧表面之间的腔体104中,并且可以位于密封剂116的下方。在将第一半导体芯片110安装在腔体104中期间,可以使用粘合剂117来固定第一半导体芯片110,并且第一半导体芯片110可以包括晶粒附接膜(DAF)、NCF或NCP。可以在安装第一半导体芯片110和将衬底102的第二表面102b平坦化期间去除粘合剂117,但是在实施例中,粘合剂117可以保留在第一半导体芯片110的侧表面上。
参照图6,第一半导体芯片110可以不包括贯通电极118。即使在不形成贯通电极118的情况下,上焊盘112和下焊盘114也可以经由第一半导体芯片110的内部电连接。由此,第一再分配层130和第二再分配层140可以经由第一半导体芯片110电连接。
参照如7,腔体104还可以包括其中的第三半导体芯片270。第一半导体芯片210可以位于腔体104的下部并且包括上焊盘212、下焊盘214和连接上焊盘212和下焊盘214的贯通电极218。第三半导体芯片270可以位于第一半导体芯片210上并且包括上焊盘272和下焊盘274。上焊盘272和下焊盘274可以在第三半导体芯片270中电连接。在实施例中,可以形成连接上焊盘272和下焊盘274的贯通电极。第三半导体芯片270可以经由内部连接元件156电连接至第一半导体芯片110。例如,第三半导体芯片270的下焊盘274可以电连接至内部连接元件276、上焊盘212、贯通电极218和下焊盘214。第三半导体芯片270可以是例如DRAM或SRAM的存储器装置,但不限于此。
下面将描述制造根据一些示例实施例的半导体封装件100的方法。
图8、图9A、图9B、图10至图12、图13A、图13B和图14至图17是顺序地示出根据一些示例实施例的半导体封装件100的制造方法的操作的截面图。
参照图1,在根据一些示例实施例的半导体封装件100的制造方法中,制备或提供包括衬底102的硅晶片。
参照图8,部分地蚀刻衬底102,以在衬底102的第一表面102a中形成多个第二沟槽106'。参照图3,第二沟槽106’可以各自具有圆形形状,并且形成在衬底102的边缘区域中。第二沟槽106’可以彼此间隔一定距离并且布置成矩形形状,但是实施例不限于此。可以通过反应离子刻蚀(RIE)或激光钻孔形成第二沟槽106’。
参照图9A,可以在第二沟槽106’中形成硅通孔(TSV)结构。TSV结构可以包括导电过孔120和过孔绝缘层122。过孔绝缘层122可以形成在第二沟槽106’的侧壁上和下部分上,并且第二沟槽106’的内部可以填充有导电过孔120。
首先,可以在第二沟槽106’的侧壁和下部分上形成过孔绝缘层122。可以通过化学气相沉积(CVD)、物理气相沉积(PVD)或原子层沉积(ALD)来形成过孔绝缘层122。在实施例中,过孔绝缘层122可以从衬底102的第一表面102a到其第二表面102b逐渐变细。图9B是图9A所示的区域R1部分的放大图。参照图9B,过孔绝缘层122可以包括阻挡膜123和绝缘膜124。阻挡膜123可以包括具有低电阻的导电层。例如,阻挡膜123可以包括选自Ti、TiN、Ta、TaN、W、WN、WC、Co、Mn、WN、Ni和Ru中的至少一种。阻挡膜123可以包括Ti、TiN、Ta、TaN、W、WN、WC、Co、Mn、WN、Ni或者Ru中的至少一种。绝缘膜124可以位于阻挡膜123的外侧,并且将导电过孔120和衬底彼此绝缘。例如,绝缘膜124可以包括氧化硅、氮化硅、碳化硅、聚合物或其组合。虽然没有示出,但是在实施例中,可以在阻挡膜123和绝缘膜124之间形成含金属绝缘膜。可以通过将阻挡膜123的在阻挡膜123和绝缘膜124之间的部分氧化来形成含金属绝缘膜。例如,含金属绝缘膜可包括氧化钽、氧氮化钽、氧化钛、氧氮化钛或其组合。
之后,可以在过孔绝缘层122上形成导电过孔120以填充第二沟槽106’。可以通过电镀或CVD形成导电过孔120。导电过孔120可以包括Cu、CuSn、CuMg、CuNi、CuZn、CuPd、CuAu、CuRe、CuW、W或导电胶中的至少一种,但不限于此。
导电过孔120和过孔绝缘层122不仅在第二沟槽106’中形成,还在衬底102的第一表面102a上形成。可以通过化学机械抛光(CMP)部分地蚀刻导电过孔120和过孔绝缘层122,以暴露衬底102的第一表面102a。蚀刻的导电过孔120和过孔绝缘层122可以位于与衬底102的第一表面102a相同的水平高度处。
之后,可以在衬底102的第一表面102a中形成第一沟槽104’。第一沟槽104’可以具有矩形形状并且形成在衬底102的中部区域。第一沟槽104’可以位于多个第二沟槽106’之间,并且多个第二沟槽106’可以关于第一沟槽104’对称。在实施例中,第二沟槽106’可以形成为围绕第一沟槽104’。第二沟槽106’的深度可以大于第一沟槽104’的深度。第二沟槽106’的宽度可以小于第一沟槽104’的宽度。第二沟槽106’之间的距离可以小于第一沟槽104’的宽度。例如,第一沟槽104'的宽度W1可以在3mm至20mm的范围内并且第二沟槽106'的直径W3可以在2μm至50μm的范围内。第一沟槽104'的深度D1可以在60μm至200μm的范围内,并且第二沟槽106'的深度D2可以在40μm至200μm的范围内。
参照图10,可以将第一半导体芯片110设置在第一沟槽104’中。第一半导体芯片110可以包括其上表面上的多个上焊盘112以及其下表面上的多个下焊盘114。可以在第一半导体芯片110和第一沟槽104’的下部之间形成粘合剂117’。粘合剂117’可以固定第一半导体芯片110并且包括DAF、NCF或NCP。第一半导体芯片110可以是逻辑芯片,并且可以包括应用程序处理器。第一半导体芯片110的宽度可以小于第一沟槽104'的宽度。
参照图11,可以在第一沟槽104’中形成密封剂116’,以填充第一沟槽104’中的空间。密封剂116’可以覆盖第一沟槽104’的侧表面和下部、第一半导体芯片110的上表面和侧表面以及衬底102的第一表面102a。密封剂116’的上端可以位于比衬底102的第一表面102a和第一半导体芯片110的上表面更高的水平高度处。密封剂116'可以是包括环氧树脂、聚酰亚胺等的树脂。例如,密封剂116'可以是双酚型环氧树脂、多环芳族环氧树脂、邻甲酚酚醛环氧树脂(o-cresol novolac epoxy resin)、联苯型环氧树脂、萘型环氧树脂等。
参照图12,可以通过平坦化工艺通过蚀刻密封剂116’来形成密封剂116。可以通过平坦化工艺来暴露衬底102的第一表面102a和第一半导体芯片110。在实施例中,第一半导体芯片110的上表面和密封剂116的上端可以处于相同的水平高度。
参照图13A,可以在衬底102的第一表面102a上形成第一再分配层130。图13B是图13A所示区域R2部分的放大图。参照图13B,第一再分配层130可以包括互连图案132、过孔134、凸块下金属(under-bump metal)135、绝缘层138和钝化层137。首先,在衬底102、第一半导体芯片110和导电过孔120上形成绝缘层138。可以堆叠多个绝缘层138。绝缘层138可以覆盖第一半导体芯片110的上焊盘112或互连图案132。接下来,蚀刻绝缘层138的一部分以暴露上焊盘112或互连图案132。还可以在暴露的上焊盘112或互连图案132上形成互连图案132和过孔134。之后,可以在互连图案132上形成钝化层137,以保护第一再分配层130上的互连图案132。通过蚀刻钝化层137的一部分来形成开口136,以暴露互连图案132。可以在暴露的互连图案132和钝化层137上形成凸块下金属135。
互连图案132可以形成在第一再分配层130的不同层上并且可以提供信号传输路径。过孔134可以将互连图案132的形成在不同层上的部分电连接。过孔134可以由导电材料形成,并且可以完全填充有导电材料。过孔134可以形成在通路孔的壁的表面上并且可以具有圆柱形状以及锥形形状。过孔134可以与第一再分配层130的互连图案132一体地形成。绝缘层138和钝化层137可以将互连图案132和过孔134与外部器件电绝缘。将在下文描述的内部连接元件156可以形成在凸块下金属135上。凸块下金属135可以限制和/或防止内部连接元件156的扩散。
互连图案132和过孔134可各自包括导电材料,例如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或其合金。钝化层137和绝缘层138可各自包括SiO2、Si3N4、SiON、Ta2O5、HfO2,聚酰胺(PI)、聚苯并恶唑(PBO)、苯并环丁烯(BCB)、双马来酰亚胺三嗪(BT)或光敏树脂中的至少一种。凸块下金属135可包括铬/铬铜合金/铜(Cr/Cr-Cu/Cu)、钛钨合金/铜(Ti-W/Cu)、铝/镍/铜(Al/Ni/Cu)或镍中的至少一种。凸块下金属135可以通过溅射、电镀或无电极电镀中的一种形成。
参照图14,可以将至少一个第二半导体芯片150安装在第一再分配层130上。可以在第一再分配层130和第二半导体芯片150之间形成底部填充物152。内部连接元件156可以形成在第二半导体芯片150的下方,并且可以电连接第一再分配层130的互连图案132和第二半导体芯片150。
在实施例中,可以通过热压(TC)键合将第二半导体芯片150安装在第一再分配层130上。可以使用键合机(未示出)将具有形成在其下表面上的内部连接元件156的第二半导体芯片150吸附到第一再分配层130上。可以移动第二半导体芯片150以将内部连接元件156定位在与互连图案132对应的位置处,随后可以通过键合机加压加热。可以通过TC键合将内部连接元件156耦接至互连图案132。在实施例中,底部填充物152可以是NCF。NCF可以附接至第二半导体芯片150的下表面并且通过键合机加压和加热。在实施例中,底部填充物152可以是NCP。NCP可以附接至第一再分配层130的上表面并且通过键合机加压和加热。在实施例中,在第二半导体芯片150通过TC键合耦接至第一再分配层130之后,可以在第二半导体芯片150的下方形成底部填充物152。
参照图15,可以在第一再分配层130的上表面和第二半导体芯片150之间形成密封剂154。密封剂154可以防止第二半导体芯片150损坏。在第二半导体芯片150上和/或第二半导体芯片150之间形成密封剂154之后,可以通过平坦化工艺部分地蚀刻密封剂154的上部。密封剂154的上端可以位于与第二半导体芯片150的上端相同的水平高度处,并且其侧表面可以与衬底102和第一再分配层130的侧表面对齐。密封剂154可以是包括环氧树脂或聚酰亚胺的树脂。作为示例,密封剂154可以是双酚型环氧树脂、多环芳族环氧树脂、邻甲酚酚醛环氧树脂、联苯型环氧树脂、萘型环氧树脂等。
参照图16,可以将衬底102倒置,使得第二表面102b面朝上。之后,可以通过平坦化工艺去除衬底102的第二表面102b、导电过孔120和过孔绝缘层122的一部分。通过平坦化工艺蚀刻衬底102的第二表面102b,以形成腔体104和通孔106。此外,可以通过平坦化工艺去除第一半导体芯片110的一部分并且可以去除附接至第一半导体芯片110的粘合剂117’。在实施例中,在平坦化工艺之后,粘合剂117’的一部分可以不被蚀刻,并且可以保留在第一半导体芯片110的侧表面上。可以执行平坦化工艺而无需形成从下面支撑第二半导体芯片150和密封剂154的载体。
参照图17,可以在衬底102的第二表面102b上形成第二再分配层140。第二再分配层140可以包括由多个层组成的互连图案142和连接互连图案142的多个层的过孔144。可以通过以上参照图14描述的方法形成第二再分配层140。在形成第二再分配层140之后,可以部分地蚀刻第二再分配层140的上表面,以形成开口146。互连图案142可以经由开口146暴露至外部。
参照图2,可以在图17的第二再分配层140上形成外部连接元件160。外部连接元件160可以连接至第二再分配层140的暴露的互连图案142。在实施例中,外部连接元件160可以是焊料球。焊料球可包括锡(Sn)、银(Ag)、铜(Cu)、钯(Pd)、铋(Bi)或锑(Sb)中的至少一种。
参照图1,可以沿晶片10上的划片线30执行切单工艺。通过切单工艺完成半导体封装件100。
根据发明构思的示例实施例,通过在硅衬底中形成导电过孔可以获得细小的中心距,从而减小半导体封装件的尺寸。
根据发明构思的示例实施例,可以在半导体芯片的侧表面上形成间隔件,因此可以在不形成支撑晶片的载体的情况下制造半导体封装件。
根据发明构思的示例实施例,再分配层可以形成为电连接至半导体芯片的上部分和下部分,因此可以获得高性能的半导体封装件。
虽然已经参考附图描述了发明构思的实施例,但是本领域技术人员应该理解,在不脱离发明构思的范围的情况下可以进行各种修改。因此,上述实施例应仅被认为是描述性的,而不是为了限制的目的。
Claims (20)
1.一种半导体封装件,包括:
硅衬底,其包括腔体和与所述腔体间隔开的多个通孔;
第一半导体芯片,其位于所述腔体中;
多个导电过孔,其位于所述多个通孔中;
第一再分配层,其位于所述硅衬底上,所述第一再分配层连接至所述第一半导体芯片和所述多个导电过孔;以及
第二再分配层,其位于所述硅衬底下方,所述第二再分配层连接至所述第一半导体芯片和所述多个导电过孔。
2.根据权利要求1所述的半导体封装件,还包括:
第一密封剂,其位于所述腔体中,所述第一密封剂位于所述腔体的内侧表面和所述第一半导体芯片的侧表面之间。
3.根据权利要求2所述的半导体封装件,还包括:
粘合剂,其位于所述腔体中,其中,
所述粘合剂位于所述第一密封剂和所述第二再分配层之间。
4.根据权利要求1所述的半导体封装件,其中,
所述第一半导体芯片的上端和所述第一半导体芯片的下端分别位于与所述硅衬底的上端和所述硅衬底的下端相同的水平高度处。
5.根据权利要求1所述的半导体封装件,其中,
所述第一半导体芯片包括贯通电极,并且
所述贯通电极沿竖直方向穿过所述第一半导体芯片。
6.根据权利要求1所述的半导体封装件,其中所述多个通孔围绕所述腔体。
7.根据权利要求1所述的半导体封装件,还包括:
过孔绝缘层,其位于所述多个通孔的每一个中,以覆盖所述多个导电过孔的外侧。
8.根据权利要求1所述的半导体封装件,其中,所述多个通孔的直径为2μm至50μm。
9.一种半导体封装件,包括:
硅衬底,其包括腔体和与所述腔体间隔开的多个通孔;
第一半导体芯片,其位于所述腔体中;
多个导电过孔,其位于所述多个通孔中;
第一再分配层,其位于所述硅衬底上,所述第一再分配层连接至所述第一半导体芯片和所述多个导电过孔;
第二再分配层,其位于所述硅衬底下方,所述第二再分配层连接至所述第一半导体芯片和所述多个导电过孔;以及
第二半导体芯片,其位于所述第一再分配层上,所述第二半导体芯片连接至所述第一再分配层。
10.根据权利要求9所述的半导体封装件,其中,所述第一半导体芯片构造为经由所述第二再分配层电连接至外部器件。
11.根据权利要求9所述的半导体封装件,还包括:
外部连接元件,其经由所述第一再分配层、所述导电过孔和所述第二再分配层电连接至所述第二半导体芯片。
12.根据权利要求9所述的半导体封装件,其中,所述第一半导体芯片经由所述第一再分配层电连接至所述第二半导体芯片。
13.根据权利要求9所述的半导体封装件,还包括:
多个第二半导体芯片,其位于所述第一再分配层上,其中,
所述多个第二半导体芯片包括所述第二半导体芯片,并且所述多个第二半导体芯片经由所述第一再分配层彼此电连接。
14.根据权利要求9所述的半导体封装件,还包括:
上焊盘,其位于所述第一半导体芯片上;
下焊盘,其位于所述第一半导体芯片下方;以及
贯通电极,其沿竖直方向穿过所述第一半导体芯片,
其中,所述上焊盘和所述下焊盘经由所述贯通电极彼此电连接。
15.根据权利要求9所述的半导体封装件,其中,所述多个通孔的直径为2μm至50μm。
16.一种半导体封装件,包括:
硅衬底,其包括腔体和与所述腔体间隔开的多个通孔;
第一半导体芯片,其位于所述腔体中;
第一再分配层,其位于所述硅衬底上;
第二再分配层,其位于所述硅衬底下方,所述第二再分配层连接至所述第一半导体芯片;
第二半导体芯片,其位于所述第一再分配层上,所述第二半导体芯片连接至所述第一再分配层;
第三半导体芯片,其位于所述第一半导体芯片上,所述第三半导体芯片连接至所述第一再分配层;以及
多个导电过孔,其位于所述多个通孔中。
17.根据权利要求16所述的半导体封装件,还包括:
第一密封剂,其位于所述腔体中,其中,
所述第一密封剂位于所述腔体的内侧表面和所述第一半导体芯片的侧表面之间。
18.根据权利要求16所述的半导体封装件,其中,所述第一半导体芯片经由所述第三半导体芯片电连接至所述第一再分配层。
19.根据权利要求16所述的半导体封装件,其中,所述第三半导体芯片经由所述第一半导体芯片电连接至所述第二再分配层。
20.根据权利要求16所述的半导体封装件,其中,所述第二半导体芯片经由所述第一再分配层和所述第三半导体芯片电连接至所述第一半导体芯片。
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