CN113517220A - 半导体器件及其制造方法和制造半导体结构的方法 - Google Patents
半导体器件及其制造方法和制造半导体结构的方法 Download PDFInfo
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- CN113517220A CN113517220A CN202110307241.0A CN202110307241A CN113517220A CN 113517220 A CN113517220 A CN 113517220A CN 202110307241 A CN202110307241 A CN 202110307241A CN 113517220 A CN113517220 A CN 113517220A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 144
- 238000004519 manufacturing process Methods 0.000 title claims description 27
- 238000002161 passivation Methods 0.000 claims abstract description 114
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 62
- 239000004020 conductor Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 3
- 238000009826 distribution Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 description 17
- 239000000523 sample Substances 0.000 description 17
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 229910052710 silicon Inorganic materials 0.000 description 12
- 239000010703 silicon Substances 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 229910045601 alloy Inorganic materials 0.000 description 9
- 239000000956 alloy Substances 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 229910052763 palladium Inorganic materials 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 229910052759 nickel Inorganic materials 0.000 description 6
- 238000012545 processing Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 238000001465 metallisation Methods 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000000227 grinding Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000007654 immersion Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 239000011135 tin Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
- H01L2224/02311—Additive methods
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- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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Abstract
半导体器件包括位于电路上方的第一钝化层和位于第一钝化层上方的导电焊盘,其中,导电焊盘电连接至电路。第二钝化层设置在导电焊盘和第一钝化层上方,并且具有第一开口和第二开口。第一开口暴露在导电焊盘下面延伸的层的上表面,并且第二开口暴露导电焊盘。第一绝缘层设置在第二钝化层上方并填充第一开口和第二开口。衬底通孔延伸穿过绝缘层、第二钝化层、钝化层和衬底。衬底通孔和第二钝化层的侧具有填充有第一绝缘层的间隙。导电通孔延伸穿过第一绝缘层并连接至导电焊盘。本申请的实施例还涉及制造半导体结构和半导体器件的方法。
Description
技术领域
本申请的实施例涉及半导体器件及其制造方法和制造半导体结构的方法。
背景技术
由于各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度的不断提高,半导体行业经历了快速的增长。大部分情况下,这种集成密度的提高源于最小部件尺寸的不断减小,从而使得更多的组件集成到特定区域中。随着近来对更小电子器件的需求增长,对半导体管芯的更小且更具创造性的封装技术的需求也在增长。
随着半导体技术的进一步发展,诸如,3D集成电路(3DIC)封装件的堆叠式半导体器件已经出现作为进一步减小半导体器件的物理尺寸的有效替代方案。在堆叠的半导体器件中,有源电路(诸如逻辑、存储器、处理器电路等)在不同半导体晶圆上制造。可以在彼此之上安装两个或更多个半导体组件,以进一步减少半导体器件的形状因数。
先进封装技术的高集成度使得能够制造具有增强功能和小覆盖区的半导体器件,这对于小形状因数器件(诸如移动电话、平板电脑和数字音乐播放器)是有利的。另一优势是缩短了连接半导体器件内的互操作部分的导电路径的长度。这提高了半导体器件的电性能,因为电路之间互连的较短布线产生更快的信号传播并且减少了噪声和串扰。
发明内容
本申请的一些实施例提供了一种制造半导体器件的方法,包括:提供半导体衬底;在所述半导体衬底上方形成导电焊盘;在所述导电焊盘上方形成钝化层;在所述钝化层中形成第一开口和第二开口,其中,所述第二开口暴露所述导电焊盘,并且其中,所述第一开口与所述导电焊盘间隔开,并暴露在所述导电焊盘下面延伸的层的上表面;在所述第一开口中形成第一导电通孔,其中,所述第一导电通孔延伸至所述半导体衬底中;以及在所述第二开口中形成第二导电通孔,其中,所述第二导电通孔连接至所述导电焊盘。
本申请的另一些实施例提供了一种制造半导体结构的方法,包括:提供其上形成有电路的衬底,其中,所述衬底具有第一区域和第二区域;在所述电路上方形成第一钝化层;在所述第一钝化层上方形成导电焊盘,其中,所述导电焊盘电连接至所述电路;在所述导电焊盘和所述第一钝化层上方形成第二钝化层,其中,所述第二钝化层在所述第一区域中具有第一开口并且在所述第二区域中具有第二开口,其中,所述第一开口暴露在所述导电焊盘下方延伸的层的上表面,并且所述第二开口暴露所述导电焊盘;在所述第二钝化层上方形成第一绝缘层,其中,所述第一绝缘层填充所述第一开口和所述第二开口;在所述第一区域中形成第一导电通孔,其中,所述第一导电通孔具有在所述第一开口中的至少一部分并且从所述第一绝缘层延伸至所述半导体衬底中;以及在所述第二区域中形成第二导电通孔,其中,所述第二通孔具有在所述第二开口中的至少一部分并且连接至所述导电焊盘。
本申请的又一些实施例提供了一种半导体器件,包括:衬底,其上形成有电路;第一钝化层,位于所述电路上方;导电焊盘,位于所述第一钝化层上方并且电连接至所述电路;第二钝化层,位于所述导电焊盘和所述第一钝化层上方,其中,所述第二钝化层具有第一开口和第二开口,所述第一开口暴露在所述导电焊盘下面延伸的层的上表面,所述第二开口暴露所述导电焊盘;第一绝缘层,设置在所述第二钝化层上方并填充所述第一开口和所述第二开口;衬底通孔,至少部分地与所述第二开口对准并延伸穿过所述第一绝缘层、所述第二钝化层、所述第一钝化层和所述衬底,其中,所述衬底通孔和所述第二钝化层的侧具有填充有所述第一绝缘层的间隙;以及导电通孔,延伸穿过所述第一绝缘层并连接至所述导电焊盘。
附图说明
当与附图一起阅读时,根据以下具体实施方式可以最佳理解本发明的各方面。应注意,根据行业中的标准实践,各种部件未按比例绘制。实际上,为了清楚的论述,各种部件的尺寸可以任意增大或减小。
图1A至图1K是示出根据本发明的一些示例性实施例的半导体器件的制造方法中的各个阶段的示意性横截面视图。
图2A至图2B是示出根据本发明的一些示例性实施例的半导体器件的制造方法中的各个阶段的示意性横截面视图。
图3A至图3B是示出根据本发明的一些示例性实施例的半导体器件的制造方法中的各个阶段的示意性横截面视图。
图4A至图4B是示出根据本发明的一些示例性实施例的半导体器件的制造方法中的各个阶段的示意性横截面视图。
图5A是示出根据本发明的一些示例性实施例的半导体器件的制造方法中的阶段的示意性截面图。
图5B是示出根据本发明的一些示例性实施例的半导体器件的制造方法中的阶段的示意性顶部图。
图6是示出根据本发明的一些示例性实施例的器件堆叠件的示意性截面图。
图7是根据本发明的一些示例性实施例的半导体器件的应用。
图8是示出根据本发明的一些示例性实施例的器件堆叠件的示意性截面图。
图9是根据本发明的一些示例性实施例的半导体器件的应用。
具体实施方式
以下公开提供了多个不同的实施例或实例,用于实施本发明的不同部件。下面描述了组件与布置的具体实例,以简化本发明。当然,这些仅是实例,并非旨在限制本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。
而且,为了便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
图1A示出了处于制造的中间阶段的半导体器件100。半导体器件100可以是半导体晶圆或与半导体晶圆分离的半导体管芯。半导体器件100包括半导体衬底110,诸如掺杂或未掺杂的硅,或绝缘体上半导体(SOI)衬底的有源层。半导体衬底110可以包括其它半导体材料,例如锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、氮化镓、磷化铟,砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或其组合。其它衬底,诸如多层或渐变衬底,也可以使用。有源和/或无源器件,诸如晶体管、二极管、电容器、电阻器等,可以在半导体衬底110中和/或之上形成。
在一些实施例中,半导体衬底具有第一区域101和第二区域102。可以在第一区域101和第二区域102中形成不同部件。例如,可以在第一区域101中形成导电通孔。在第一区域101中或至少在将要形成导电通孔的区域中没有形成有源或钝化器件,除了在一些实施例中,可能期望导电通孔电接触互连结构的一部分,如下所述。有源和无源器件可以在半导体衬底110的第二区域102和其他区域中形成。尽管为了清楚仅示出了一个区域102和一个区域101,但是本领域技术人员将认识到,可以在具有不同结构的典型集成电路上形成多个这样的区域。例如,在一些实施例中,区域101可以分散在多个区域102之中,而在其他实施例中,可以在区域102的外围周围形成单个区域101或区域101的阵列。
在实施例中,半导体器件100包括在半导体衬底110上方的互连结构114。互连结构114可以在一个或多个介电层114a中包括金属化部件。金属化部件可以包括金属线114b,分布在介电层中,以及通孔114b,以不同水平连接金属线114b。金属化部件可以包括铜、钨、钴、钌、它们的合金或其组合。在一些实施例中,金属线114a和通孔114b可以还包括扩散阻挡层。扩散阻挡层可以包括钛、氮化钛、钽、氮化钽或其组合。在一些实施例中,互连结构114可以通过一个或多个单镶嵌工艺、一个或多个双镶嵌工艺或其组合形成。
在一些实施例中,介电层114a具有至少一层由氧化硅或低k介电材料形成的层。低k介电材料的介电常数(k值)低于3.9。在一些实施例中,低k介电材料的介电常数低于约3.0或低于约2.7。例如,低k介电材料可以由黑金刚石(应用材料的注册商标)、含碳的低k材料、多孔低k材料、氢倍半硅氧烷(HSQ)或甲基倍半硅氧烷(MSQ)形成。
半导体器件100包括在互连结构114上方形成的钝化层120。钝化层120可以由氮化硅、氮氧化硅、碳氮化硅、聚合物、其他材料或其组合形成,能够防止下面的互连结构114受到有害化学物质和水分的不利影响。在实施例中,钝化层120具有约0.3μm至约2.5μm的厚度。钝化层120可以通过化学气相沉积(CVD)、等离子体增强CVD(PECVD)或其他合适的工艺形成。在一些实施例中,钝化层120具有平坦的上表面。
在第二区域102中的第一钝化层120上方形成导电焊盘130a,可选地称为测试焊盘。导电焊盘130a可以由铝或其合金(诸如铝-铜合金)形成。导电焊盘130a可以具有约2μm至约500μm的直径,或者可选地为矩形(或另一多边形)的形状,其侧面具有相同尺寸。连接至导电焊盘的导电线的直径或宽度通常在约1.5μm至约30μm的范围内。在一些实施例中,导电焊盘130a包括探针标记132。探针标记132可以在与测试设备接触之后形成,例如,探针卡的尖端或针,其会划伤,刮伤或以其他方式冲击导电焊盘的表面。探针标记132可以是包括从导电焊盘130a的上表面凹入的中心部分和在导电焊盘130a的上表面上突出并环绕该中心部分的环形部分的结构。探针标记132可以具有任何形状,诸如圆形、正方形、矩形、椭圆形或其他可能的形状。探针标记132的直径通常可以在约10μm至约300μm的范围内,尽管这仅是示例性的而非限制性的,其通常位于导电焊盘130a的中心或附近。在所示的实施例中,由于设计或未对准,探针标记132偏离导电焊盘130a的中心。在一些实施例中,探针标记132部分地占据导电焊盘130a的上表面,并留出适当的空间用于接合在导电焊盘130a上的通孔。
在一些实施例中,导电线130b以与导电焊盘130a相同的水平形成并且连接至导电焊盘130a。导电焊盘130a和导电线130b可以由相同的材料形成并且可以在相同的图案化工艺中一起形成。在实施例中,在导电焊盘130a或导电线130b下方形成导电通孔134,以将互连结构114电连接至导电焊盘130a或导电线130b。
钝化膜122在钝化层120上方形成并且覆盖导电焊盘130a。钝化层122可以包括一层或多层。例如,钝化层122可以是包括层122a和层122b的双层结构。层122a可以由氮化硅、氮氧化硅或其他合适的材料形成。层122b可以由氧化硅、掺硼硅玻璃(BSG)或掺磷硅玻璃(PSG)、其他类似材料或其组合形成。层122a可以具有约0.3μm至约1.5μm的厚度。层122b通常可以具有约0.6μm至约3μm的厚度。层122b可以通过减轻层122a产生的应力来为导电焊盘130a提供缓冲。在一些实施例中,钝化层122通过沉积工艺(诸如CVD、PECVD)形成,并且具有与导电焊盘130a的分布共形的上表面。
如图1B所示,在第一区域101中的钝化层122中形成开口140。开口140暴露第一钝化层120。开口140可以具有约1μm至约200μm的直径。在第二区域102中的钝化层122中形成开口142。开口142暴露导电焊盘130a和探针标记132。开口142可以具有例如约2μm至约500μm的直径。在一些实施例中,开口142与导电焊盘130a的中心对准而不暴露导电焊盘130a的侧壁。在其他实施例中,开口142与导电焊盘部分对准,并暴露导电焊盘130a的侧壁(图中未示出)。在实施例中,开口140和开口142以相同的图案化工艺形成。尽管仅示出了单个开口140和单个开口142,但是应当理解,具有不同尺寸、图案和结构的多个开口140和142在本发明的预期范围内。图案化工艺可以包括在钝化层122上方形成光刻胶层(未示出);通过光刻对光刻胶层进行图案化以形成光刻胶层中的开口140和142的图案,并且使用导电焊盘130a和第一钝化层120作为蚀刻停止层根据光刻胶层中的图案来蚀刻钝化层122。本发明的范围不限于光刻图案化,并且其他图案化技术,诸如离子束、电子束等,也在预期的范围内。
如图1C所示,在钝化层122上方形成绝缘层150。在一些实施例中,绝缘层150填充开口140和142。绝缘层150可以具有平坦的上表面,以在其上形成后续的导电层。例如,可以通过在钝化层122上方沉积膜并在膜上执行平坦化工艺(诸如化学机械抛光(CMP)、回蚀刻工艺或机械研磨)来形成绝缘层150。在其他实施例中,绝缘层150可以使用提供足够平坦的表面以避免需要平坦化步骤的技术进行沉积。绝缘层150可以包括氧化硅或其他类似的材料。在一些实施例中,在形成绝缘层150之前,通过将测试设备(例如,探测卡)连接至导电焊盘130a来测试半导体器件100的功能或电特性。仅当半导体器件100通过功能或电测试时,才进行绝缘层150的形成和后续工艺。
如图1D所示,通过蚀刻绝缘层150、钝化层120、介电层114a和半导体衬底110,在第一区域101中形成通孔152。在一些实施例中,通孔152从绝缘层150延伸穿过钝化层120和介电层114a,并进入半导体衬底110。通孔152至少部分地与第一开口140对准。通孔152可以具有适合于应用的直径。通常,通孔152应在开口140的直径的约0.5倍至约0.9倍的范围内。在一些实施例中,通孔152的尺寸小于第一开口140的尺寸。在其他实施例中,通孔152的尺寸大于第一开口140(图中未示出)。示出的通孔152与互连114的一部分对准,其中没有形成线114b或通孔114c。然而,在其他实施例中,可以定位通孔152,以使得随后形成的导电通孔154(图1E)可以电连接至互连结构114内的一条或多条线114b。
如图1E所示,导电材料填充有通孔152以形成导电通孔154。导电通孔154可以与钝化层122水平间隔开,但是与钝化层120接触。导电通孔154的一侧与钝化层122之间的间隙被绝缘层150填充。导电材料可以包括铜、铝、银、金、铂、钯、钨及其合金。可以通过例如在绝缘层150上方和在通孔152的开口中形成晶种层,在晶种层上方镀(例如,电镀或化学镀)导电材料,然后通过平坦化工艺(诸如CMP)去除过量填充通孔152的导电材料以形成导电通孔154。在一些实施例中,晶种层可以包括铜的子层和阻挡层的子层(例如,钛、氮化钛、钽、氮化钽或其组合)。形成导电通孔154的其他方法是可能的,并且旨在完全包括在本发明的范围内。同样,本领域的技术人员将认识到,形成导电通孔154可以包括形成一个或多个介电衬垫、阻挡衬垫、粘附层等。
如图1F所示,在绝缘层150和导电通孔154上方形成绝缘层160。对绝缘层160进行图案化以具有线沟槽162。线沟槽162可以暴露导电通孔154的至少一部分。线沟槽162可以具有与导电焊盘130a对准的部分。在一个实施例中,绝缘层160由与绝缘层150相同的材料形成,尽管可以使用与绝缘层150不同的材料。例如,绝缘层160可以包括氧化硅或未掺杂或掺杂的硅玻璃。在其他实施例中,绝缘层162可以包括氮化硅、氮氧化硅、碳化硅或其他合适的材料。
如图1G所示,通过蚀刻绝缘层150在第二区域102中形成通孔170。通孔170的形成工艺包括:在绝缘层150和160上方形成具有用于通孔的图案的光刻胶层,并根据光刻胶层的图案蚀刻绝缘层150。在一些实施例中,当光刻胶层的图案暴露绝缘层160的一部分时,当蚀刻绝缘层150时,绝缘层160可以与光刻胶层一起充当掩模。通孔170至少部分地与导电焊盘130a对准。在一个实施例中,通孔170完全接合在导电焊盘130a的上表面上。在其他实施例中,通孔170暴露导电焊盘130a的侧壁的至少一部分。在一些实施例中,通孔170与探针标记132间隔开并且至少部分地与线沟槽162对准。
如图1H所示,沉积导电材料以填充通孔170和线沟槽162以形成导电通孔172和导电线174。导电通孔172在图1H中的端部连接至导电焊盘130a和导电线174之一。在其他实施例中,例如,导电焊盘130a和导电通孔154可以彼此电隔离,或通过互连结构114彼此连接。导电材料可以是但不一定是与用于形成导电通孔154的材料相同的材料。可以通过例如在通孔170和线沟槽162中形成晶种层,在晶种层上方镀(例如,电镀或化学镀)导电材料,然后通过平坦化工艺(诸如CMP)去除过量填充线沟槽162的导电材料以形成填充工艺。在一些实施例中,晶种层可以包括铜的子层和阻挡层的子层(例如,钛、氮化钛、钽或氮化钽)。用于形成导电通孔172和导电线174的其他方法是可能的,并且旨在完全包括在本发明的范围内。
如图1I所示,在一些实施例中,在绝缘层160和导电线174上方形成绝缘层180和接合焊盘182。绝缘层180可以包括氧化硅、氮氧化硅、氮化硅或其组合。在实施例中,接合焊盘182连接至导电通孔174。接合焊盘182包括铜或其他合适的金属或导体,或其合金。接合焊盘182可以通过镶嵌工艺形成。在一些实施例中,图1A所示的半导体器件100为晶圆形式,并且执行切割工艺以将半导体器件100分离成管芯形式。可选地,晶圆级集成在本发明的预期范围内,并且器件100(或本文示出的其他器件)可以涵盖整个晶圆。
如图1J所示,从半导体衬底110的背面(与互连结构114相对的一侧)去除半导体衬底110的一部分,以露出导电通孔174的一部分。因此,导电通孔174成为衬底通孔(TSV)。可以通过研磨工艺去除半导体衬底110。如图1K所示,在半导体衬底110的背面上方形成氧化层190(例如,氧化硅)。在一些实施例中,可以通过氧化工艺(诸如热氧化|化学氧化或其组合)形成氧化物层190。
在上述实施例中,钝化层120和122包括硬质材料,诸如氮化硅或氮氧化硅,与其他绝缘/介电层相比,其相对难以蚀刻。例如,在蚀刻具有不同性质的多层时,将难以控制蚀刻速率和蚀刻分布。通过与用于测试目的而形成的开口142一起形成开口140,用于形成通孔172的蚀刻工艺将更易于控制,因为仅需要蚀刻一层钝化层122。
图2A至图2B示出了根据本发明的一些实施例的制造半导体器件200的中间阶段。除了在第一区域101中的钝化层122和钝化层120中形成开口240之外,图2A中的半导体器件200与图1A中所示的半导体器件100相同。开口240暴露下面的介电层114a。在实施例中,以与使用介电层114a作为蚀刻停止层来形成开口142相同的蚀刻工艺来形成开口240。同样,导电焊盘130a可以用作开口142中的蚀刻停止层。
在其他实施例中,在图1A所示的半导体器件100中形成开口140和142之后,通过执行另一蚀刻工艺以蚀刻钝化层120来形成开口240。例如,形成开口240的工艺可以包括形成具有图案的光刻胶层,该图案至少部分地与开口140重叠;根据光刻胶层的图案和开口140的分布,执行蚀刻工艺以去除钝化层120的一部分;以及去除光刻胶层。
在形成开口240之后,执行图1B至图1K所示的类似制造步骤,并且在图2B中示出所得的半导体器件200。在实施例中,绝缘层150填充开口240并且与互连结构114的介电层114a接触。在以上实施例中,当执行用于形成通孔172的蚀刻工艺时,蚀刻工艺不需要穿透钝化层120,这有助于更容易地控制蚀刻工艺。
图3A至图3B示出了根据本发明的一些实施例的制造半导体器件300的中间阶段。除了半导体器件300具有第三区域103之外,此阶段的半导体器件300与图1A所示的半导体器件100相同。互连结构114的金属化部件在第三区域103中形成,而没有在其上布置测试焊盘130a。互连结构114的金属化部件可以包括位于互连结构114的顶层的连接焊盘314b。因为钝化层120没有被导电焊盘130a覆盖,所以在钝化层122中形成开口344并且暴露钝化层120。在实施例中,在相同蚀刻工艺中,开口344与开口140和142一起形成。
在形成开口344之后,执行图1B至图1K所示的类似制造步骤,并且在图3B中示出所得的半导体器件300。制造步骤还包括在第三区域103中的绝缘层150中形成导电通孔376。导电通孔376从绝缘层150延伸,穿过钝化层120,并接合在互连结构114的314b的连接焊盘上。导电通孔376可以但不是必须也连接至导电线174。
在一些实施例中,连接焊盘未必形成在介电层的顶层上。例如,图4A示出了位于第四区域104中的介电层114a的中间或较低水平处的连接焊盘414b。在实施例中,可以在互连结构的介电层的不同层上形成焊盘,并且导电通孔落在不通水平的连接焊盘上。例如,图4A示出了位于第三区域103中的介电层114a的较高水平处的连接焊盘314b和位于第四区域104中的介电层114a的较低水平处的连接焊盘414a。在一些实施例中,开口446在钝化层122中形成并且暴露钝化层120。开口446可以在相同的蚀刻工艺中与开口140、142和344一起形成。在其他实施例中,在图1A所示的半导体器件100处形成开口140和142之后,通过额外的蚀刻工艺形成开口446。
在形成开口446之后,执行图1B至图1K所示的类似制造步骤,并且在图4B中示出所得的半导体器件400。在第四区域104中形成导电通孔478。在一些实施例中,导电通孔478延伸穿过绝缘层150,穿过钝化层120和介电层114a的上层,以物理连接位于介电层114a的下层的连接焊盘414b。在一些实施例中,导电通孔在不同区域中的介电层的不同水平处落在连接焊盘上。例如,导电通孔376落在位于第三区域103中的介电层114a的最高水平处的连接焊盘314b上,并且导电通孔478落在位于第四区域104中的介电层114a的较低水平处的连接焊盘414b上。
应当注意,与图2A中公开的工艺相反,图3A至图3B和图4A至图4B的实施例均使用其中形成第一开口的工艺,该第一开口穿透钝化层122并且在绝缘层150之前停止在钝化层120上或暴露钝化层120,其中,在形成绝缘层150之前,第一开口穿过钝化层122和120。在本发明的预期范围内,可以使用关于图2A描述的工艺来形成参考图3A至图3B和图4A至图4B描述的结构,在这种情况下,在成品中绝缘层150将同样地与互连结构114接触。
图5A示出了根据本发明的一些实施例的制造半导体器件500的中间阶段。除了在探针标记132周围形成多个导电通孔172’之外,图5A中的半导体器件500与图1K中所示的半导体器件100相同。例如,图5B示出了半导体器件500的导电焊盘部分130a处的顶部图。探针标记形成在导电焊盘130a的中心处或附近132,并且多个导电通孔172’位于导体130a的外围部分并且环绕探针标记132。在一些实施例中,导电通孔172’的直径可以小于导电通孔172的直径。根据一些实施例,导电通孔172’中的至少一个可以与探针标记132横向间隔开。可以通过与形成导电通孔172的工艺类似的工艺形成导电通孔172’,但是具有不同的光刻图案。应当注意,如图1K、图2B、图3B或图4B所示,导电通孔172’也可以在半导体器件100、200、300或400中使用。
图6示出了根据本发明的一些实施例的器件堆叠件600。在一些实施例中,器件堆叠件600包括堆叠在另一半导体器件610’上方的半导体器件610。半导体器件610和半导体器件610’中的每个可以根据如前述实施例中所示的方法进行制造。例如,如图1K、图2B、图3B、图4B或图5A所示,每个半导体器件610和610’可以是半导体器件100、200、300、400或500。在实施例中,半导体器件610和半导体器件610’具有相同的集成电路设计。在其他实施例中,半导体器件610和半导体器件610’具有不同的集成电路设计。例如,半导体器件610和半导体器件610’可以包括应用处理器(AP)、中央处理单元、微控制器、射频单元、传感器、微机电系统(MEMS)、功率管理单元、信号处理单元(例如,数字信号处理(DSP)单元)、模拟单元等。
在一些实施例中,半导体器件610和610’以混合接合配置接合。半导体器件610和610’面向下放置,使得半导体器件610的前侧可以面对半导体器件610’的后侧。在混合接合配置中,穿过氧化物-氧化物接合将半导体器件610的氧化物层190接合至半导体器件610’的绝缘层180,并且通过金属-金属接合将半导体器件610的导电通孔154接合至半导体器件510’的接合焊盘182。可以通过对准半导体器件610和半导体器件610’并且将器件610和610’加热至约150℃至350℃的温度持续约0.5小时至4小时的时间来形成混合接合配置。在一些实施例中,导电通孔154和接合焊盘182的金属原子彼此相互扩散以形成半导体器件610和610’的金属-金属接合,并且通过接合焊盘182到导电通孔154的物理连接提供电连接。
在一些实施例中,半导体器件610和610’可以进一步堆叠在另一个半导体器件610’上并电连接(通过混合接合或其他技术)。半导体器件610”可以与半导体器件610或610’相同。在其他实施例中,半导体器件610”可以是半导体器件100、200、300、400或500之一。连接件614可以形成在半导体器件610”的有源侧上,以将器件堆叠件600连接至衬底或另一封装件。在一些实施例中,连接件614可以是球栅阵列(BGA)连接件、无铅焊球、可控塌陷连接(C4)凸块、化学镀镍化学镀钯浸金(ENEPIG)形成的凸块等。连接件614可以包括导电材料,诸如焊料、金、镍、银、钯、锡等、或它们的组合。在一些实施例中,UBM(凸块下金属)612在接合焊盘182与连接件614之间形成。UBM 614可以为连接件614提供更好的粘合力和应力缓冲。UBM 614可以包括由铜、钛、钨、铝等形成的材料。
图7示出了根据本发明的一些实施例的多芯片封装件700。多芯片封装件700可以包括器件堆叠件600和存储器堆叠件702。器件堆叠件600和存储器堆叠件702水平地布置在中介层710上,并通过连接件614和704连接至中介层710。存储器堆叠件702可以包括多个存储器芯片,诸如动态随机存取存储器(DRAM)芯片、静态随机存取存储器(SRAM)芯片、电阻性随机存取裸片(RRAM)芯片、磁阻随机存取存储器(MRAM)芯片等。中介层710可以具有或不具有形成于其内或之上的有源电路。中介层710包括贯通导电通孔712,以通过连接件714将器件堆叠件600和存储器堆叠件700电连接至衬底720。在一些实施例中,衬底720是印刷电路板。连接件614、704和714可以是球栅阵列(BGA)连接件、无铅焊球、可控塌陷连接(C4)凸块、化学镀镍化学镀钯浸金(ENEPIG)形成的凸块等。连接件614、704和714可以包括导电材料,诸如焊料、金、镍、银、钯、锡等,或其组合。
图8示出了根据本发明的一些实施例的包括多个半导体器件的器件堆叠件800。在一些实施例中,器件堆叠件800包括堆叠在另一半导体器件810’上方的半导体器件810,该另一半导体器件810’又堆叠在半导体器件810”上方。可以根据前述实施例中所示的方法制造图8的半导体器件中的每个或至少一个。例如,每个半导体器件或至少一个半导体器件可以是如图1K、图2B、图3B、图4B或图5A所示的半导体器件100、200、300、400或500。在实施例中,半导体器件具有相同的集成电路设计。在其他实施例中,半导体器件具有不同的集成电路设计。例如,图8中的每个或至少一个半导体器件可以包括应用处理器(AP)、中央处理单元、微控制器、射频单元、传感器、微机电系统(MEMS)、功率管理单元、信号处理单元(例如,数字信号处理(DSP)单元)、模拟单元等。
在一些实施例中,连接件814是形成在焊盘182上方的金属柱(例如,Cu柱)。金属柱可以通过电镀形成。然后,将聚合物层816沉积在绝缘层180上方并环绕连接件814。在一些实施例中,聚合物层816包括聚苯并噁唑(PBO)、聚酰亚胺(PI)、苯并环丁烯(BCB)等。
图9示出了根据本发明的一些实施例的扇出多芯片封装件900。扇出多芯片封装件900可以包括:上部封装件910,其包括存储器堆叠件;以及下部封装件920,其包括器件堆叠件800。上部封装件910的存储器堆叠件可以包括多个存储器芯片。存储器堆叠件可以包括多个存储器芯片,诸如动态随机存取存储器(DRAM)芯片、静态随机存取存储器(SRAM)芯片、电阻性随机存取裸片(RRAM)芯片、磁阻随机存取存储器(MRAM)芯片等。
下部封装件920包括由封装层922(例如,模塑料)围绕的器件堆叠件800。下部封装件920包括多个绝缘通孔926,其设置在器件堆叠件800周围并且穿过封装材料922。下部封装件920包括设置在器件堆叠件800和封装材料922上方的扇出再分布层924。器件堆叠件800通过连接件814连接至扇出再分布层924。在一些实施例中,下部封装件920通过在载体衬底上形成多个绝缘通孔926;将器件堆叠件800设置在载体衬底上方,其连接件814面向远离载体衬底的一侧;通过绝缘通孔926将密封层922填充到器件堆叠件800之间的空间中;通过绝缘通孔926和包封层922研磨连接件814以形成平坦表面;在表面上形成扇出再分布层924形成。在一些实施例中,载体衬底是玻璃晶圆或玻璃面板。
上部封装件910通过连接件912设置在下部封装件920上。因此,器件堆叠件800通过连接件604、再分布层924、绝缘通孔926和连接件912电连接至上部封装件。在一些实施例中,上部封装件910和下部封装件920的封装堆叠件通过连接件928设置在衬底(例如,印刷电路板)上方。连接件912和924可以包括球栅阵列(BGA)连接件、无铅焊球、可控塌陷连接(C4)凸块、化学镀镍化学镀钯浸金(ENEPIG)形成的凸块等。连接件912和928可以包括导电材料,诸如焊料、金、镍、银、钯、锡等,或其组合。
应当注意,图9所示的封装器件不限于器件堆叠件800,而在其他实施例中,器件堆叠件600可以在下部封装件920内使用。同样地,图7所示的封装件不限于器件堆叠件600,并且可以想到可以在其中采用器件堆叠件800。
根据本发明的一些实施例,提供了制造半导体器件的方法。该方法包括提供半导体衬底;在所述半导体衬底上方形成导电焊盘;在所述导电焊盘上方形成钝化层;在所述钝化层中形成第一开口和第二开口,其中,所述第二开口暴露所述导电焊盘,并且其中,所述第一开口与所述导电焊盘间隔开,并暴露在所述导电焊盘下面延伸的层的上表面;在所述第一开口中形成第一导电通孔,其中,所述第一导电通孔延伸至所述半导体衬底中;以及在所述第二开口中形成第二导电通孔,其中,所述第二导电通孔连接至所述导电焊盘。
在一些实施例中,所述钝化层具有与所述导电焊盘的分布共形的上表面。在一些实施例中,方法还包括:在所述钝化层上方沉积第一绝缘层并填充所述第一开口和所述第二开口;以及平坦化所述第一绝缘层。在一些实施例中,形成所述第一导电通孔的步骤包括:蚀刻平坦化的第一绝缘层、所述层和所述半导体衬底以形成第一通孔;其中,所述第一通孔至少部分地与所述第一开口对准;以及用导电材料填充所述第一通孔。在一些实施例中,方法还包括:在所述平坦化的第一绝缘层和所述第一导电通孔上方形成第二绝缘层;在所述第二绝缘层中形成线沟槽,其中,所述线沟槽具有暴露所述第一导电通孔的至少一部分;形成暴露所述导电焊盘的第二通孔,其中,所述第二通孔至少部分地与所述线沟槽对准;以及将所述导电材料填充到所述线沟槽和所述第二通孔中。在一些实施例中,形成所述第二导电通孔的步骤包括:蚀刻所述平坦化的第一绝缘层以形成第二通孔,其中,所述第二通孔至少部分地与所述第二开口对准并且暴露所述导电焊盘;以及在所述第二通孔中填充导电材料。在一些实施例中,方法还包括在所述半导体衬底上方形成互连结构,其中,在所述导电焊盘下方延伸的所述层是设置在所述钝化层与所述互连结构之间的层或设置在所述互连结构中的层。在一些实施例中,所述互连结构具有与所述第一导电过孔和所述导电焊盘间隔开的连接焊盘,并且所述方法还包括形成第三导电通孔,所述第三导电通孔延伸穿过所述第一绝缘层并连接至所述互连结构的所述连接焊盘。在一些实施例中,所述导电焊盘具有探针标记,并且所述第二导电通孔与所述探针标记横向间隔开。在一些实施例中,方法还包括:从所述半导体衬底的背面研磨所述半导体衬底以露出所述第一导电通孔;以及在所述半导体衬底的背面上方形成氧化物层。
根据可选的实施例,提供了制造半导体器件的方法。该方法包括提供其上形成电路的衬底,其中,所述衬底具有第一区域和第二区域;在所述电路上方形成第一钝化层;在所述第一钝化层上方形成导电焊盘,其中,所述导电焊盘电连接至所述电路;在所述导电焊盘和所述第一钝化层上方形成第二钝化层,其中,所述第二钝化层在所述第一区域中具有第一开口,并且在所述第二区域中具有第二开口,其中,所述第一开口暴露在导电焊盘下方延伸的层的上表面,并且所述第二开口暴露所述导电焊盘;在所述第二钝化层上方形成第一绝缘层,其中,所述第一绝缘层填充所述第一开口和所述第二开口;在所述第一区域中形成第一导电通孔,其中,所述第一导电通孔在所述第一开口中具有至少一部分,并且从所述第一绝缘层延伸至所述半导体衬底中;以及在所述第二区域中形成第二导电通孔,其中,所述第二通孔在所述第二开口中具有至少一部分,并且连接至所述导电焊盘。
在一些实施例中,方法还包括在形成所述第一导电通孔之后,在所述第一绝缘层和所述第一导电通孔上方形成第二绝缘层,其中,所述第二绝缘层具有暴露所述第一导电通孔的至少一部分的线沟槽。在一些实施例中,形成所述第二导电通孔的步骤包括:蚀刻所述第一绝缘层以形成与所述第二绝缘层的所述线沟槽部分地对准并暴露所述导电焊盘的通孔;以及在所述通孔和所述线沟槽中填充导电材料。在一些实施例中,方法还包括在形成所述第一钝化层之前在所述衬底上方形成互连结构,其中,所述互连结构在与所述第一区域和所述第二区域间隔开的第三区域内具有连接焊盘,其中,在所述导电焊盘下方延伸的层是所述互连结构中的所述第一钝化层或绝缘层。在一些实施例中,所述导电焊盘由铝或其合金形成,并且所述连接焊盘由铜或其合金形成。在一些实施例中,所述第一钝化层包括氮化硅、氧氮化硅、碳氮化硅、聚合物或其组合。在一些实施例中,所述第二钝化层包括一个或多个子层,并且所述一个或多个子层中的至少一个包括氧化硅、掺杂硼的硅玻璃或掺杂磷的硅玻璃或其组合。
根据又一可选的实施例,提供了半导体器件。该半导体器件包括衬底,其上形成电路;第一钝化层,位于所述电路上方;导电焊盘,位于所述第一钝化层上方并且电连接至所述电路;第二钝化层,位于所述导电焊盘和所述第一钝化层上方,其中,所述第二钝化层具有第一开口和第二开口,所述第一开口暴露在所述导电焊盘下面延伸的层的上表面,所述第二开口暴露所述导电焊盘;第一绝缘层,设置在所述第二钝化层上方并填充所述第一开口和所述第二开口;衬底通孔,至少部分地与所述第二开口对准并延伸穿过所述第一绝缘层、所述第二钝化层、所述第一钝化层和所述衬底,其中,所述衬底通孔和所述第二钝化层的一侧具有填充所述第一绝缘层的间隙;以及导电通孔,延伸穿过所述第一绝缘层并连接至所述导电焊盘。
在一些实施例中,半导体器件还包括形成互连结构,所述互连结构设置在所述衬底与所述第一钝化层之间,其中,在所述导电焊盘下方延伸的所述层是设置在所述互连结构中的所述第一钝化层或绝缘层。在一些实施例中,半导体器件还包括接合焊盘,设置在所述衬底通孔上方,其中,所述导电焊盘由铝或其合金形成,并且所述接合焊盘由铜或其合金形成。
前述内容概述了几个实施例的特征,从而使得本领域技术人员可以更好地理解本发明的各方面。本领域的技术人员应理解,其可以轻松地将本发明服务于基础,用于设计或修改其他工艺或结构,从而达成与本文所介绍实施例的相同目的和/或实现相同的优点。本领域技术人员还应认识到,这种等效结构并不背离本发明的精神和范围,并且其可以进行各种更改、替换和变更而不背离本发明的精神和范围。
Claims (10)
1.一种制造半导体器件的方法,包括:
提供半导体衬底;
在所述半导体衬底上方形成导电焊盘;
在所述导电焊盘上方形成钝化层;
在所述钝化层中形成第一开口和第二开口,其中,所述第二开口暴露所述导电焊盘,并且其中,所述第一开口与所述导电焊盘间隔开,并暴露在所述导电焊盘下面延伸的层的上表面;
在所述第一开口中形成第一导电通孔,其中,所述第一导电通孔延伸至所述半导体衬底中;以及
在所述第二开口中形成第二导电通孔,其中,所述第二导电通孔连接至所述导电焊盘。
2.根据权利要求1所述的方法,其中,所述钝化层具有与所述导电焊盘的分布共形的上表面。
3.根据权利要求2所述的方法,还包括:
在所述钝化层上方沉积第一绝缘层并填充所述第一开口和所述第二开口;以及
平坦化所述第一绝缘层。
4.根据权利要求3所述的方法,其中,形成所述第一导电通孔的步骤包括:
蚀刻平坦化的第一绝缘层、所述层和所述半导体衬底以形成第一通孔;其中,所述第一通孔至少部分地与所述第一开口对准;以及
用导电材料填充所述第一通孔。
5.根据权利要求4所述的方法,还包括:
在所述平坦化的第一绝缘层和所述第一导电通孔上方形成第二绝缘层;
在所述第二绝缘层中形成线沟槽,其中,所述线沟槽具有暴露所述第一导电通孔的至少一部分;
形成暴露所述导电焊盘的第二通孔,其中,所述第二通孔至少部分地与所述线沟槽对准;以及
将所述导电材料填充到所述线沟槽和所述第二通孔中。
6.根据权利要求3所述的方法,其中,形成所述第二导电通孔的步骤包括:
蚀刻所述平坦化的第一绝缘层以形成第二通孔,其中,所述第二通孔至少部分地与所述第二开口对准并且暴露所述导电焊盘;以及
在所述第二通孔中填充导电材料。
7.根据权利要求3所述的方法,还包括在所述半导体衬底上方形成互连结构,其中,在所述导电焊盘下方延伸的所述层是设置在所述钝化层与所述互连结构之间的层或设置在所述互连结构中的层。
8.根据权利要求7所述的方法,其中,所述互连结构具有与所述第一导电过孔和所述导电焊盘间隔开的连接焊盘,并且所述方法还包括形成第三导电通孔,所述第三导电通孔延伸穿过所述第一绝缘层并连接至所述互连结构的所述连接焊盘。
9.一种制造半导体结构的方法,包括:
提供其上形成有电路的衬底,其中,所述衬底具有第一区域和第二区域;
在所述电路上方形成第一钝化层;
在所述第一钝化层上方形成导电焊盘,其中,所述导电焊盘电连接至所述电路;
在所述导电焊盘和所述第一钝化层上方形成第二钝化层,其中,所述第二钝化层在所述第一区域中具有第一开口并且在所述第二区域中具有第二开口,其中,所述第一开口暴露在所述导电焊盘下方延伸的层的上表面,并且所述第二开口暴露所述导电焊盘;
在所述第二钝化层上方形成第一绝缘层,其中,所述第一绝缘层填充所述第一开口和所述第二开口;
在所述第一区域中形成第一导电通孔,其中,所述第一导电通孔具有在所述第一开口中的至少一部分并且从所述第一绝缘层延伸至所述半导体衬底中;以及
在所述第二区域中形成第二导电通孔,其中,所述第二通孔具有在所述第二开口中的至少一部分并且连接至所述导电焊盘。
10.一种半导体器件,包括:
衬底,其上形成有电路;
第一钝化层,位于所述电路上方;
导电焊盘,位于所述第一钝化层上方并且电连接至所述电路;
第二钝化层,位于所述导电焊盘和所述第一钝化层上方,其中,所述第二钝化层具有第一开口和第二开口,所述第一开口暴露在所述导电焊盘下面延伸的层的上表面,所述第二开口暴露所述导电焊盘;
第一绝缘层,设置在所述第二钝化层上方并填充所述第一开口和所述第二开口;
衬底通孔,至少部分地与所述第二开口对准并延伸穿过所述第一绝缘层、所述第二钝化层、所述第一钝化层和所述衬底,其中,所述衬底通孔和所述第二钝化层的侧具有填充有所述第一绝缘层的间隙;以及
导电通孔,延伸穿过所述第一绝缘层并连接至所述导电焊盘。
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