CN102222629A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN102222629A
CN102222629A CN2010105303939A CN201010530393A CN102222629A CN 102222629 A CN102222629 A CN 102222629A CN 2010105303939 A CN2010105303939 A CN 2010105303939A CN 201010530393 A CN201010530393 A CN 201010530393A CN 102222629 A CN102222629 A CN 102222629A
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layer
lower metal
metal layer
projection lower
projection
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CN102222629B (zh
Inventor
林志伟
郑明达
吕文雄
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1603—Process or apparatus coating on selected surface areas
    • C23C18/1605—Process or apparatus coating on selected surface areas by masking
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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Abstract

本发明提供一种半导体装置及其制造方法，其中该方法是以无电铜电镀工艺于一光致抗蚀剂层的开口中的钛凸块下金属层上选择性形成铜凸块下金属层的制造方法。包括提供一基材；形成一第一凸块下金属(UBM)层于此基材上；形成一掩模层于此第一凸块下金属层上，其中此掩模层具有一开口，暴露一部分的此第一凸块下金属层；以及进行一无电电镀工艺以形成一第二凸块下金属层于此掩模层的此开口所暴露的此第一凸块下金属层上。在剥除此光致抗蚀剂层之后，无需于铜凸块下金属层上进行湿式蚀刻工艺，及因而使凸块下金属层结构不具有底切结构。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置的制造方法，且特别涉及一种具有无底切的凸块下金属层的凸块结构的制造方法。
背景技术
现今集成电路由数以百万计的有源装置(例如晶体管及电容)所制造。这些装置起初为互相隔离，但之后彼此内连接以形成功能性电路。内连线结构通常包含横向内连线(例如金属线)及垂直内连线(例如通孔及接触点)，对现今集成电路效能及密度的限制影响渐增。连接垫形成于内连线结构顶部，并暴露于其所对应的芯片表面外。电性连接通过连接垫形成，以连接芯片至封装基材或另一芯片。连接垫可用于导线连接或倒装芯片连接(flip-chipbonding)。在一般的凸块工艺中，为形成内连线结构于金属化层(metallizationlayers)上，接着形成凸块下金属层(under-bump metallurgy，UBM)，并设置焊球。
倒装芯片封装使用凸块来建立芯片的输入/输出垫与基材之间的电性接触，或芯片的输入/输出垫与封装体的导线架之间的电性接触。在结构上，凸块其实包含凸块本身及位于凸块及输入/输出垫之间的凸块下金属。凸块下金属通常包含粘着层、阻挡层及润湿层(wetting later)，依序排列于输入/输出垫上。凸块本身依其主要使用的材料可分类为焊锡凸块、金凸块、铜柱凸块(copper pillar bumps)及合金凸块(bumps with mixed metals)。近来，已有铜内连线柱(copper interconnection post)技术问世。电子元件通过铜柱与基材连接，取代焊锡凸块的使用。铜内连线柱技术达成了间距细化(finer pitch)，且使凸块桥接(bump bridging)的机率降至最低，减少电路的电容负载及使电子元件能在更高频率下操作。仍需使用焊料合金覆盖凸块结构并连接电子元件。
通常，湿蚀刻凸块下金属铜层(UBM Cu layer)时，会形成各向同性的蚀刻轮廓，对每个方向皆具有相同的蚀刻速率而导致受蚀刻的铜材料具有底切(undercutting)，造成不想要的线宽损失。由铜的湿蚀刻工艺所造成的底切，将导致诱导应力集中、导致凸块侧壁脱层或凸块破裂。虽然底切是蚀刻工艺固有的现象，然底切也限制了内连线的长期可靠度。底切会使焊锡凸块与芯片的连接垫之间的接合减弱，造成焊锡凸块的完整性下降，因而导致芯片过早失效。
发明内容
为克服现有技术中的缺陷，本发明提供一种半导体装置的制造方法，包括：提供一基材；形成一第一凸块下金属(UBM)层于此基材上；形成一掩模层于此第一凸块下金属层上，其中此掩模层具有一开口，暴露一部分的此第一凸块下金属层；以及进行一无电电镀工艺以形成一第二凸块下金属层于此掩模层的此开口所暴露的此第一凸块下金属层上。
本发明也提供一种半导体装置，包括：一半导体基材；一第一凸块下金属层，形成于此半导体基材上；一第二凸块下金属层，形成于此第一凸块下金属层上；以及一钯层，形成于此第一凸块下金属层及此第二凸块下金属层之间的界面。
本发明还提供一种半导体装置，包括：一半导体基材；一第一凸块下金属层，形成于此半导体基材上；以及一第二凸块下金属层，形成于此第一凸块下金属层上；一导电材料层，形成于此第二凸块下金属层上，其中此第二凸块下金属层为一含钯的铜合金层。
本发明中，在掩模层剥除之后，无需对第二凸块下金属层进行湿蚀刻工艺，因此最终的凸块下金属层具有无底切的轮廓。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合附图，进行详细说明。
附图说明
图1至图7显示为本发明一实施例的形成具有无底切的凸块下金属层的凸块结构的一系列剖面图。
图8至图10显示为本发明一实施例的形成具有无底切的凸块下金属层的铜柱凸块结构的一系列剖面图。
其中，附图标记说明如下：
10～基材                12～接触区
14～保护层              15～第一开口
16～聚合物层            17～第二开口
18～第一凸块下金属层    20～掩模层
21～第三开口            22～第二凸块下金属层
24～二氧化钛层          26～钯层
28～第二凸块下金属层    30～焊料层
32～凸块结构            34～铜层
36～第一盖层            38～第二盖层
40～盖层                42～凸块结构
具体实施方式
本发明提供一种使用于半导体装置的凸块工艺，此半导体装置具有焊锡凸块、铜柱(Cu posts)、护层后内连线(post passivation interconnect)及硅穿孔(TSV)形成于其上，并可应用于倒装芯片组装、晶片级芯片尺寸封装(WLCSP)、三维集成电路(3D-IC)堆迭及/或先进封装技术的领域。在以下的说明中，本发明接下来将会提供许多不同的实施例以实施本发明中不同的特征。各特定实施例中的组成及配置将会在以下作描述以简化本发明。这些为实施例并非用于限定本发明。例如，公知的结构及工艺在此将不再赘述，以避免对本发明造成不必要的混淆。本说明书中所述的“一实施例”意指为至少一实施例中包含的含特定的元件、结构或特征的一实施例。因此，于本说明书中各处出现“一实施例”的用语时，不需全部认为是相同的实施例。此外，特定的元件、结构或特征可在一或多个实施例中任意的结合。值得注意的是，以下所示的各图示仅用于举例说明，而非依比例绘示。
在此，图1至图7显示为依照本发明一实施例的无底切的凸块下金属层(UBM)的形成方法。
参见图1，在一实施例中，用于制造凸块的基材10可包含用于半导体集成电路制造的半导体基材，且集成电路可形成于其中或其上。半导体基材定义为包含半导体材料的任何结构，包含但不仅限于：硅块材、半导体晶片、绝缘层上覆硅(SOI)基材或硅锗基材。也可使用其他包含第III族、第IV族及第V族元素的材料。基材10可更包含多个隔离元件(未显示)，例如浅沟槽隔离(STI)元件或硅局部氧化(LOCOS)。隔离元件可定义或隔离各种微机电元件(未显示)。微机电元件可例如为形成于基材10中的晶体管(例如金属氧化物半导体场效应晶体管(MOSFET)、互补式金属氧化物半导体晶体管(CMOS)、双载子接面晶体管(BJT)、高电压晶体管、高频晶体管、p-沟道及/或n-沟道场效应晶体管(PFETs/NFETs)等)、电阻、二极管、电容、电感、熔丝或其他合适元件。可进行各种工艺以形成各种微机电元件，例如沉积、蚀刻、注入、光学光刻、退火或其他合适工艺。微机电元件彼此内连接以形成集成电路装置，例如逻辑装置、存储器装置(例如静态随机存存储器，SRAM)、射频装置、输入/输出装置、系统单芯片(system-on-chip，SoC)装置、前述的组合及/或其他合适的装置。
基材10更包含层间介电层及金属化结构于集成电路上。于金属化结构中的层间介电层，包含低介电常数介电材料、无掺杂硅玻璃(USG)、氮化硅、氮氧化硅或其他常用材料。低介电常数介电材料的介电常数可小于约3.9，或小于约2.8。金属化结构中的金属线可由铜或铜合金形成。本领域技术人员应可了解金属层的详细制造方法。接触区12为形成于最顶部的层间介电层中的最顶部的金属层，其为一部分的导电通路，并视需要可具有经平坦化工艺(化学机械研磨)处理的暴露表面。适于接触区12的材料可包含但不仅限于：铜、铝、铜铝合金(AlCu)、铜合金(copper alloys)或其他导电材料(mobile conductive material)。在一实施例中，接触区12为金属垫区12，其可在接合工艺中用以将各芯片中的集成电路连接至外部元件。
图1也示出了保护层14形成于基材10上，及将此保护层14图案化形成暴露一部分金属垫区12的第一开口15，以利于后续凸块形成。在一实施例中，保护层14由择自下列的非有机材料组成：非掺杂硅玻璃(USG)、氮化硅、氮氧化硅、氧化硅及前述的组合。在另一实施例中，保护层由聚合物层形成，例如环氧化物、苯环丁烯(BCB)、聚苯恶唑(polybenzoxazole，PBO)或其类似物，或也可使用其他相对较软及通常为有机物的介电材料。
图1更显示聚合物层16形成于保护层14上，且图案化聚合物层16以形成暴露一部分的金属垫区12的第二开口17。第二开口17可小于、等于或大于第一开口15。在一实施例中，第二开口17位于第一开口15中。聚合物层16，如其名，由聚合物形成，例如环氧化物、聚酰亚胺、苯环丁烯(BCB)、聚苯恶唑(PBO)。或者，聚合物层16也可由其他相对较软的介电材料形成。在一实施例中，聚合物层16为聚酰亚胺层。在另一实施例中，聚合物层16为聚苯恶唑(PBO)层。聚合物层16性质柔软，因此具有降低基材上的固有应力的功能。此外，聚合物层16可轻易地形成数十微米的厚度。
参见图2，其为形成第一凸块下金属(UBM)层18于图1的结构上。详细地说，第一凸块下金属层18形成于聚合物层16上及金属垫区12暴露的部分上，并内衬于第二开口17的侧壁及底部。第一凸块下金属层18也可称为扩散阻挡层，其可由钛、氮化钛、氮化钽、钽或其类似物形成，形成方法包含物理气相沉积(PVD)或溅镀。第一凸块下金属层18沉积的厚度为约500至
Figure BSA00000331254800051
较佳为约
Figure BSA00000331254800052
接着，如图3所示，形成掩模层20于第一凸块下金属层18上，并将此掩模层20图案化以形成一暴露一部分的第一凸块金属层18的第三开口21。第三开口21的直径大于或等于第二开口17的直径。掩模层20为经过涂布、硬化、去残胶(descum)及其类似步骤所形成的干膜(dry film)或光致抗蚀剂层，并接着进行光刻工艺及例如干蚀刻或湿蚀刻的蚀刻工艺。
参见图4，以无电沉积(electroless deposition)选择性形成第二凸块下金属层22于掩模层20的开口21中的第一凸块下金属层18上。在一实施例中，进行无电铜沉积以选择性电镀铜层于第一凸块下金属层18所暴露的部分上。第二凸块下金属层22的厚度为约1至10微米，例如约4至6微米，但亦可为其他较厚或较薄的厚度。
在无电铜电镀中，通常使用钯(Pd)作为无电铜电镀的活化基材(activatedbase material)。在经活化后，铜的无电沉积发生于催化表面上。通常，通过调整工艺条件(condition)，铜沉积的覆盖率达100％，且钯吸附的数量大幅增加。然而，为了确保均匀性，扩散阻挡层必需无任何金属氧化物，其有可能在无电铜电镀工艺之前形成。
图4A及图4显示为本发明一实施例，在第一凸块金属层18上进行无电铜沉积。一旦基材10转移至腔室以作沉积，即进行活化或初始化步骤。在某些实施例中，活化或初始步骤为将钯活化或初始化。使用于铜无电电镀工艺的预处理包含使用氢氟酸溶液自扩散阻挡层18移除二氧化钛层24，及沉积钯层26以活化扩散阻挡层18。接着，无电电镀于不均匀或粗糙的钯层26上的铜层28展现了高的电阻及方均根(RMS)粗糙度。因此，第二凸块下金属层22包含铜凸块下金属层28及钯层26。或者，第二凸块下金属层22意指为包含钯成分的铜层。可由电感式耦合等离子体(ICP)及/或扫瞄电子显微X-射线能谱分析法(SEM/EDX)侦测到钯成分，其位于第一凸块下金属层18及第二凸块金属层28之间的界面。
参见图5，接着形成焊料层30于掩模层20的开口21中的第二凸块下金属层22上。焊料层30可由Sn、SnAg、Sn-Pb、SnAgCu(铜重量百分率小于0.3％)、SnAgZn、SnBi-In、Sn-In、Sn-Au、SnPb、SnCu、SnZnIn或SnAgSb等。接着，如第6图所示，移除掩模层20，暴露出一部分的第一凸块下金属层18。在此实施例中，掩模层20为干膜，其可使用碱性溶液予以移除。如掩模层是由光致抗蚀剂形成，其可使用丙酮、N-甲基吡咯酮(n-methylpyrrolidone，NMP)、二甲基亚砜(dimethyl sulfoxide，DMSO)、胺基乙氧基乙醇(aminoethoxyl ethanol)或其类似物予以移除。
参见图7，依照第一凸块下金属层18的材料(metallurgy)，以传统湿式及/或干式蚀刻工艺伴随使用焊料层30为掩模，回蚀刻第一凸块下金属层18所暴露的部分。可使用标准的反应性离子蚀刻(RIE)来蚀刻第一凸块下金属层18。可视需要于焊料层30上进行焊料回流工艺。接着，切割基材10及将其封装于封装基材或另一芯片上，且焊球或铜凸块设置于封装基材或其他芯片上的垫上。
完成的凸块结构32包含第一凸块下金属层18、第二凸块下金属层22及焊球30，其中第二凸块下金属层为包含钯成分的铜层。相较于传统凸块工艺，本发明公开一种于掩模层20形成之后，以无电铜电镀工艺选择性形成第二凸块下金属层22的方法。无需在掩模层剥除后，对第二凸块下金属层22进行湿蚀刻工艺，因此最终的凸块下金属层具有无底切的轮廓。
图8至图10显示为依照本发明一实施例形成含无底切的凸块下金属层的铜柱凸块结构。与图1至图7相似或相同的部分的解释在此将作省略。
在形成如图4所示的第二凸块下金属层22之后，接着以具有焊料湿润性质(solder wettability)的导电材料将开口21部分填满。参见图8，铜层34较佳形成于开口21中，以与第二凸块下金属层22接触。铜层34较佳包含一膜层，其实质上包含纯元素铜、仅含不可避免的杂质的铜、及含少量例如钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或锆元素的铜合金。形成方法可包含溅镀、印刷、电镀、无电电镀及常用的化学气相沉积法。例如，进行化学电镀(electro-chemical plating，ECP)以形成铜层28。在一实施例中，铜层34的厚度大于30μm。在另一实施例中，铜层34的厚度大于40μm。例如，铜层的厚度为约40至50μm，或约40至70μm，虽然其厚度可更厚或更薄。此后，铜层34将称为铜柱34。
接着，形成盖层40于铜柱34的顶部表面上。盖层36可作为阻挡层以防止铜柱34中的铜扩散至例如焊料合金的接合材料中，此接合材料可用于接合10及外部元件。防止铜的扩散增加了封装的可靠度及接合强度。盖层34可包含镍、锡、铅锡合金(SnPb)、金、钯、铟、镍钯金合金(NiPdAu)、镍金合金(NiAu)、其他相似材料或前述的合金。盖层34可为单层或多层结构。如图8所示，在某些实施例中，盖层40包含第一盖层36及第二盖层38。第一盖层36为镍层，厚度为约1至5μm。第二盖层38为焊料层或金层。
接着，如图9所示，移除掩模层20，暴露一部分的第一凸块下金属层18。依照第一凸块下金属层18的材料(metallurgy)，以传统湿式及/或干式蚀刻工艺伴随使用铜柱34及掩模层40为掩模，回蚀刻第一凸块下金属层18所暴露的部分，如图10所示。可依照盖层40的材料，视需要进行焊料回流工艺。接着，切割基材10并封装至封装基材或另一芯片上，焊球或铜凸块设置封装基材或其他芯片上的垫上。
完成的凸块结构42包含第一凸块下金属层18、第二凸块下金属层22、铜柱34及盖层40，其中第二凸块下金属层22为包含钯成分的铜层。相较于传统凸块工艺，本发明提供一种于形成掩模层20之后，以无电铜沉积工艺选择性形成第二凸块下金属层22的方法。在掩模层20剥除之后，无需对第二凸块下金属层22进行湿蚀刻工艺，因此最终的凸块下金属层具有无底切的轮廓。
虽然本发明已以数个较佳实施例公开如上，然其并非用以限定本发明，任何所属技术领域中的普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的保护范围为准。

Claims (10)

1.一种半导体装置的制造方法，包括：
提供一基材；
形成一第一凸块下金属层于该基材上；
形成一掩模层于该第一凸块下金属层上，其中该掩模层具有一开口，暴露一部分的该第一凸块下金属层；以及
进行一无电电镀工艺以形成一第二凸块下金属层于该掩模层的该开口所暴露的该第一凸块下金属层上。
2.如权利要求1所述的半导体装置的制造方法，其中该第二凸块下金属层包含一铜层。
3.如权利要求1所述的半导体装置的制造方法，其中该无电电镀工艺形成一钯层于该第一凸块下金属层及该第二凸块下金属层之间的界面。
4.如权利要求1所述的半导体装置的制造方法，还包含形成一导电层于该掩模层的该开口中的该第二凸块下金属层上，其中该导电层为一焊料层或一铜柱。
5.如权利要求4所述的半导体装置的制造方法，还包含形成一盖层于该掩模层的该开口中的该导电层上，其中该盖层包含一镍层及一焊料层。
6.一种半导体装置，包括：
一半导体基材；
一第一凸块下金属层，形成于该半导体基材上；
一第二凸块下金属层，形成于该第一凸块下金属层上；以及
一钯层，形成于该第一凸块下金属层及该第二凸块下金属层之间的界面。
7.如权利要求6所述的半导体装置，其中该第一凸块下金属层包含一钛层，该第二凸块下金属层包含一铜层，该第二凸块下金属层具有一无底切的轮廓。
8.如权利要求6所述的半导体装置，还包含一导电层形成于该第二凸块下金属层上，其中该导电层为一焊料层或一铜柱。
9.如权利要求8所述的半导体装置，更包含：
一镍层形成于该导电层上，及
一焊料层或一金层，形成于该镍层上。
10.一种半导体装置，包括：
一半导体基材；
一第一凸块下金属层，形成于该半导体基材上；
一第二凸块下金属层，形成于该第一凸块下金属层上；以及
一导电材料层，形成于该第二凸块下金属层上，
其中该第二凸块下金属层为一含钯的铜合金层，其中该导电材料层包含一焊层或一铜柱。
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103107156A (zh) * 2011-11-11 2013-05-15 讯忆科技股份有限公司 晶圆焊垫的凸块结构及其制造方法
CN105399043A (zh) * 2014-09-04 2016-03-16 因文森斯公司 用于集成装置的释放化学物质保护
CN106129032A (zh) * 2016-08-14 2016-11-16 天津大学 用于超大规模集成电路芯片的柱状焊球重分布封装结构
CN106653719A (zh) * 2016-12-30 2017-05-10 通富微电子股份有限公司 一种圆片级封装结构与封装方法
CN107689356A (zh) * 2016-08-05 2018-02-13 台湾积体电路制造股份有限公司 具有减薄的衬底的封装件
CN110942983A (zh) * 2018-09-21 2020-03-31 台湾积体电路制造股份有限公司 接合的半导体器件及其形成方法
US11996383B2 (en) 2022-04-25 2024-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded semiconductor devices and methods of forming the same

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8922004B2 (en) * 2010-06-11 2014-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump structures having sidewall protection layers
US8259464B2 (en) * 2010-06-24 2012-09-04 Maxim Integrated Products, Inc. Wafer level package (WLP) device having bump assemblies including a barrier metal
US20150048499A1 (en) * 2013-08-16 2015-02-19 Macrotech Technology Inc. Fine-pitch pillar bump layout structure on chip
US10163828B2 (en) * 2013-11-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
US9159671B2 (en) 2013-11-19 2015-10-13 International Business Machines Corporation Copper wire and dielectric with air gaps
US9159683B2 (en) 2014-02-10 2015-10-13 GlobalFoundries, Inc. Methods for etching copper during the fabrication of integrated circuits
CN103871908A (zh) * 2014-03-28 2014-06-18 江阴长电先进封装有限公司 一种铜柱凸块的封装方法
WO2017143307A1 (en) * 2016-02-18 2017-08-24 University Of Southern California Modular piezoelectric sensor array with co-integrated electronics and beamforming channels
US10424552B2 (en) 2017-09-20 2019-09-24 Texas Instruments Incorporated Alloy diffusion barrier layer
KR20190043194A (ko) * 2017-10-17 2019-04-26 삼성디스플레이 주식회사 금속 배선 및 이를 포함하는 박막 트랜지스터
US11024593B2 (en) * 2018-09-28 2021-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Metal bumps and method forming same
KR102624169B1 (ko) 2019-06-24 2024-01-12 삼성전자주식회사 반도체 소자 및 이를 포함하는 반도체 패키지
US10950631B1 (en) * 2019-09-24 2021-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor-on-insulator wafer having a composite insulator layer

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1679154A (zh) * 2002-05-16 2005-10-05 新加坡国立大学 晶片级无电镀铜法和凸块制备方法,以及用于半导体晶片和微芯片的渡液
US20060094224A1 (en) * 2004-11-03 2006-05-04 Advanced Semiconductor Engineering, Inc. Bumping process and structure thereof
US7262505B2 (en) * 2000-01-18 2007-08-28 Micron Technology, Inc. Selective electroless-plated copper metallization
US20090079094A1 (en) * 2007-09-21 2009-03-26 Stats Chippac, Ltd. Solder Bump with Inner Core Pillar in Semiconductor Package

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100804392B1 (ko) * 2005-12-02 2008-02-15 주식회사 네패스 반도체 패키지 및 그 제조 방법
US20070238283A1 (en) * 2006-04-05 2007-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Novel under-bump metallization for bond pad soldering
US7456090B2 (en) 2006-12-29 2008-11-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method to reduce UBM undercut
US20090108443A1 (en) * 2007-10-30 2009-04-30 Monolithic Power Systems, Inc. Flip-Chip Interconnect Structure
JP2009164442A (ja) * 2008-01-09 2009-07-23 Nec Electronics Corp 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7262505B2 (en) * 2000-01-18 2007-08-28 Micron Technology, Inc. Selective electroless-plated copper metallization
CN1679154A (zh) * 2002-05-16 2005-10-05 新加坡国立大学 晶片级无电镀铜法和凸块制备方法,以及用于半导体晶片和微芯片的渡液
US20060094224A1 (en) * 2004-11-03 2006-05-04 Advanced Semiconductor Engineering, Inc. Bumping process and structure thereof
US20090079094A1 (en) * 2007-09-21 2009-03-26 Stats Chippac, Ltd. Solder Bump with Inner Core Pillar in Semiconductor Package

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103107156B (zh) * 2011-11-11 2016-02-10 讯忆科技股份有限公司 晶圆焊垫的凸块结构及其制造方法
CN103107156A (zh) * 2011-11-11 2013-05-15 讯忆科技股份有限公司 晶圆焊垫的凸块结构及其制造方法
US10071906B2 (en) 2014-09-04 2018-09-11 Invensense, Inc. Release chemical protection for integrated complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical (MEMS) devices
CN105399043A (zh) * 2014-09-04 2016-03-16 因文森斯公司 用于集成装置的释放化学物质保护
US10683205B2 (en) 2014-09-04 2020-06-16 Invensense, Inc. Release chemical protection for integrated complementary metal-oxide-semiconductor (CMOS) and micro-electro-mechanical (MEMS) devices
US10679968B2 (en) 2016-08-05 2020-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Package with thinned substrate
CN107689356A (zh) * 2016-08-05 2018-02-13 台湾积体电路制造股份有限公司 具有减薄的衬底的封装件
CN107689356B (zh) * 2016-08-05 2021-04-27 台湾积体电路制造股份有限公司 具有减薄的衬底的封装件
US11094671B2 (en) 2016-08-05 2021-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package with thinned substrate
CN106129032A (zh) * 2016-08-14 2016-11-16 天津大学 用于超大规模集成电路芯片的柱状焊球重分布封装结构
CN106653719B (zh) * 2016-12-30 2020-01-17 通富微电子股份有限公司 一种圆片级封装结构与封装方法
CN106653719A (zh) * 2016-12-30 2017-05-10 通富微电子股份有限公司 一种圆片级封装结构与封装方法
CN110942983A (zh) * 2018-09-21 2020-03-31 台湾积体电路制造股份有限公司 接合的半导体器件及其形成方法
US11315900B2 (en) 2018-09-21 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded semiconductor devices and methods of forming the same
US11996383B2 (en) 2022-04-25 2024-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded semiconductor devices and methods of forming the same

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