CN1645565A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN1645565A CN1645565A CNA2005100045319A CN200510004531A CN1645565A CN 1645565 A CN1645565 A CN 1645565A CN A2005100045319 A CNA2005100045319 A CN A2005100045319A CN 200510004531 A CN200510004531 A CN 200510004531A CN 1645565 A CN1645565 A CN 1645565A
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Abstract
本发明提供半导体装置及其制造方法,在覆盖熔丝而将SiON膜、SiN膜、SiO2膜以该顺序形成后,通过蚀刻至作为蚀刻阻止膜的SiN膜,在熔丝上均一地形成所需的膜厚的SiON膜。另外,通过设置被嵌入熔丝下部的绝缘膜并且包围熔丝的外周部而形成的保护环,就可以防止水分从外部穿过熔丝切断部而浸入的情况。利用本发明可以防止在与电路连接的熔丝上的绝缘膜厚在晶片面内不均一的情况下,因激光照射强度不足而切断不充分,或因激光过度照射而产生切断至相邻的熔丝部分的问题。另外,还可以在熔丝切断后,防止水分从外部穿过切断部而浸入,对配置于下层部的膜质造成不良影响的问题。
Description
技术领域
本发明涉及具有存储或逻辑等电路元件的半导体装置及其制造方法。
背景技术
一直以来,半导体装置当中的DRAM等存储器中,有为了使取代不良位的冗余位动作而具有熔丝的存储器(例如参照非专利文献1),在晶片加工制造工序后确认半导体装置的动作,如果为不良位,则为了将该不良位置换为冗余位,向与不良位连接的熔丝照射激光而进行切割。
作为半导体装置中的熔丝的使用方法,除了所述存储器的情况以外,还有如下的方法。如果在熔丝是否熔断的状态下记录「1」或「0」的信息,则例如通过对每个半导体芯片设置128个熔丝,就可以将128位的信息记录在各半导体芯片中。所记录的信息如果是对于每个半导体芯片不同的标识符,则通过读出记录在熔丝中的信息,就可以区别各半导体芯片。
另外,作为其他的使用方法,有设置用于半导体装置内的电压调整的熔丝,在晶片加工制造工序后测定内部的电压,按照达到所需的电压的方式切断熔丝的方法。
对所述非专利文献1的情况的半导体装置的构成进行说明。
图5是表示以往的半导体装置的一个构成例的剖面示意图。
该半导体装置在半导体基板100上形成晶体管、电容器及电阻等半导体元件(未图示)及基底绝缘膜101,如图5所示,在作为配线嵌入用绝缘膜而形成的SiO2膜102上形成铜(Cu)配线120,在Cu配线120上形成有Al(铝)配线124。cu配线120和Al配线124的连接部分以外的层间绝缘膜为SiO2膜210单层。另外,熔丝122被SiO2膜210覆盖。SiO2膜2l0的形成膜厚约为1μm。在SiO2膜210上形成SiON膜212,其膜厚约为1μm。
熔丝122借助未图示的配线与电路连接。另外,熔丝122由与Cu配线120的Cu腐蚀防止膜123相同的层形成,是依次形成了Ti膜和TiN膜的构造(以下表记为「TiN/Ti」构造)的叠层导电性膜。
而且,图5中,Al配线124发挥焊盘部126的作用,而形成于与Al配线124相同层上的其他的Al配线(未图示)起到用于将元件间电连接的作用。
在形成图5所示的用于焊接的开口时,通过控制SiO2膜210的蚀刻时间而使熔丝122上的SiO2膜210残留特定的膜厚。
[非专利文献]K.Arndt et al.,Reliability of Laser Activated Metal Fusesin DRAMs,1999 IEEE/CPMT Inte’l Electronics Manufacturing TechnologySymposium,p.389-394
如上所述,当通过进行特定的蚀刻时间量的蚀刻,使熔丝上的绝缘膜残留特定的膜厚,则由于蚀刻装置的小室内气氛使蚀刻速度发生改变,因此即使用相同的蚀刻时间进行处理,熔丝上的绝缘膜的膜厚在晶片间及晶片面内也会产生很大的不均。即使激光的照点直径和照射能量等照射条件相同,当熔丝上的绝缘膜的膜厚与设定值相比过薄时,则照射到熔丝上的能量就会过强,不仅是要切断的熔丝,而且连相邻的熔丝也会被切断。相反,当熔丝上的绝缘膜的膜厚与设定值相比过厚时,则照射到熔丝上的激光的能量就会不足,因而就会产生无法切断熔丝的问题。
由此,在切断熔丝时,即使按照使激光的照射条件每次相同的方式来控制,在熔丝上的绝缘膜的膜厚中有不均的情况下,则容易产生无法切断熔丝的「切断失败」或切割至相邻的熔丝的「误切断」,从而有可能导致材料成品率的降低。
另外,在以往例中,由于熔丝上的绝缘膜仅为SiO2膜,因此水分就会经过设于熔丝上的开口部而从外部浸入。由于该水分,就会产生铜配线的特性变化或腐蚀。当作为比氧化硅膜介电常数更低的绝缘膜的Low-k膜位于熔丝的下层时,则当水分浸入Low-k膜时,Low-k膜的配线间电容就会上升,从而有可能导致半导体装置的长期可靠性变差。
发明内容
本发明是为了解决如上所述的以往的技术所具有的问题而完成的方案,其目的在于,提供熔丝上的绝缘膜的膜厚均一并且防止了水分的侵入的半导体装置及其制造方法。
用于达成所述目的的本发明的半导体装置是具有形成于半导体基板上的电路、与电路连接的熔丝的半导体装置,具有覆盖熔丝而被形成的含有氮的氧化硅膜。
另外,电路也可以含有铜配线。本发明中,由于熔丝上的绝缘膜为含有氮的氧化硅膜,因此就可以防止来自熔丝上绝缘膜的水分的浸入,从而可以抑制铜配线的腐蚀。
另外,本发明的其他的半导体装置的特征是,具有形成于熔丝的下部的基底绝缘膜、被嵌入基底绝缘膜并且包围熔丝的外周部而被形成的保护环。本发明中,由于在熔丝的下层设有保护环,因此即使熔丝被切断,也会抑制从熔丝切断位置侵入的水分的扩散。
另外,保护环也可以形成于与铜配线相同的平面上。
另外,包含氮的氧化硅膜也可以含有SiON。本发明中,由于含有氮的氧化硅膜为SiON膜,因此与氧化硅膜相比,更可以防止水分的浸入。
本发明的半导体装置的制造方法的特征是,具有在半导体基板上形成熔丝的工序、覆盖熔丝而形成含有氮的氧化硅膜的工序、在氧化硅膜上形成蚀刻阻止膜的工序、在蚀刻阻止膜上形成绝缘膜的工序、将熔丝上的绝缘膜除去的工序、将熔丝上的蚀刻阻止膜除去的工序。本发明中,由于有蚀刻阻止膜,因此在进行氧化硅膜蚀刻时,蚀刻就会在蚀刻阻止膜处停止。其后,当进行蚀刻阻止膜的蚀刻时,含有氮的氧化硅膜的膜厚的不均与以往相比就会减少。
另外,氧化硅膜也可以含有SiON。
另外,含有氮的氧化硅膜的膜厚优选150~300nm,更优选180~250nm。
另外,本发明的另外的半导体装置的制造方法的特征是,具有在半导体基板上形成基底绝缘膜的工序、在基底绝缘膜上形成铜配线的工序、在基底绝缘膜上形成熔丝的工序、覆盖熔丝和铜配线而形成含有氮的第1氧化硅膜的工序、在第1氧化硅膜上形成蚀刻阻止膜的工序、在蚀刻阻止膜上形成绝缘膜的工序、将形成于铜配线的一部分之上的第1氧化硅膜和蚀刻阻止膜和绝缘膜除去的工序、形成与铜配线连接的焊接盘的工序、按照覆盖焊接盘的方式形成含有氮的第2氧化硅膜的工序、在第2氧化硅膜上形成有机膜的工序、将形成于焊接盘的一部分之上的有机膜和所述第2氧化硅膜和绝缘膜除去的同时,将形成于所述熔丝的一部分之上的所述有机膜和所述第2氧化硅膜和所述绝缘膜除去的工序、将形成于所述熔丝的一部分之上的所述蚀刻阻止膜除去的工序。本发明中,由于在蚀刻绝缘膜时,蚀刻在蚀刻阻止膜处停止,因此蚀刻阻止膜的蚀刻后的第1氧化硅膜的膜厚的不均与以往相比就会减少。另外,不需要对盘上和熔丝上的膜分别进行蚀刻,有机膜的光刻仅1次即可。
另外,第1氧化硅膜及第2氧化硅膜也可以含有SiON。
另外,蚀刻阻止膜也可以含有氮化硅膜或SiCN膜。本发明中,由于蚀刻阻止膜至少含有氮化硅膜及SiCN膜的任意一个,因此在对氧化硅膜进行蚀刻的条件下,对蚀刻阻止膜进行蚀刻的速度与氧化硅膜相比就会变慢,从而就可以检测出氧化硅膜的蚀刻停止。
另外,蚀刻阻止膜的膜厚优选30~100nm。
本发明中,由于作为熔丝上绝缘膜有含有氮的氧化硅膜,因此就可以防止来自熔丝上绝缘膜的水分浸入,在作为熔丝的基底绝缘膜使用Low-k膜等容易受到水分的影响的材料的情况下,就可以防止Low-k膜等的来自水分的影响。
另外,本发明中,在进行用于使熔丝上的含有氮的氧化硅膜残留所需的厚度的蚀刻时,最终的被蚀刻膜的膜厚就会达到蚀刻阻止膜的膜厚的30~100nm,与以往的情况相比更薄。由此,即使因过蚀刻而削掉了含有氮的氧化硅膜,由蚀刻造成的膜厚不均与以往相比也会更小,含有氮的氧化硅膜的熔丝上残膜与以往相比,膜厚不均也会更小。
本发明的半导体装置的制造方法通过在熔丝上绝缘膜上设置用于停止蚀刻的蚀刻阻止膜,使得熔丝上的膜厚控制更加容易,因此就可以使熔丝上的SiON膜残留所需的膜厚。由此,当利用激光从绝缘膜上切断熔丝时,就会形成熔丝上绝缘膜的晶片面内及晶片间的膜厚不均减少了的构造,从而可以大幅度减少熔丝的切断失败或误切断的比例,进而可以使半导体装置的材料成品率提高。
另外,本发明的半导体装置由于SiON膜完全覆盖包括设于熔丝上的激光照射用的开口部、以及熔丝上,因此就可以抑制来自外部的水分的浸入。由此,就可以防止铜配线的特性变化或腐蚀。另外,即使将水分一浸入配线间电容就会上升的Low-k膜用于层间绝缘膜,也会防止水分向Low-k膜的浸入,与以往的制造方法相比,配线的可靠性大大提高,且半导体装置的可靠性也提高。
附图说明
图1是表示实施方式1的半导体装置的一个构成例的剖面示意图。
图2是表示实施方式1的半导体装置的制造方法的剖面示意图。
图3是表示实施方式1的半导体装置的制造方法的剖面示意图。
图4是表示实施方式2的半导体装置第一个构成例的图。
图5是表示以往的半导体装置的一个构成例的剖面示意图。
其中,100 半导体基板,101 基底绝缘膜,106、112、212 SiON膜,108 SiN膜,102、110、210 SiO2膜,114 光致抗蚀剂,120 Cu配线,121 Cu膜,122 熔丝,123 Cu腐蚀防止膜,124 Al配线,128、132 TiN膜,130 Al-Cu膜,141a 焊盘用开口图案,141b 熔丝用开口图案,142 熔丝用开口部
具体实施方式
本发明的半导体装置的特征是,具有覆盖熔丝地设置了防止水分的侵入的绝缘膜的构成。另外,本发明的半导体装置的制造方法的特征是,具有在覆盖熔丝而形成的防止水分的侵入的绝缘膜上形成包括用于蚀刻停止的蚀刻阻止膜(以下简称为阻止膜)的绝缘膜的工序。
对本发明的半导体装置进行说明。
图1是表示本发明的半导体装置的一个构成例的剖面示意图。而且,虽然与以往相同,在半导体基板100之上形成有半导体元件,但是将图示省略。
如图1所示,本发明的半导体装置中,在熔丝122之上形成有SiON膜106。另外,作为成为最上层配线的Al配线124和成为其下层的配线的Cu配线120之间的连接部以外的层间绝缘膜,形成有SiO2/SiN/SiON构造的叠层绝缘膜。熔丝122由与Cu配线120的Cu腐蚀防止膜123相同材质的膜形成,是TiN/Ti构造的叠层导电性膜。熔丝122上的SiON膜106的膜厚优选150~300nm,更优选180~250nm。
SiON膜106为含有氮的氧化硅膜,是与SiO2膜相比水分更难浸入的膜。由此,SiON膜106不仅防止水分从熔丝用开口部142向熔丝122侵入,而且还防止水分向Cu配线120、SiO2膜102以及未图示的下层的配线及绝缘膜浸入。从而,如果超过所述的范围而增加膜厚,则利用激光照射进行的熔丝的切断就会变得困难,另一方面,当使之变薄时,则抑制水分的浸入的效果就会降低。
熔丝122借助未图示的配线而与包括Cu配线120的电路连接。
下面,对所述的构成的半导体装置的制造方法进行说明。图2及图3是表示半导体装置的制造方法的剖面示意图。
在半导体基板100上,形成了未图示的半导体元件和多个配线层之后,如图2(a)所示,形成基底绝缘膜101。然后,在形成了SiO2膜102后,利用光刻工序及蚀刻工序,在SiO2膜102上形成配线用的槽。在所形成的槽的底部和侧壁上形成屏蔽金属(未图示),继而,用电解电镀法在槽内嵌入Cu。在利用热处理使Cu晶粒长大后,利用CMP(Chemical andMechanical Polishing)处理,将SiO2膜102上的Cu除去而形成Cu膜121。Cu膜121不限于纯Cu,包括以Cu为主成分而含有其他的元素的金属膜的情况。
然后,在形成了膜厚50nm的Ti膜和膜厚150nm的TiN膜的叠层导电性膜后,利用光刻工序及蚀刻工序形成用叠层导电性膜覆盖Cu膜121的上面的Cu腐蚀防止膜123和熔丝122。这样,就可以形成包括Cu膜121及Cu腐蚀防止膜123的Cu配线120。而且,该Cu腐蚀防止膜123还起到增强Cu配线121的强度的作用。
其后,利用等离子体CVD法形成膜厚200~300nm的SiON膜106,利用CVD法依次形成膜厚30~100nm的SiN膜108和膜厚600~700nm的SiO2膜110。SiN膜108成为用于对SiO2膜110的蚀刻停止的阻止膜。
如图2(b)所示,在SiO2膜110上形成了光致抗蚀剂114后,进行曝光及显影处理,在光致抗蚀剂114的Cu配线120之上形成开口图案115。然后,通过从光致抗蚀剂114之上进行各异向性蚀刻,将开口图案115的SiO2膜110、SiN膜108及SiON膜106除去,而露出Cu腐蚀防止膜123。
在除去了光致抗蚀剂114后,依次形成作为下层屏蔽金属膜的膜厚25nm的TiN膜128、膜厚1600nm的Al-Cu膜130和作为上层屏蔽金属膜的膜厚25nm的TiN膜132。然后,利用光刻工序和蚀刻工序形成Al配线124(图2(c))。
其后,如图3(a)所示,利用等离子体CVD法形成膜厚1000nm的SiON膜112。
然后,在涂布了成为保护膜的聚酰亚胺膜140后,利用光刻工序,在聚酰亚胺膜140上,在焊接盘之上形成焊盘用开口图案141a且在熔丝122之上形成熔丝用开口图案141b。
其后,利用异向性蚀刻,将焊盘用开口图案141a和熔丝用开口图案141b的SiON膜112除去。这样,在焊盘用开口图案141a上,Al配线124的TiN膜132的上面就会露出。然后,在对氧化硅膜进行蚀刻的条件下进行异向性蚀刻,除去熔丝用开口图案141b的SiO2膜110。在进行该SiO2膜110的蚀刻时,由于SiO2膜110的下层为SiN膜108,因此在对氧化硅膜进行蚀刻的条件下,蚀刻氮化硅膜的速度与氧化硅膜相比更慢,就可以充分地检测出SiO2膜110的蚀刻结束的时刻。
其后,在对氮化硅膜进行蚀刻的条件下,进行异向性蚀刻,将熔丝用开口图案141b的SiN膜108除去。此时,即使为了将SiN膜108完全地除去,而施加100%的过蚀刻,SiON膜106也仅削除了大约100nm,因此在熔丝122上残留膜厚大约200nm的SiON膜。
而且,焊盘部126中,在对熔丝用开口图案141b的SiO2膜110及SiN膜108进行蚀刻时,由于TiN膜132暴露在蚀刻下,因此TiN膜132就被除去,而Al-Cu膜130露出时,则蚀刻基本上就会停止。其理由是,对于作为蚀刻速度的比的蚀刻选择比(以下简称为选择比),相对于绝缘膜和TiN膜的选择比,绝缘膜和铝的选择比的一方更大,在对绝缘膜进行蚀刻的条件下,铝难以被削除。这样,由于在焊盘用开口图案141a中,形成露出了Al-Cu膜130的焊盘部126,因此就可以获得利用引线接合法的与外部的连接配线的良好的连接特性。
而且,所述SiON膜106为本发明的含有氮的第1氧化硅膜,SiON膜112为本发明的含有氮的第2氧化硅膜。
本发明中,如上所述,在对熔丝122上的绝缘膜进行蚀刻时,在削除SiO2膜110时一次地在SiN膜108处使蚀刻停止,其后对SiN膜108进行蚀刻,则可以对SiON膜106的膜厚很好地控制并形成。由此,就可以减少熔丝122上的绝缘膜的晶片内及晶片间不均。将该情况与以往的情况比较而进行说明。
当像以往那样,在熔丝上使SiON膜和SiO2膜对齐而形成数μm,则用时间控制对绝缘膜进行蚀刻时,由于晶片面内的蚀刻速率的不均和绝缘膜形成时的不均,就会导致熔丝上的膜厚的不均变得非常大。例如,如果相对于被蚀刻膜所削掉的膜的膜厚不均为10%,则被蚀刻膜的膜厚为2.0μm时,所削掉的膜的膜厚不均就达到0.2μm。与之相对,被蚀刻膜的膜厚为0.2μm时,则所削掉的膜的膜厚不均就变为0.02μm。所以,一次地用SiN膜使蚀刻停止,其后,通过对SiN膜进行蚀刻,就可以大幅度地降低熔丝上的绝缘膜的膜厚不均。
当熔丝上的绝缘膜为以往的构造,而要使熔丝上的绝缘膜达到所需的膜厚,则焊盘部上绝缘膜的蚀刻时间的最佳值的一方与熔丝上绝缘膜的蚀刻时间的最佳值相比更长,因此需要将蚀刻分2次进行。
与之相反,本发明中,如上所述,由于在聚酰亚胺膜140上,用1次的光刻工序形成焊盘用开口图案141a和熔丝用开口图案141b,其后的蚀刻工序中,一次地用SiN膜使熔丝上的绝缘膜的蚀刻停止,因此相对于焊盘部126的开口,就可以确保足够的蚀刻时间,并且可以将熔丝上的SiON膜106制成所需的膜厚。
另外,与SiON膜106相比,SiO2膜210(参照以往例的图5)抑制水分的浸入的能力较小。以往的制造方法中,由于在熔丝用开口部处SiO2膜210露出,因此水分就能够从该处浸入。本发明中,由于熔丝之上被SiON膜106覆盖,因此就可以抑制水分的浸入。
本发明的半导体装置的制造方法由于通过作为熔丝上绝缘膜而形成SiO2/SiN/SiON构造的叠层绝缘膜,将SiN膜作为用于停止蚀刻的阻止膜使用,使熔丝上的膜厚控制更加容易,因此就可以使熔丝上的SiON膜残留所需的膜厚。由此,就会形成当利用激光从绝缘膜之上切断熔丝时熔丝上的绝缘膜的晶片面内及晶片间的膜厚不均减少的构造,从而熔丝的切断失败或误切断的比例大幅度降低。所以,半导体装置的材料成品率提高。
另外,本发明的半导体装置由于在熔丝上完全覆盖SiON膜,因此就可以抑制来自外部的水分的浸入。由此,就可以防止铜配线的特性变化或腐蚀。另外,将水分一浸入配线间电容就会上升的Low-k膜用于层间绝缘膜,也可以防止水分向Low-k膜中的浸入,且与以往那样的制造方法相比,配线的可靠性大大提高。所以,半导体装置的可靠性提高。
下面,介绍实施方式2。
本实施方式是在实施方式1中所示的构成中,为了防止熔丝切断后的水分的侵入,而在熔丝122形成部位的下层设置了保护环。
对本实施方式的构成进行说明。而且,对于与实施方式1相同的构成,将使用相同的符号,省略其详细的说明。
图4(a)是表示本实施方式的一个构成例的剖面示意图。图4(b)是表示Cu配线120和熔丝122的层的图案的俯视示意图,线段X-X’的部分的剖面图相当于图4(a)。
如图4(a)及(b)所示,在熔丝122的下层的SiO2膜102上,由Cu配线形成包围熔丝122的俯视图案区域的保护环150。即,保护环150被嵌入作为熔丝的基底绝缘膜的SiO2膜102中,并且环绕熔丝122的外周部。此外,本实施方式中,表示形成了多个熔丝122的例子。当向熔丝122照射激光而将熔丝122切断时,由于熔丝122上的SiON膜106及熔丝122的一部分消失,因此水分就有可能穿过所述消失了的部分而浸入SiO2膜102。即使在侵入了SiO2膜102的水分在熔丝下部将要沿横向扩散的情况下,保护环150也会防止水分的向横向的扩散。而且,保护环150由于被与其他的配线电绝缘,因此即使水分浸入保护环150自身中也不会有问题。
下面,对图4(a)、(b)所示的构造的保护环的作用进行说明。
例如,在半导体芯片上设置以3~4μm的间距排列的多个熔丝122。当向其中的1条熔丝122照射照点直径为2.7~3.3μm的激光而切断时,熔丝122上的SiON膜106及熔丝122的一部分就会飞散。虽然水分会从切断了的熔丝122上的SiON膜106及熔丝122的一部分飞散了的部位浸入SiO2膜102,但是利用保护环150可以保护水分向图中的横向的扩散,从而可以抑制水分向Cu配线120的浸入。
对于所述构成的半导体装置的制造方法,只要将保护环150用与Cu配线120相同的工序形成即可,加工的工序数不会增加。
本实施方式中,即使当熔丝被切断时,也可以防止水分从图1所示的熔丝用开口部142向半导体装置内部的浸入。
而且,在所述实施方式1及实施方式2中,虽然熔丝122被形成于与Cu配线120的Cu腐蚀防止膜123相同的层上,但是并不限定于与Cu腐蚀防止膜123相同的层,也可以形成于Cu腐蚀防止膜123的上层。这是因为,从熔丝用开口部142侵入的水分就可以从SiO2膜102向任意一个方向扩散。
另外,虽然将熔丝122设成了TiN/Ti构造的叠层导电性膜,但是也可以是TiN膜单层。
另外,虽然将用于停止对氧化硅膜的蚀刻的阻止膜设为SiN膜,但是也可以是SiCN膜。这是因为,当在对氧化硅膜蚀刻的条件下进行蚀刻时,SiCN膜也与SiN膜相同,其蚀刻速度较慢。
另外,SiON膜106并不限定于氧和氮的含有比1∶1。
另外,虽然将最上层配线以Al配线124设为单层,但是也可以是TiN单层构造、TiN/Ti叠层构造、TiN/Cu叠层构造及TiN/Ti/Cu叠层构造当中的任意一种。
另外,虽然作为用于实现与外部的连接的盘,以焊接盘126的情况进行了说明,但是并不限定于用于引线接合的盘。
另外,虽然出示了使用铜配线作为配线的例子,但是也可以使用铜配线以外的配线,此时,在配线中使用可因水分而受到腐蚀等的影响的材料的情况下,也能通过采用本发明而防止配线被水分腐蚀。另外,在配线不会因水分受到腐蚀的情况下,当将Low-k膜等容易受到水分的影响的材料作为熔丝的基底绝缘膜使用时,通过采用本发明,也可以防止Low-k膜等受到水分的影响。
Claims (19)
1.一种半导体装置,是具有形成于半导体基板上的电路、与所述电路连接的熔丝的半导体装置,其特征是,具有以覆盖所述熔丝的方式形成的含有氮的氧化硅膜。
2.根据权利要求1所述的半导体装置,其特征是,所述电路含有铜配线。
3.根据权利要求1所述的半导体装置,其特征是,具有形成于所述熔丝的下部的基底绝缘膜、被嵌入所述基底绝缘膜并且包围所述熔丝的外周部而形成的保护环。
4.根据权利要求2所述的半导体装置,其特征是,具有形成于所述熔丝的下部的基底绝缘膜、被嵌入所述基底绝缘膜并且包围所述熔丝的外周部而形成的保护环。
5.根据权利要求4所述的半导体装置,其特征是,所述保护环被形成于与所述铜配线相同的平面上。
6.根据权利要求1~5中任意一项所述的半导体装置,其特征是,所述含有氮的氧化硅膜含有SiON。
7.根据权利要求1~5中任意一项所述的半导体装置,其特征是,所述含有氮的氧化硅膜的膜厚为150~300nm。
8.根据权利要求1~5中任意一项所述的半导体装置,其特征是,所述含有氮的氧化硅膜的膜厚为180~250nm。
9.一种半导体装置的制造方法,其特征是,包括:在半导体基板上形成熔丝的工序、覆盖所述熔丝而形成含有氮的氧化硅膜的工序、在所述氧化硅膜上形成蚀刻阻止膜的工序、在所述蚀刻阻止膜上形成绝缘膜的工序、将所述熔丝上的所述绝缘膜除去的工序、将所述熔丝上的所述蚀刻阻止膜除去的工序。
10.根据权利要求9所述的半导体装置的制造方法,其特征是,所述含有氮的氧化硅膜含有SiON。
11.一种半导体装置的制造方法,其特征是,包括:
在半导体基板上形成基底绝缘膜的工序、在所述基底绝缘膜上形成铜配线的工序、
在所述基底绝缘膜上形成熔丝的工序、
覆盖所述熔丝和所述铜配线而形成含有氮的第1氧化硅膜的工序、在所述第1氧化硅膜上形成蚀刻阻止膜的工序、
在所述蚀刻阻止膜上形成绝缘膜的工序、将形成于所述铜配线的一部分之上的所述第1氧化硅膜和所述蚀刻阻止膜和所述绝缘膜除去的工序、
形成与所述铜配线连接的焊接盘的工序、
按照覆盖所述焊接盘的方式形成含有氮的第2氧化硅膜的工序、
在所述第2氧化硅膜上形成有机膜的工序、
将形成于所述焊接盘的一部分之上的所述有机膜和所述第2氧化硅膜和所述绝缘膜除去的同时将形成于所述熔丝的一部分之上的所述有机膜和所述第2氧化硅膜和所述绝缘膜除去的工序、
将形成于所述熔丝的一部分之上的所述蚀刻阻止膜除去的工序。
12.根据权利要求11所述的半导体装置的制造方法,其特征是,所述第1氧化硅膜含有SiON。
13.根据权利要求11或12所述的半导体装置的制造方法,其特征是,所述第2氧化硅膜含有SiON。
14.根据权利要求9~13中任意一项所述的半导体装置的制造方法,其特征是,所述蚀刻阻止膜含有氮化硅膜。
15.根据权利要求9~13中任意一项所述的半导体装置的制造方法,其特征是,所述蚀刻阻止膜含有SiCN膜。
16.根据权利要求9~15中任意一项所述的半导体装置的制造方法,其特征是,所述蚀刻阻止膜的膜厚为30~100nm。
17.根据权利要求1所述的半导体装置,其特征是:
还具备:配置于含有所述氮的氧化硅化膜上的蚀刻阻止膜、配置于所述蚀刻阻止膜上的绝缘膜,
而且,所述蚀刻阻止膜和所述绝缘膜,将含有所述氮的氧化硅膜的露出区域具备于所述熔丝的一部分的上部。
18.根据权利要求17所述的半导体装置,其特征是:
所述蚀刻阻止膜包含SiN膜。
19.根据权利要求17所述的半导体装置,其特征是:
所述蚀刻阻止膜包含SiCN膜。
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2005
- 2005-01-18 CN CN2008101449544A patent/CN101339925B/zh not_active Expired - Fee Related
- 2005-01-18 CN CNB2005100045319A patent/CN100444314C/zh not_active Expired - Fee Related
- 2005-01-19 US US11/037,166 patent/US7323760B2/en not_active Expired - Fee Related
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2007
- 2007-11-30 US US11/947,807 patent/US7579266B2/en not_active Expired - Fee Related
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101771021B (zh) * | 2008-12-29 | 2013-07-24 | 联华电子股份有限公司 | 电熔丝结构及其制作方法 |
CN103094248A (zh) * | 2011-11-04 | 2013-05-08 | 上海华虹Nec电子有限公司 | 金属熔丝结构及其制造方法 |
CN103094248B (zh) * | 2011-11-04 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | 金属熔丝结构及其制造方法 |
CN108257934A (zh) * | 2016-12-29 | 2018-07-06 | 联华电子股份有限公司 | 焊垫开口及熔丝焊接口的制作方法与焊垫开口结构 |
CN108257934B (zh) * | 2016-12-29 | 2021-02-19 | 联华电子股份有限公司 | 焊垫开口及熔丝焊接口的制作方法与焊垫开口结构 |
CN108511414A (zh) * | 2017-02-24 | 2018-09-07 | 艾普凌科有限公司 | 半导体装置和半导体装置的制造方法 |
CN108630657A (zh) * | 2017-03-24 | 2018-10-09 | 联华电子股份有限公司 | 半导体结构及其制作方法 |
CN108630657B (zh) * | 2017-03-24 | 2020-12-15 | 联华电子股份有限公司 | 半导体结构及其制作方法 |
US10825769B2 (en) | 2018-04-16 | 2020-11-03 | Winbond Electronics Corp. | Semiconductor devices and methods for manufacturing the same |
CN110416182A (zh) * | 2018-04-28 | 2019-11-05 | 华邦电子股份有限公司 | 半导体装置及其制造方法 |
CN110416182B (zh) * | 2018-04-28 | 2021-01-29 | 华邦电子股份有限公司 | 半导体装置及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20050156276A1 (en) | 2005-07-21 |
JP4673557B2 (ja) | 2011-04-20 |
JP2005203688A (ja) | 2005-07-28 |
CN100444314C (zh) | 2008-12-17 |
CN101339925A (zh) | 2009-01-07 |
US7579266B2 (en) | 2009-08-25 |
US7323760B2 (en) | 2008-01-29 |
US20080081454A1 (en) | 2008-04-03 |
CN101339925B (zh) | 2011-07-27 |
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