JP4673557B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP4673557B2 JP4673557B2 JP2004010596A JP2004010596A JP4673557B2 JP 4673557 B2 JP4673557 B2 JP 4673557B2 JP 2004010596 A JP2004010596 A JP 2004010596A JP 2004010596 A JP2004010596 A JP 2004010596A JP 4673557 B2 JP4673557 B2 JP 4673557B2
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Description
K. Arndt et al., Reliability of Laser Activated Metal Fuses in DRAMs, 1999 IEEE/CPMT Inte'l Electronics Manufacturing Technology Symposium, p.389-394
(実施形態2)
本実施形態は、実施形態1で示した構成で、ヒューズ切断後の水分の侵入を防ぐためにヒューズ122形成部位の下層にガードリングを設けたものである。
101 下地絶縁膜
106、112、212 SiON膜
108 SiN膜
102、110、210 SiO2膜
114 レジスト
120 Cu配線
121 Cu膜
122 ヒューズ
123 Cu腐蝕防止膜
124 Al配線
128、132 TiN膜
130 Al−Cu膜
141a パッド用開口パターン
141b ヒューズ用開孔パターン
142 ヒューズ用開口部
Claims (11)
- 半導体基板上に形成された回路と、
前記半導体基板上に設けられた下地絶縁膜と、
前記下地絶縁膜中に設けられた銅配線と、
前記回路に接続され、前記下地絶縁膜上に設けられたヒューズと、
前記ヒューズ上、前記銅配線上および前記下地絶縁膜上に設けられ、前記ヒューズおよび前記銅配線を覆う第1のSiON膜と、
前記第1のSiON膜上に設けられたエッチングストッパ膜と、
前記エッチングストッパ膜上に設けられた層間絶縁膜と、
前記層間絶縁膜上に設けられ、前記銅配線と接続するボンディングパッドと、
前記ボンディングパッド上および前記層間絶縁膜上に設けられた第2のSiON膜と、
前記第2のSiON膜上に設けられた有機膜と、
を有しており、
前記エッチングストッパ膜、前記層間絶縁膜、前記第2のSiON膜および前記有機膜は、平面視で前記ヒューズと重なる第1の開口部を有し、
前記第2のSiON膜および前記有機膜は、平面視で前記ボンディングパッドと重なる第2の開口部を有し、
前記エッチングストッパ膜は、SiN膜またはSiCN膜からなることを特徴とする半導体装置。 - 前記回路は銅配線を含むことを特徴とする請求項1記載の半導体装置。
- 前記下地絶縁膜に埋め込まれ、かつ、前記ヒューズの外周部を取り囲んで形成されたガードリングを有することを特徴とする請求項1記載の半導体装置。
- 前記下地絶縁膜に埋め込まれ、かつ、前記ヒューズの外周部を取り囲んで形成されたガードリングを有することを特徴とする請求項2記載の半導体装置。
- 前記ガードリングは前記銅配線と同一平面上に形成されていることを特徴とする請求項4記載の半導体装置。
- 前記第1のSiON膜の膜厚は150〜300nmであることを特徴とする請求項1乃至5のいずれか一項に記載の半導体装置。
- 前記第1のSiON膜の膜厚は180〜250nmであることを特徴とする請求項1乃至5のいずれか一項に記載の半導体装置。
- 半導体基板上に下地絶縁膜を形成する工程と、
前記下地絶縁膜に銅配線を形成する工程と、
前記下地絶縁膜上にヒューズを形成する工程と、
前記ヒューズと前記銅配線を覆って第1のSiON膜を形成する工程と、
前記第1のSiON膜上にエッチングストッパ膜を形成する工程と、
前記エッチングストッパ膜上に絶縁膜を形成する工程と、
前記銅配線の一部の上に形成された前記第1のSiON膜と前記エッチングストッパ膜と前記絶縁膜を除去する工程と、
前記銅配線と接続されたボンディングパッドを形成する工程と、
前記ボンディングパッドを覆うようにして第2のSiON膜を形成する工程と、
前記第2のSiON膜上に有機膜を形成する工程と、
前記ボンディングパッドの一部の上に形成された前記有機膜と前記第2のSiON膜を除去すると共に、前記ヒューズの一部の上に形成された前記有機膜と前記第2のSiON膜と前記絶縁膜を、前記エッチングストッパ膜によってストップされるエッチングにより除去する工程と、
前記ヒューズの一部の上に形成された前記エッチングストッパ膜を除去する工程とを含むことを特徴とする半導体装置の製造方法。 - 前記エッチングストッパ膜は窒化シリコン膜を含むことを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記エッチングストッパ膜はSiCN膜を含むことを特徴とする請求項8に記載の半導体装置の製造方法。
- 前記エッチングストッパ膜の膜厚は30〜100nmであることを特徴とする請求項8乃至10のいずれか一項記載の半導体装置の製造方法。
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CN2008101449544A CN101339925B (zh) | 2004-01-19 | 2005-01-18 | 半导体装置 |
CNB2005100045319A CN100444314C (zh) | 2004-01-19 | 2005-01-18 | 半导体装置的制造方法 |
US11/037,166 US7323760B2 (en) | 2004-01-19 | 2005-01-19 | Fuse structure for semiconductor integrated circuit with improved insulation film thickness uniformity and moisture resistance |
US11/947,807 US7579266B2 (en) | 2004-01-19 | 2007-11-30 | Fuse structure for semiconductor integrated circuit with improved insulation film thickness uniformity and moisture resistance |
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CN101339925B (zh) | 2011-07-27 |
CN1645565A (zh) | 2005-07-27 |
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US7323760B2 (en) | 2008-01-29 |
US7579266B2 (en) | 2009-08-25 |
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US20080081454A1 (en) | 2008-04-03 |
JP2005203688A (ja) | 2005-07-28 |
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