CN108630657B - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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CN108630657B
CN108630657B CN201710180554.8A CN201710180554A CN108630657B CN 108630657 B CN108630657 B CN 108630657B CN 201710180554 A CN201710180554 A CN 201710180554A CN 108630657 B CN108630657 B CN 108630657B
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layer
metal
fuse
pad
opening
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CN108630657A (zh
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张峰溢
李甫哲
郭明峰
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Priority to US15/497,182 priority patent/US10472731B2/en
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Priority to US16/594,088 priority patent/US10619266B2/en
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Abstract

本发明公开一种半导体结构及其制作方法，该半导体结构的制作方法包含提供一基底，在基底上形成焊垫金属以及熔丝金属，然后形成衬层以及蚀刻停止层至少覆盖熔丝金属的顶面，在基底上形成介电层与钝化层，再于钝化层中定义出焊垫开口和熔丝开口，进行第一蚀刻步骤自焊垫开口以及熔丝开口移除暴露的介电层直到焊垫金属的顶面以及蚀刻停止层的表面分别自焊垫开口以及熔丝开口暴露出来，再进行第二蚀刻步骤，自熔丝开口移除暴露的蚀刻停止层直到暴露出衬层的一表面。

Description

半导体结构及其制作方法
技术领域
本发明涉及一种半导体结构及其制作方法，特别是涉及一种焊垫开口结构与熔丝开口结构及其制作方法。
背景技术
随着半导体制作工艺的微小化以及复杂度的提高，半导体元件也变得更容易受各式缺陷或杂质所影响，而单一金属连线、二极管或晶体管等的失效往往即构成整个芯片的缺陷。因此为了解决这个问题，现行技术便会在集成电路中形成一些可熔断的连接线，也就是熔丝(fuse)，以确保集成电路的可利用性。熔丝是连接集成电路中的冗余电路，一旦检测发现电路具有缺陷时，这些连接线就可用于修复或取代有缺陷的电路。熔丝可以是由半导体材料或金属材料制作而成，例如多晶硅或金属，其中金属熔丝由于具有较好的良率而被广泛应用。
一般而言，金属熔丝是整合制作在金属内连线系统中，可以与某中间金属层(inter metal)同层，或者与最后金属层(last metal)同层。制作芯片的最后制作工艺中，通常包含于钝化层和介电层中形成焊垫开口(pad opening)以暴露出焊垫(pad)作为后续电连接使用，同时也需于钝化层和介电层中形成熔丝开口(fuse opening)，若是在后续需要重绕电路时，可自熔丝开口烧断金属熔丝。
暴露在熔丝开口中的金属熔丝通常会覆盖一介电材料层，以避免金属熔丝被氧化或腐蚀而影响到良率。但是，介电材料层的厚度和均匀性会影响到烧断金属熔丝的过程的稳定性。此外，在制作焊垫开口与熔丝开口的过程中，光致抗蚀剂材料或显影液可能会与焊垫金属或熔丝金属直接接触而造成残留或腐蚀金属。有鉴于此，本领域仍需一种改良的焊垫开口与熔丝开口结构及其制作方法，可避免上述问题。
发明内容
本发明目的在于提供一种半导体结构及其制作方法，其中包含整合制作的焊垫开口与熔丝开口，可具有较简化的制作工艺以及较好的良率。
本发明一方面提供一种半导体结构的制作方法。首先，提供一基底，并于基底上形成一焊垫金属以及一熔丝金属。然后，在基底上依序形成一衬层以及一蚀刻停止层，至少覆盖熔丝金属的一顶面。接着，在基底上形成介电层，完全覆盖焊垫金属以及熔丝金属，然后于介电层上形成一钝化层。在钝化层中定义出一位于焊垫金属正上方的焊垫开口和一位于熔丝金属正上方的熔丝开口，分别暴露出部分介电层，然后进行第一蚀刻步骤，自焊垫开口以及熔丝开口移除暴露的介电层直到焊垫金属的顶面以及蚀刻停止层的表面分别自焊垫开口以及熔丝开口暴露出来，再进行第二蚀刻步骤，自熔丝开口移除暴露的蚀刻停止层直到暴露出衬层的一表面。
本发明另一方面提供一种半导体结构，包含一基底，其上设有一焊垫金属以及一熔丝金属，一衬层以及一蚀刻停止层至少覆盖熔丝金属的顶面。一介电层位于基底上并且覆盖住焊垫金属和熔丝金属，一钝化层位于介电层上。一熔丝开口位于熔丝金属的正上方并且贯穿钝化层、介电层以及蚀刻停止层，但不贯穿衬层，暴露出衬层的一表面。一焊垫开口位于焊垫金属的正上方并贯穿钝化层以及介电层，暴露出焊垫金属的一顶面。
附图说明
图1至图6为本发明第一实施例的半导体结构的制作步骤剖面示意图；
图7为本发明第一实施例的一变化型的示意图；
图8至图10为本发明第二实施例的半导体结构的制作步骤剖面示意图；
图11为本发明第二实施例的一变化型的示意图；
图12至图15b为本发明第三实施例的半导体结构的制作步骤剖面示意图；
图16至图20为本发明第四实施例的半导体结构的制作步骤剖面示意图。
主要元件符号说明
Figure BDA0001253467880000021
Figure BDA0001253467880000031
具体实施方式
接下来的详细叙述须参照相关附图所示内容，用来说明可依据本发明具体实行的实施例，其中相同或类似的特征通常以相同的附图标记描述，描述的结构并不必然按比例绘制。在不悖离本发明的范围内，可做结构、逻辑和电性上的修改应用在其他实施例上。
图1至图6为本发明第一实施例的半导体结构的制作步骤剖面示意图。
请参考图1和图2。首先提供一基底10，一焊垫金属16以及一熔丝金属18形成于基底10上。基底10可以是已完成前段制作工艺(FEOL)和部分后段制作工艺(BEOL)的半导体基底，为了简化图示，仅绘示出基底10最上层的层间介电层14及其中分别电连接至焊垫金属16和熔丝金属18的导电插塞12。层间介电层14可包含由氧化硅、未掺杂硅玻璃、氟掺杂硅玻璃或其他介电材料构成的单层或多层结构。导电插塞12可以是由铝、铜、钨或其他金属构成。第一实施例中，焊垫金属16和熔丝金属18具有相同的水平高度，是形成在同一材料层中，例如是铝、铜、钨或其他金属材料层。根据实施例，焊垫金属16和熔丝金属18是形成在半导体结构的最顶金属层(Top metal)中。形成焊垫金属16与熔丝金属18的方法例如于基底10上全面性地形成一金属材料层，例如铝，接着图案化该金属材料层以同时定义出焊垫金属16与熔丝金属18。在其他实施例中，可以于形成该金属材料层时，同时以该金属材料层填充层间介电层14中的导电插塞开口，制作出与焊垫金属16和熔丝金属18一体成型的导电插塞12。值得注意的是，基底10上可另包含内连线金属(图未示)，与焊垫金属16和熔丝金属18同时定义在该金属材料层中，与焊垫金属16和熔丝金属18具有相同的水平高度。
接着，依序形成衬层22和蚀刻停止材料层24，共型地覆盖在基底10、焊垫金属16与熔丝金属18的顶面及侧壁上。蚀刻停止材料层24较佳选用与后续形成的介电层32(参考图2)不同的材料，以于蚀刻制作工艺中产生蚀刻选择性，例如当介电层32为氧化硅时，蚀刻停止材料层24较佳选用氮化硅、氮氧化硅或氮碳化硅。衬层22较佳选用与蚀刻停止材料层24不同的材料，例如氧化硅。
接着，在基底10上形成图案化光致抗蚀剂层26，完全覆盖住熔丝金属18的顶面和侧壁并延伸覆盖熔丝金属18周围部分的基底10，但不覆盖住焊垫金属16的顶面和侧壁，暴露出位于焊垫金属16顶面和侧壁上的部分蚀刻停止材料层24。根据本发明一实施例，在形成图案化光致抗蚀剂层26之前，可选择性地对蚀刻停止材料层24的表面进行氧处理而形成一氧化物层(图未示)，改善图案化光致抗蚀剂层26与蚀刻停止材料层24之间的结合品质。接着，以对衬层22和蚀刻停止材料层24具有蚀刻选择性的蚀刻制作工艺，例如湿蚀刻制作工艺或干蚀刻制作工艺，对暴露出来的蚀刻停止材料层24进行蚀刻移除。移除图案化光致抗蚀剂层26后，剩余的蚀刻停止材料层24即为蚀刻停止层24a，覆盖在熔丝金属18的顶面和侧壁上。
接着全面性地形成介电层32覆盖住焊垫金属16和熔丝金属18，然后再于介电层32上形成介电层34以及钝化层36。介电层32的材料包含氧化硅、未掺杂硅玻璃、氟掺杂硅玻璃或其他介电材料。介电层34的材料包含氮化硅、氮化硅、氮氧化硅或氮碳化硅。钝化层36的材料包含环氧化物(epoxy)、聚酰亚胺(polyimide)、苯并环丁烯(benzocyclobutene,BCB)等有机材料，较佳是选用感光性聚酰亚胺，可通过光刻制作工艺而被图案化。根据所述实施例，形成介电层32后可不进行平坦化，随即于其上形成介电层34，因此介电层32与介电层34可能具有对应于焊垫金属16和熔丝金属18位置的表面形貌。在其他实施例中，也可选择对介电层32进行平坦化后再形成介电层34，使得介电层32和介电层34均具有平坦的表面。较佳者，钝化层36是通过涂布的方式形成在介电层34上，可自我流平而具有平坦的表面。
请参考图3。接着，图案化钝化层36以于钝化层36中定义出焊垫开口36a以及熔丝开口36b，分别位于焊垫金属16和熔丝金属18的正上方，分别暴露出部分介电层34。较佳者，焊垫开口36a和熔丝开口36b的宽度小于焊垫金属16和熔丝金属18的宽度，换句话说，焊垫开口36a和熔丝开口36b是完全位于焊垫金属16和熔丝金属18正上方的范围内。
接下来的图4至图6说明以钝化层36为蚀刻掩模，对焊垫金属16和熔丝金属18正上方材料层进行蚀刻，以使定义在钝化层36的焊垫开口36a和熔丝开口36b往下延伸至目标深度。
请参考图4。在钝化层36中定义出焊垫开口36a和熔丝开口36b后，接着进行第一蚀刻步骤42，同时自焊垫开口36a和熔丝开口36b往下蚀刻移除暴露的介电层34，直到显露出下方的介电层32并移除了部分介电层32。第一蚀刻步骤42可以是以含氟气体为蚀刻气体的干蚀刻制作工艺，含氟气体包含CF4、CHF3、C4F6、C4F8或者其它有机氟化合物，通过调整蚀刻气体的比例使第一蚀刻步骤42对介电层34和介电层32具有低蚀刻选择性，蚀刻速率比较佳约是1:1。原先暴露在焊垫开口36a和熔丝开口36b的介电层34的表面形貌可通过第一蚀刻步骤42的低蚀刻选择性而被复制到暴露的介电层32表面，使得分别暴露在焊垫开口36a和熔丝开口36b的介电层32具有例如凸起的表面形貌。
请参考图5，接着进行第二蚀刻步骤44，以焊垫金属16和蚀刻停止层24a做为停止层，自焊垫开口36a和熔丝开口36b往下移除暴露的介电层32，直到焊垫金属16和蚀刻停止层24a分别自焊垫开口36a和熔丝开口36b暴露出来。第二蚀刻步骤42同样是以含氟气体为蚀刻气体的干蚀刻制作工艺，含氟气体包含CF4、CHF3、C4F6、C4F8或者其它有机氟化合物，其对介电层32和蚀刻停止层24a具有高蚀刻选择性，蚀刻速率比较佳介于3.5:1至5.5:1之间。由于衬层22也由氧化硅构成，因此位于焊垫金属16顶面正上方的衬层22也会被第二蚀刻步骤44移除而暴露出焊垫金属16。
请参考图6。接着进行第三蚀刻步骤46，自熔丝开口36b移除蚀刻停止层24a，暴露出其正下方的衬层22，然后再进一步移除部分衬层22至到剩余的衬层22具有目标厚度T，并且不暴露熔丝金属18的任何部分。第三蚀刻步骤46同样是以含氟气体为蚀刻气体的干蚀刻制作工艺，含氟气体包含CF4、CHF3、C4F6、C4F8或者其它有机氟化合物，其对蚀刻停止层24a和衬层22具有低蚀刻选择性，蚀刻速率比较佳约是1:1。
本发明选择性地于熔丝金属正上方设置衬层以及蚀刻停止层，因此可以用相同的制作工艺同时形成焊垫开口和熔丝开口，还可在熔丝金属上留下厚度较均匀且准确的介电层(剩余的衬层)，作为熔丝金属的保护层，避免熔丝金属暴露出来而被氧化影响到良率，且其较均匀且准确的厚度也使得修补电路时的烧断熔丝过程可较稳定。此外，本发明还可避免钝化层、光致抗蚀剂材料或者显影液与焊垫金属或熔丝金属的直接接触，可降低发生残留或腐蚀的机会。
请参考图7，为本发明第一实施例的一变化型，与前文所述制作工艺不同的地方在于，对暴露的蚀刻停止材料层24进行蚀刻移除时，通过调整蚀刻制作工艺的参数来控制蚀刻制作工艺的各向异性特性，使得位于焊垫金属16侧壁的蚀刻停止材料层24不会被蚀刻移除，留下来成为间隙壁24b。已知，若当焊垫开口36a与焊垫金属16之间发生对准偏差时，可能会在焊垫金属侧壁和焊垫开口36a侧壁之间形成一狭缝，容易残留蚀刻气体或液体。图7所示变化型即可通过形成间隙壁24b，来减少焊垫金属16侧壁暴露出来而被残留的蚀刻气体或液体腐蚀的机会，提高了制作工艺余裕度。图中间隙壁24b与衬层22大致上等高并且具有平整的顶面，也可通过调整蚀刻制作工艺的参数而制作出不同形状的间隙壁24b，例如顶面为弧形或斜面的间隙壁。
图8至图10为本发明第二实施例的半导体结构的制作步骤剖面示意图，为了简化说明，其中与第一实施例相同的材料层或相同的制作工艺步骤以相同的符号表示。与第一实施例主要不同处在于，第二实施例中，图案化光致抗蚀剂层26仅覆盖在熔丝金属18的正上方，使得形成的蚀刻停止层24a也仅位于熔丝金属18的正上方。
同样的，提供一基底10，可包含导电插塞12以及层间介电层14，并于基底10上形成焊垫金属16和熔丝金属18。接着形成衬层22和蚀刻停止材料层24共型地覆盖在基底10、焊垫金属16与熔丝金属18的顶面及侧壁上。接着形成图案化光致抗蚀剂层26，仅覆盖住位于熔丝金属18顶面正上方的蚀刻停止材料层24，如图8所示。图案化光致抗蚀剂层26的宽度较佳等于或略大于熔丝金属18的宽度。接着，移除未被图案化光致抗蚀剂层26覆盖的蚀刻停止材料层24，形成蚀刻停止层24a，仅覆盖在熔丝金属18顶面的正上方。后续，依序形成介电层32、介电层34和钝化层36，并图案化钝化层36，在钝化层36中定义出焊垫开口36a和熔丝开口36b，如图9所示。
接着与第一实施例相同，以钝化层36为蚀刻掩模，依序进行第一蚀刻步骤42、第二蚀刻步骤44以及第三蚀刻步骤46，自焊垫开口36a和熔丝开口36b往下蚀刻，直到暴露出焊垫金属16和覆盖熔丝金属18的衬层22，如图10所示。
请参考图11，为本发明第二实施例的一变化型。第二实施例中，同样可通过调整蚀刻制作工艺参数来控制各向异性的特性，使得位于焊垫金属16和熔丝金属18的侧壁的蚀刻停止材料层24不会被蚀刻移除，可留下来成为间隙壁24b。
图12至图15b为本发明第三实施例的半导体结构的制作步骤剖面示意图，为了简化说明，其中与前文所述实施例相同的材料层或相同的制作工艺步骤以相同的符号表示。与第一实施例主要不同处在于，第三实施例中，图案化光致抗蚀剂层26仅暴露出位于焊垫金属16正上方的蚀刻停止材料层24，因此移除该暴露的蚀刻停止材料层24后形成的蚀刻停止层24a仅包含一开口24c暴露出位于焊垫金属16的正上方的衬层22。
同样的，提供一基底10，可包含导电插塞12以及层间介电层14，并于基底10上形成焊垫金属16和熔丝金属18。接着形成衬层22和蚀刻停止材料层24共型地覆盖在基底10、焊垫金属16与熔丝金属18的顶面及侧壁上。接着于蚀刻停止材料层24上形成图案化光致抗蚀剂层26，仅暴露出部分焊垫金属16顶面正上方的蚀刻停止材料层24，如图12所示。接着，移除未被图案化光致抗蚀剂层26覆盖的蚀刻停止材料层24，形成蚀刻停止层24a，包含一开口24c位于焊垫金属16顶面的正上方。后续，依序形成介电层32、介电层34和钝化层36，并图案化钝化层36，在钝化层36中定义出焊垫开口36a和熔丝开口36b，如图13所示。焊垫开口36a大致上对准于开口24c。
接着与第一实施例相同，以钝化层36为蚀刻掩模，依序进行第一蚀刻步骤42、第二蚀刻步骤44以及第三蚀刻步骤46，自焊垫开口36a和熔丝开口36b往下蚀刻直到暴露出焊垫金属16和覆盖熔丝金属18的衬层22。如第14图所示，当焊垫开口36a与开口24c具有相同宽度并对准时，衬层22和介电层32被蚀刻停止层24a完全区隔开，并不直接接触。蚀刻停止层24a和衬层22的端点会自焊垫开口36a的侧壁暴露出来。
当焊垫开口36a与开口24c具有不同宽度时，则可能形成如图15a、图15b所示结构。请参考图15a，当开口24c的宽度大于焊垫开口36a的宽度时，仅衬层22的端点会自焊垫开口36a的侧壁显露出来，蚀刻停止层24a的端点会埋藏在介电层32中，并不会自焊垫开口36a显露出来。相反的，请参考图15b，当开口24c的宽度小于钝化层36的焊垫开口36a的宽度时，第二蚀刻步骤44完成后第三蚀刻步骤46进行前，开口24c周围的蚀刻停止层24a及被其遮蔽住而未于第二蚀刻步骤44中被移除的衬层22会突出于焊垫开口36a的侧壁。后续第三蚀刻步骤46移除掉开口24c周围的蚀刻停止层24a并对其正下方的衬层22进行蚀刻，因此在焊垫开口36a的底角位置形成衬层足部22a，使得焊垫开口36a的底部具有较圆滑的剖面形状，可避免后续制作工艺使用的气体或液体残留在焊垫开口36a底角造成金属腐蚀，也使得后续于焊垫开口36a中形成金属打线或焊锡凸块时，金属材料较容易完全填满焊垫开口36a。
图16至图20为本发明第四实施例的半导体结构的制作步骤剖面示意图。为了简化说明，与前文所述实施例相同的材料层或相同的制作工艺步骤以相同的符号表示。第四实施例中主要不同处在于，焊垫金属54和熔丝金属18是形成在不同金属层中，是位于基底10上不同水平高度的位置，例如焊垫金属54是形成在最顶金属层(top metal)中，而熔丝金属18是形成在该最顶金属层形成前的金属层中。
请参考图16。首先提供一基底10，一内连线金属20以及一熔丝金属18形成于基底10上。基底10可包含层间介电层14，以及分别电连接至内连线金属20与熔丝金属18的导电插塞12。形成内连线金属20与熔丝金属18的方法例如于基底10上形成一金属材料层，接着图案化该金属材料层以定义出内连线金属20与熔丝金属18。类似的，可以于形成该金属材料层时同时以该金属材料层填充层间介电层14中的导电插塞开口，制作出与内连线金属20和熔丝金属18一体成型的导电插塞12。接着，依序形成衬层22以及蚀刻停止材料层24，共型地覆盖在基底10、内连线金属20与熔丝金属18的顶面及侧壁上，然后于蚀刻停止材料层24上形成层间介电层52。并对层间介电层52进行平坦化后，在层间介电层52上形成焊垫金属54。接着依序形成介电层32、介电层34和钝化层36，全面性地覆盖焊垫金属54和层间介电层52。层间介电层52与介电层32可以是由相同材料构成，例如都是氧化硅。层间介电层52可以是单层或多层结构。层间介电层52中可形成有其他半导体结构，例如电容、金属绕线、导电插塞，为了简化而并未绘示于图中。但须注意的是，熔丝金属18正上方的层间介电层52中并不会形成有其他半导体结构。
请参考图17。接着图案化钝化层36，以于钝化层36中定义出焊垫开口36a以及熔丝开口36b。焊垫开口36a位于焊垫金属54的正上方，熔丝开口36b位于熔丝金属18的正上方，分别暴露出部分介电层34。
请参考图18。接着以图案化的钝化层36为蚀刻掩模进行第一蚀刻步骤42，同时自焊垫开口36a和熔丝开口36b移除暴露的介电层34直到显露出下方的介电层32。相同的，第一蚀刻步骤42对介电层34和介电层32的蚀刻速率比较佳约是1:1。第四实施例中，原先暴露在焊垫开口36a和熔丝开口36b的部分介电层34大致上具有平坦的表面，因此第一蚀刻步骤42后，暴露出来的部分介电层32也大致上具有平坦的表面。
请参考图19，接着同样以钝化层36为蚀刻掩模，以蚀刻停止材料层24和焊垫金属54作为停止层，进行第二蚀刻步骤44，自焊垫开口36a和熔丝开口36b往下蚀刻，直到分别暴露出焊垫金属54和覆盖在熔丝金属18正上方的蚀刻停止材料层24。相同的，第二蚀刻步骤44对介电层32(介电层52)和蚀刻停止材料层24的蚀刻速率比较佳介于3.5:1至5.5:1之间。
请参考图20。接着进行第三蚀刻步骤46，自熔丝开口36b移除暴露的蚀刻停止材料层24并进一步往下蚀刻移除部分衬层22至剩余目标厚度T，并且不暴露出熔丝金属18的任何部分。相同的，第三蚀刻步骤46对蚀刻停止材料层24和衬层22的蚀刻速率比较佳约是1:1。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (12)

1.一种半导体结构的制作方法，包含：
提供一基底；
在该基底上形成一焊垫金属以及一熔丝金属，其中该焊垫金属以及该熔丝金属是形成在同一材料层中；
形成一衬层于该焊垫金属及该熔丝金属上；
形成一蚀刻停止层，至少覆盖该熔丝金属的一顶面；
形成一介电层于该衬层及该蚀刻停止层上，其中该衬层与该介电层直接接触；
在该介电层上形成一钝化层；
在该钝化层中定义出一焊垫开口以及一熔丝开口，其中该焊垫开口位于该焊垫金属正上方，该熔丝开口位于该熔丝金属正上方；
进行一第一蚀刻步骤，自该焊垫开口以及该熔丝开口移除该介电层，直到该焊垫金属以及该蚀刻停止层分别自该焊垫开口以及该熔丝开口暴露出来；以及
进行一第二蚀刻步骤，自该熔丝开口移除暴露的该蚀刻停止层直到暴露出该衬层。
2.如权利要求1所述的制作方法，其中该第一蚀刻步骤对于该介电层以及该蚀刻停止层具有蚀刻选择性。
3.如权利要求1所述的制作方法，其中该衬层以及该介电层包含氧化硅，该蚀刻停止层包含氮化硅。
4.如权利要求1所述的制作方法，其中该钝化层包含聚酰亚胺(polyimide)。
5.如权利要求1所述的制作方法，其中形成该衬层以及形成该蚀刻停止层的步骤包含:
形成该衬层，共型地覆盖该基底、该焊垫金属以及该熔丝金属的顶面和侧壁；
在该衬层上形成一蚀刻停止材料层；
移除位于该焊垫金属正上方的部分该蚀刻停止材料层，剩余的该蚀刻停止材料层即为该蚀刻停止层。
6.如权利要求5所述的制作方法，其中移除部分该蚀刻停止材料层的步骤包含移除该蚀刻停止材料层位于该焊垫金属的侧壁的部分。
7.如权利要求5所述的制作方法，其中移除部分该蚀刻停止材料层的步骤包含完全移除该蚀刻停止材料层非位于该熔丝金属正上方的部分。
8.一种半导体结构，包含：
基底，焊垫金属以及熔丝金属位于该基底上，其中该焊垫金属以及该熔丝金属是形成在同一材料层中；
衬层，位于该焊垫金属及该熔丝金属上；
蚀刻停止层，至少覆盖该熔丝金属的顶面；
介电层，覆盖该焊垫金属以及该熔丝金属，其中该衬层与该介电层直接接触；
钝化层，位于该介电层上；
焊垫开口，位于该焊垫金属的正上方，贯穿该钝化层、该介电层以及该衬层，暴露出该焊垫金属；以及
熔丝开口，位于该熔丝金属正上方，贯穿该钝化层、该介电层以及该蚀刻停止层，但不贯穿该衬层，暴露出该衬层的一表面。
9.如权利要求8所述的半导体结构，其中该衬层以及该介电层包含氧化硅，该蚀刻停止层包含氮化硅。
10.如权利要求8所述的半导体结构，其中该钝化层包含聚酰亚胺(polyimide)。
11.如权利要求8所述的半导体结构，其中该介电层与该焊垫金属的侧壁上的该衬层直接接触，该介电层与该熔丝金属的侧壁上的该衬层被该蚀刻停止层区隔开而不直接接触。
12.如权利要求8所述的半导体结构，其中非位于该熔丝金属正上方的该衬层与该介电层直接接触。
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