FR3091410B1 - Procédé de gravure - Google Patents

Procédé de gravure Download PDF

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Publication number
FR3091410B1
FR3091410B1 FR1874151A FR1874151A FR3091410B1 FR 3091410 B1 FR3091410 B1 FR 3091410B1 FR 1874151 A FR1874151 A FR 1874151A FR 1874151 A FR1874151 A FR 1874151A FR 3091410 B1 FR3091410 B1 FR 3091410B1
Authority
FR
France
Prior art keywords
engraving process
selective etching
etching
abstract
locally
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1874151A
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English (en)
Other versions
FR3091410A1 (fr
Inventor
Delia Ristoiu
Pierre Bar
François Leverd
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Original Assignee
STMicroelectronics Crolles 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Crolles 2 SAS filed Critical STMicroelectronics Crolles 2 SAS
Priority to FR1874151A priority Critical patent/FR3091410B1/fr
Priority to US16/709,251 priority patent/US11469095B2/en
Publication of FR3091410A1 publication Critical patent/FR3091410A1/fr
Application granted granted Critical
Publication of FR3091410B1 publication Critical patent/FR3091410B1/fr
Priority to US17/940,758 priority patent/US20230005735A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02019—Chemical etching
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/36—Mechanical coupling means
    • G02B6/3628—Mechanical coupling means for mounting fibres to supporting carriers
    • G02B6/3684—Mechanical coupling means for mounting fibres to supporting carriers characterised by the manufacturing process of surface profiling of the supporting carrier
    • G02B6/3692—Mechanical coupling means for mounting fibres to supporting carriers characterised by the manufacturing process of surface profiling of the supporting carrier with surface micromachining involving etching, e.g. wet or dry etching steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/26—Optical coupling means
    • G02B6/30—Optical coupling means for use between fibre and thin-film device
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/36—Mechanical coupling means
    • G02B6/3628—Mechanical coupling means for mounting fibres to supporting carriers
    • G02B6/3632—Mechanical coupling means for mounting fibres to supporting carriers characterised by the cross-sectional shape of the mechanical coupling means
    • G02B6/3644—Mechanical coupling means for mounting fibres to supporting carriers characterised by the cross-sectional shape of the mechanical coupling means the coupling means being through-holes or wall apertures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67253—Process monitoring, e.g. flow or thickness monitoring

Abstract

Procédé de gravure La présente description concerne un procédé de formation d'une cavité (30) traversant un empilement (10) de couches (6, 8) incluant une couche inférieure (61) dont une première portion (24) présente localement une surépaisseur, le procédé comprenant une première étape de gravure non sélective et une deuxième étape de gravure sélective à l'aplomb de la première portion (24). Figure pour l'abrégé : Fig. 6
FR1874151A 2018-12-26 2018-12-26 Procédé de gravure Active FR3091410B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1874151A FR3091410B1 (fr) 2018-12-26 2018-12-26 Procédé de gravure
US16/709,251 US11469095B2 (en) 2018-12-26 2019-12-10 Etching method
US17/940,758 US20230005735A1 (en) 2018-12-26 2022-09-08 Etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1874151A FR3091410B1 (fr) 2018-12-26 2018-12-26 Procédé de gravure

Publications (2)

Publication Number Publication Date
FR3091410A1 FR3091410A1 (fr) 2020-07-03
FR3091410B1 true FR3091410B1 (fr) 2021-01-15

Family

ID=66867317

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1874151A Active FR3091410B1 (fr) 2018-12-26 2018-12-26 Procédé de gravure

Country Status (2)

Country Link
US (2) US11469095B2 (fr)
FR (1) FR3091410B1 (fr)

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63258021A (ja) * 1987-04-16 1988-10-25 Toshiba Corp 接続孔の形成方法
GB2230135A (en) * 1989-04-05 1990-10-10 Koninkl Philips Electronics Nv Dopant diffusion in semiconductor devices
US5229785A (en) * 1990-11-08 1993-07-20 Hewlett-Packard Company Method of manufacture of a thermal inkjet thin film printhead having a plastic orifice plate
US6211092B1 (en) * 1998-07-09 2001-04-03 Applied Materials, Inc. Counterbore dielectric plasma etch process particularly useful for dual damascene
US6930034B2 (en) * 2002-12-27 2005-08-16 International Business Machines Corporation Robust ultra-low k interconnect structures using bridge-then-metallization fabrication sequence
JP4113199B2 (ja) * 2005-04-05 2008-07-09 株式会社東芝 半導体装置
US7371684B2 (en) * 2005-05-16 2008-05-13 International Business Machines Corporation Process for preparing electronics structures using a sacrificial multilayer hardmask scheme
JP2013120786A (ja) * 2011-12-06 2013-06-17 Toshiba Corp 半導体記憶装置
JP6327970B2 (ja) * 2014-06-19 2018-05-23 東京エレクトロン株式会社 絶縁膜をエッチングする方法
CN107004719B (zh) * 2014-11-28 2020-07-03 夏普株式会社 半导体装置及其制造方法
US9406693B1 (en) * 2015-04-20 2016-08-02 Sandisk Technologies Llc Selective removal of charge-trapping layer for select gate transistors and dummy memory cells in 3D stacked memory
US9484298B1 (en) * 2015-07-02 2016-11-01 Kabushiki Kaisha Toshiba Non-volatile memory device
CN106548979A (zh) * 2016-12-28 2017-03-29 武汉华星光电技术有限公司 层叠无机膜的蚀刻方法
CN108630657B (zh) * 2017-03-24 2020-12-15 联华电子股份有限公司 半导体结构及其制作方法
US20180286707A1 (en) * 2017-03-30 2018-10-04 Lam Research Corporation Gas additives for sidewall passivation during high aspect ratio cryogenic etch
US11417534B2 (en) * 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
JP2021180276A (ja) * 2020-05-15 2021-11-18 キオクシア株式会社 記憶装置

Also Published As

Publication number Publication date
FR3091410A1 (fr) 2020-07-03
US20200211835A1 (en) 2020-07-02
US11469095B2 (en) 2022-10-11
US20230005735A1 (en) 2023-01-05

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