TWI300616B - Flip chip structure - Google Patents

Flip chip structure Download PDF

Info

Publication number
TWI300616B
TWI300616B TW092117871A TW92117871A TWI300616B TW I300616 B TWI300616 B TW I300616B TW 092117871 A TW092117871 A TW 092117871A TW 92117871 A TW92117871 A TW 92117871A TW I300616 B TWI300616 B TW I300616B
Authority
TW
Taiwan
Prior art keywords
layer
chip structure
flip chip
copper
nickel
Prior art date
Application number
TW092117871A
Other languages
Chinese (zh)
Other versions
TW200501374A (en
Inventor
Chung Hsiung Ho
Tai Yuan Huang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW092117871A priority Critical patent/TWI300616B/en
Publication of TW200501374A publication Critical patent/TW200501374A/en
Application granted granted Critical
Publication of TWI300616B publication Critical patent/TWI300616B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Description

1300616 意1^117871 五、發明說明(1) 年 曰 修正 '【發明所屬之技術領域】 、 月係關於一種覆晶晶片結構’且特別是有關於一 種可避免鲜料凸塊迴銲後造成球底金屬層下方之(晶片)保 護層破壞。 一)、【先前技術】 、 在回度資訊化社會的今日,多媒體應用市場不斷地急 ^擴張’積體電路封裝技術也隨之朝電子裝置的數位化、 、罔路化、區域連接化以及使用人性化的趨勢發展。為達成 上述的要求’電子元件必須配合高速處理化、多功能化、 積集化、小型輕量化及低價化等多方面之要求,也因此積 體電路封叙技術也跟著朝向微型化、高密度化發展。其中 =格陣列式構裝(Bal 1 Gr id Array,BGA ),晶片尺寸構 M Chip-Scale Package,CSP ),覆晶構裝(Flip C^iip,F/C ),多晶片模組(Multi 一M〇dule,)等 南密度積體電路封裝技術也因應而生。 其中覆晶構裴技術(Flip Chip Packaging Technology)主要是利用面陣列(area array)的排列方式, 將多個銲墊(bonding pad)配置於晶片(die)之主動表面 (active surface),並在各個銲墊上形成凸塊(bump),接 著再將晶片翻面(flip)之後,利用晶片銲墊上的凸塊分別 電性(616(^!^〇^115〇及機械(1116(:^11][(^117)連接至基板 (substrate)或印刷電路板(PCB)之表面所對應的接墊 (mounting pad)。再者,由於覆晶接合技術係可應用於高 接腳數(High Pin Count)之晶片封裝結構,並同時且右1300616 Meaning 1^117871 V. Description of invention (1) Yearly revision '[Technical field to which the invention belongs], Monthly on a flip-chip structure' and especially related to a ball that can be avoided after reflow of fresh bumps The (wafer) protective layer underneath the bottom metal layer is destroyed. a), [previous technology], in today's information society, the multimedia application market continues to expand rapidly. 'Integrated circuit packaging technology has also been digitalized, smashed, and connected to electronic devices. Use human trends to develop. In order to achieve the above requirements, electronic components must meet the requirements of high-speed processing, multi-function, integration, small size, light weight, and low cost. Therefore, the integrated circuit sealing technology is also becoming more miniaturized and high. Density development. Among them, Bal 1 Gr id Array (BGA), chip size M Chip-Scale Package (CSP), Flip C^iip (F/C), multi-chip module (Multi A M〇dule,) and other southern density integrated circuit packaging technology also came into being. Flip Chip Packaging Technology mainly uses an array of area arrays to arrange a plurality of bonding pads on the active surface of the die. A bump is formed on each of the pads, and after the wafer is flipped, the bumps on the wafer pads are electrically used (616 (^^^^^^ and mechanical (1116(:^11) [(^117) is connected to a substrate (substrate) or a mounting pad corresponding to the surface of a printed circuit board (PCB). Furthermore, since the flip chip bonding technique can be applied to the high pin count (High Pin Count) ) chip package structure, and at the same time and right

1300616 修正 案號 92117871 五、發明說明(2) 小封裝面積及縮短訊號傳輸路徑等多項優點,所以覆晶接 合技術目前已經廣泛地應用在晶片封裝領域。 •而所謂的晶圓凸塊製程,則常見於覆晶技術(fHp ch 1 p)中,主要係在形成有多個晶片的晶圓上對外的接點 (通常是金屬銲墊)上形成球底金屬層(UBM,Unde;r1300616 Amendment Case No. 92117871 V. Invention Description (2) Small package area and shortened signal transmission path, etc., so flip chip bonding technology has been widely used in the field of chip packaging. • The so-called wafer bump process is common in flip chip technology (fHp ch 1 p), which is mainly used to form balls on external contacts (usually metal pads) on wafers with multiple wafers. Bottom metal layer (UBM, Unde;r

Metallurgy),接著於球底金屬層之上形成凸塊或植入銲球 以作為後續晶片與基板(substrate)電性導通之連接介面。 承上所述,請參照圖1,係為習知之覆晶晶片結構 1 〇 〇。覆晶晶片結構1 〇 〇係具有一主動表面丨〇 1、一保護層 102、一苯併環丁烯層(Benzocycl〇bui:ene,BCB)l〇3 及複數 個晶片銲墊104。其中,保護層102及晶片銲墊1〇4係形成於 主動表面101上,且保護層1〇2係暴露出晶片銲墊1〇4。另 外,苯併環丁烯層1 〇 3係形成於晶片保護層丨〇 2上,並暴露 出晶片銲墊104。再者,晶片銲墊上1〇4及苯併環丁烯層1〇3 上形成有一球底金屬層1〇6,且球底金屬層1〇6上形成有一 銲料凸塊108。其中,球底金屬層106係配置於晶圓銲墊1〇4 與銲料凸塊108之間,用以作為晶片銲墊1〇4及銲料凸塊1〇8 間之接合介面。 請再參考圖1,習知之球底金屬層1〇6主要包括黏著層 (adhesion layer ) l〇6a、阻障層(barrier layer ) 106b 及潤濕層(wettable layer ) 106c。黏著層l〇6a係用以增 加晶片銲墊104及阻障層l〇6b之間的接合強度,其材質例如 為紹或鈦等金屬。而阻障層1 Q β b係用以防止阻障層1 Q β b之 上下兩側的金屬發生擴散(diffusion)的現象,其常用材 貝例如為鎳飢合金、鎳銅合金及鎳等金屬。另外,潤濕層Metallurgy), then forming a bump or implanting a solder ball on the bottom metal layer to serve as a connection interface for subsequent wafer-substrate electrical conduction. As mentioned above, please refer to FIG. 1 , which is a conventional flip chip structure 1 〇 〇. The flip chip structure 1 〇 has an active surface 丨〇 1, a protective layer 102, a benzocyclobutene layer (Benzocycl 〇 ene, BCB) 〇 3 and a plurality of wafer pads 104. The protective layer 102 and the wafer pads 1〇4 are formed on the active surface 101, and the protective layer 1〇2 exposes the wafer pads 1〇4. Further, a benzocyclobutene layer 1 〇 3 is formed on the wafer protective layer 丨〇 2, and the wafer pad 104 is exposed. Further, a ball-bottom metal layer 1〇6 is formed on the wafer pad 1〇4 and the benzocyclobutene layer 1〇3, and a solder bump 108 is formed on the ball-bottom metal layer 1〇6. The ball metal layer 106 is disposed between the pad pads 1〇4 and the solder bumps 108 to serve as a bonding interface between the pad pads 1〇4 and the solder bumps 1〇8. Referring to FIG. 1 again, the conventional ball bottom metal layer 〇6 mainly includes an adhesion layer 〇6a, a barrier layer 106b, and a wettable layer 106c. The adhesive layer 16a is used to increase the bonding strength between the wafer pad 104 and the barrier layer 16b, and is made of a metal such as sinter or titanium. The barrier layer 1 Q β b is used to prevent diffusion of metal on the upper and lower sides of the barrier layer 1 Q β b , and the commonly used materials are, for example, nickel-star alloy, nickel-copper alloy, and nickel. . In addition, the wetting layer

circle

第7頁 1300616 —案號 921Π871 發明說明(3) 106c係用以增加球底金屬層106對於銲料凸塊108之沾附 力’其常用材質包括銅等金屬。值得注意的是,由於錫錯 合金具有較佳之銲接特性,所以銲料凸塊丨〇 8之材質經常採 用锡雜合金,惟鉛對於自然環境的影響甚鉅,故有無鉛銲 料(lead free s〇ider)之誕生,其中含鉛或無鉛之銲料 其組成成分均包括錫。 請繼續參考圖1,銲料凸塊108於迴銲(Reflow)過程 期間,常因銲料凸塊1〇8之内聚力作用,使得球化之銲料凸 ^08會使球體金屬層106之周邊向上牵引而使球體金屬層 執^部分下方之苯併環丁烯層(BCB Uyer)103及晶片銲 之骚銲料凸塊108之擠壓。然而由於苯併環丁烯層丨〇3 上Ϊίΐί較大(換言之’即是其較為堅硬),故常會使得 # =壓之苯併環丁烯層m下方之保護層ι〇2 二之二it擠壓而破裂。再者,更會造成球底金屬層 G6周邊下方之苯併環丁烯層⑽ i ay er ) 1 〇 3間剝洛脫離之現象。 、【發明内容】 有 構,用 料凸塊 金屬層 layer) 分下方 層之破 鑑於此,本發明之目的侈. Φ ^ ^ ^ '、在於楗出一種覆晶晶片結 之球化導致“:二 〜(Reflow)時,因銲 〈欠化導致球底金屬層之 之周邊與球底金屬層周邊下太少Z引而k成球底 間剝落脫離之現象;再者更下 /掩之壓本/ 广環了烯層(B c B 之苯併環丁烯層,而進一牛曰故掩麼球底金屬層中央4 壞。 V擠壓保護層而造成保護Page 7 1300616 - Case No. 921 871 Description of Invention (3) 106c is used to increase the adhesion of the ball-bottom metal layer 106 to the solder bumps 108. Common materials include metals such as copper. It is worth noting that due to the better soldering characteristics of tin-tin alloys, the material of solder bumps 8 is often tin-alloyed, but lead has a great influence on the natural environment, so lead-free solder (lead free s〇ider) The birth of lead-containing or lead-free solders consists of tin. Referring to FIG. 1 again, during the reflow process, the solder bumps 108 are often caused by the cohesive force of the solder bumps 1 〇 8 so that the spheroidized solder bumps 08 pull the periphery of the sphere metal layer 106 upward. The benzocyclobutene layer (BCB Uyer) 103 and the wafer soldering solder bumps 108 are pressed under the spherical metal layer. However, since the benzocyclobutene layer 丨〇3 is larger (in other words, it is harder), it often causes the #=pressure benzocyclobutene layer m under the protective layer ι〇2 two of it Squeeze and rupture. Furthermore, it also causes a phenomenon in which the benzocyclobutene layer (10) i ay er ) 1 〇 3 is stripped and detached below the periphery of the metal layer G6. [Invention] The structure of the material bump layer is divided into the lower layer. In view of this, the object of the present invention is Φ ^ ^ ^ ', which is caused by the spheroidization of a flip chip wafer resulting in ": In the case of Reflow, due to the under-conformation, the periphery of the metal layer of the ball and the periphery of the metal layer at the bottom of the ball are too small to lead to the phenomenon of peeling off and separating between the bottom and the bottom of the ball; This / wide ring of olefin layer (B c B benzocyclobutene layer, and into a calf, so the bottom of the bottom of the metal layer 4 is bad. V squeeze the protective layer to protect

第8頁 1300616 年月曰 修正 17871 五、發明說明(4) 緣疋,為達上述目的,本發明係提出一 數個晶片鲜塾、一保護層、一聚亞=、、、口 衣丁烯層、複數個球底金屬層及複數個銲料凸 鬼。/、中,該保護層係形成於覆晶晶片之主動表面上並義 銲塾’而聚亞醯胺層及苯併環丁烯層係依: 形成於保濩層上並同時暴露出該等銲墊。再者, 層係形成於銲塾上,以作為銲料凸塊與銲塾間之過渡層 (phase layer) ° θ 數個發明更提出一種覆晶晶片結構’其係包含複 2料凸塊。其中’該晶片保護層係形成於覆 上並暴露出該等晶片銲墊,巾聚亞醯胺 ^係直接形成於保護層上並同時暴露出料晶片料。再 ^球底金屬層係形成於晶片鲜塾上’以作為薛料凸塊盥 曰曰片銲墊間之過渡層。 /、 伴幾亩:亞!胺層係形成於笨併環丁烯層與晶片 層之間或直接形成於球底金屬層與晶片保護層之間, 声:層之彈性模數係小於笨併環丁稀層及保護 :亦即水亞駄妝層係由較為柔軟之材質所組成,故可作 2保護層承受外力作用之緩衝介面層’以防止銲料凸塊球 而牽引球底金屬層之周邊’造成球底金屬層中 周 邊以外部分)下方之保護層被擠壓而破壞變形。、° (四)、【實施方式】Page 8 1300616 曰 曰 Amendment 17871 V. OBJECT DESCRIPTION OF THE INVENTION (4) For the above purposes, the present invention proposes a number of wafers of fresh enamel, a protective layer, a poly-Asia, and Layer, a plurality of ball bottom metal layers and a plurality of solder bumps. And, the protective layer is formed on the active surface of the flip chip and soldered to the 'polyimide layer and the benzocyclobutene layer: formed on the protective layer and simultaneously exposed the solder pad. Further, a layer is formed on the solder tab to provide a flip chip structure as a phase layer of the solder bump and the solder bump. The system includes a bump bump. Wherein the wafer protective layer is formed on the cover and exposes the wafer pads, and the polyimide is formed directly on the protective layer while exposing the discharged wafer. Further, the bottom metal layer is formed on the wafer slab as a transition layer between the solder bumps and the solder pads. /, with a few acres: Ya! The amine layer is formed between the stupid and cyclobutene layer and the wafer layer or directly between the bottom metal layer and the wafer protective layer, and the acoustic modulus of the layer is less than the stupid and thin layer and protection: That is, the water-Asian makeup layer is composed of a relatively soft material, so it can be used as a buffer layer for the external protective layer of the protective layer to prevent the solder bump ball from pulling the periphery of the metal layer of the ball. The protective layer below the peripheral portion is squeezed to break the deformation. , ° (four), [implementation]

13006161300616

睛參考圖2,其顯示根據本發明之較 片結構的剖面示意圖。 只也例之覆晶晶 MM 92117871 五、發明說明(5) 晶晶片結構。 谨一 :3地請參考圖2 ’係表示覆晶晶片結構200之邻八社 構不思圖。覆晶晶片結構20〇係具有 j 〇〇 ^刀結 介雷屉f入、第一"電層(介電保護層)205、第- 2 8 2電保護層)2°6、-球底金屬層m及銲料凸塊 208。其中,保護層2〇2係配置於主動 +凸免 ^ =結構m之主動表面201並暴露出晶片銲墊=保J 入’/形成第-介電層(介電保護層)205及第二介電声 層i 20 6於保護層202上,並暴露出晶片銲㈣曰4。 第二二入一介電層(介電保護層)205之彈性模數係小於 =拖 護層)2°6之彈性模數及保護層2°2之彈 入雷居/ί二之,第一介電層(介電保護層)205係由比第二 =層(介電保護層)2 06及保護層2〇2較為柔軟之材質所组 。:般而言’保護層可為氧化矽(siHc〇n ο—。' 鼠化石夕(silicori nitride)、磷矽玻璃 (ph〇Sph〇Silicate glass,PSG )等材質。較佳地,♦第 ^介,層(介電保護層)20 6為較堅硬之苯併環丁烯層所組成 日寸,第一介電層(介電保護層)2〇5可由聚亞醯胺所組成。 另外’再形成一球底金屬層207於晶片銲墊204及第二 介電層(介電保護層)206上,且球底金屬層2〇7主要由黏著 層207=、阻障層2〇7b、潤濕層207c所組成。當晶片銲墊2〇4 為鋁墊時,黏著層/阻障層/潤濕層較佳地可為鋁/鎳釩合 金/銅三層i構。而當晶片銲墊2〇4為銅銲墊時,黏著層/阻Referring to Figure 2, there is shown a cross-sectional view of a comparative structure in accordance with the present invention. Only the case of flip-chip MM 92117871 V. Description of the invention (5) Crystal wafer structure. I would like to: 3, please refer to Figure 2, which shows the neighboring eight communities of the flip chip structure 200. The flip chip structure 20 has a j 〇〇 ^ knife junction jie Lei drawer f input, a first " electrical layer (dielectric protective layer) 205, a 208 electric protective layer) 2 ° 6, - ball bottom Metal layer m and solder bumps 208. Wherein, the protective layer 2〇2 is disposed on the active surface 201 of the active+convex no-structure m and exposes the wafer pad=protecting into/forming the first dielectric layer (dielectric protective layer) 205 and the second The dielectric acoustic layer i 620 is on the protective layer 202 and exposes the wafer solder (four) 曰4. The second two-in-one dielectric layer (dielectric protective layer) 205 has a modulus of elasticity less than = drag layer) 2 ° 6 elastic modulus and protective layer 2 ° 2 of the bomb into the Lei Ju / ί 二之, A dielectric layer (dielectric protective layer) 205 is composed of a material that is softer than the second layer (dielectric protective layer) 206 and the protective layer 2〇2. In general, the protective layer may be a material such as cerium oxide (siHc〇n ο-. 'silicori nitride, ph〇Sph〇Silicate glass (PSG). Preferably, ♦ ^ The layer (dielectric protective layer) 20 6 is composed of a harder benzocyclobutene layer, and the first dielectric layer (dielectric protective layer) 2〇5 may be composed of polyamidene. Forming a ball bottom metal layer 207 on the wafer pad 204 and the second dielectric layer (dielectric protective layer) 206, and the ball bottom metal layer 2〇7 is mainly composed of an adhesive layer 207=, a barrier layer 2〇7b, The wetted layer 207c is composed of. When the wafer pad 2〇4 is an aluminum pad, the adhesive layer/barrier layer/wetting layer can preferably be aluminum/nickel-vanadium alloy/copper three-layer structure. Adhesive layer/resistance when pad 2〇4 is a copper pad

第10頁 1300616Page 10 1300616

障層/潤濕層較佳地可為鈦/鎳釩合金/銅三層结構 f黏著層、阻障層、、潤濕層是由何材料所組成:隹不論 吕’黏著層之材質係選自於由鈦、鎢、鈦鎢合金、^而 ::士族群中之一種材質;阻障層之材質係選自於由鎳、、呂 釩5金、鎳銅合金及鎳鈦合金所組成族群中之一種材μ鎳 :濕層之材質係選自於銅、鉻銅及銅合金所組成族群 中,黏著層、阻障層及潤濕層可利用濺鍍之方式^ 方式形成之。 人电鱺之 再者,於潤濕層2 0 7c上設置一銲料凸塊2 〇 8,以作 =晶片結構與基板(未繪示於圖中)覆晶接合時之連接元、 值得注意的是,球底金屬層2〇7亦可於第二介電芦(人 電保護層)206上延伸形成一線路重分佈層,並於線路3重& t層上覆蓋另一介電層(介電保護層)以暴露出部分線路= 分佈層作為凸塊銲墊之用。之後,再將銲料凸塊形成於凸 塊鲜塾上。 承上所述,由於銲料凸塊2〇8迴銲球化時,球底金屬層 2〇7之周邊會文銲料凸塊2〇8之牽引而擠壓球底金屬層go?中 央邛分(即周邊以外部分)下方之第一介電層(介電保護層) 20 5及第二介電層(介電保護層)2〇6 ;惟第二士介電層(介電 保護層)20互各係由彈性模數較低之材質所組成,故第二士介 $層(介電保護層)2〇旦务可吸收球底金屬層207被牽引而對 $三一介電層(介電保護層)2〇旦·子所施加之壓應力,以作為 第二一介電層(介電保護層)2 0企卜及晶片保護層2 〇 2之緩衝界 面’而防止保護層2 0 2之破壞及避免造成球底金屬層207之The barrier layer/wetting layer may preferably be a titanium/nickel-vanadium alloy/copper three-layer structure f-adhesive layer, a barrier layer, and a material of the wetting layer: 隹 regardless of the material of the adhesive layer From titanium, tungsten, titanium-tungsten alloy, ^:: a material in the group of people; the material of the barrier layer is selected from the group consisting of nickel, Lu vanadium 5 gold, nickel-copper alloy and nickel-titanium alloy One of the materials: Nickel: The material of the wet layer is selected from the group consisting of copper, chrome copper and copper alloy, and the adhesive layer, the barrier layer and the wetting layer can be formed by sputtering. In addition, a solder bump 2 〇8 is disposed on the wetting layer 2 0 7c as a connecting element when the wafer structure is bonded to the substrate (not shown), which is noteworthy. The bottom metal layer 2〇7 may also extend over the second dielectric reed (human protective layer) 206 to form a line redistribution layer, and over the line 3 heavy & t layer over the other dielectric layer ( The dielectric protective layer) is used to expose part of the line = distribution layer as a bump pad. Thereafter, solder bumps are formed on the bumps. As described above, since the solder bumps 2〇8 are soldered and spheroidized, the periphery of the ball metal layer 2〇7 is pulled by the solder bumps 2〇8 to press the bottom metal layer go? That is, the first dielectric layer (dielectric protective layer) 20 5 and the second dielectric layer (dielectric protective layer) 2 〇 6 under the peripheral portion; only the second dielectric layer (dielectric protective layer) 20 The mutual system is composed of a material with a low modulus of elasticity, so the second layer (dielectric protective layer) 2 can absorb the bottom metal layer 207 and be pulled to the $31 dielectric layer. The electrical protective layer) is applied to the compressive stress applied by the sub-layer as the second dielectric layer (dielectric protective layer) 20 and the buffer interface of the wafer protective layer 2 〇 2 to prevent the protective layer 2 0 2 damage and avoid causing the bottom metal layer 207

1300616 修正 案號 92117871 五、發明說明(7) 周邊與球底金屬層207周邊下方之第二介電層(介 ^ ^ ^ ^ ^ ^ ^ ^ t ,a ,a '; 之汉计,k雨覆晶晶片結構之使用壽命。 接著,請參考圖3,其顯示根據本發明之另一較 例之覆晶晶片結構的剖面示意圖 只& =樣地請參考圖3,係表示覆晶晶片結構3〇〇之部分社 ί:圖入。Λ晶ί片結構3GG係具有—主動表面3Gi、保ΐ 層302、),電層(介電保護層)3〇3、#塾3〇4、一球底 銲料凸塊3〇8。其中’保護廣3。2係配置於主動表面曰 r塾30’4用ϋ護覆晶晶片結構州之主動表面301並暴露出 形成—介電層(介電保護層)3G3於保護層 302上’並暴鉻出晶片銲塾 异302其二ΛΛ層(介電保護層)3°3之彈性模數係小於保護 言之,介電層(介電保護層)3°3係由比 $濩層302較為“人之材質所組成的。較佳地,介 電保護層)3 0 3可由聚亞醯胺所組成。 9 m及另二金屬層306係形成於介電層(介電保護層) 及鈈墊304上,且球底金屬層306主要由黏著声3〇6a I1早層3 0 6 b、潤濕層3 〇 6 C所組成。合晶片锃埶q二 牯机-紅/ ^ 取 田日日月鋅墊304為鋁銲墊 二:者!曰阻广//潤濕層較佳地可為銘/錄叙合金/銅三 曰、、,口構而曰曰片备銲墊304為銅銲墊時,黏著層/阻 /潤 濕層較佳地可為鈦/鎳飢合金/ _二# β曰+ 声、阻暗@9 ,鱼/钔一層釔構。惟不論其黏著 曰F Ρ早層、潤濕層疋由何材料所組成,一般而士,黏著 ^ ^ ^ ^ „ 鎢鈦鎢合金、鉻、鋁所組成族1300616 Amendment No. 92117871 V. Description of the invention (7) The second dielectric layer around the periphery of the perimeter and the bottom metal layer 207 (in the case of ^ ^ ^ ^ ^ ^ ^ t , a , a '; The service life of the flip chip structure. Next, please refer to FIG. 3, which shows a cross-sectional view of a flip chip structure according to another comparative example of the present invention. Referring to FIG. 3, the flip chip structure is shown. 3〇〇之社 ί:图入.Λ晶ί片结构3GG series has—active surface 3Gi, protective layer 302,), electrical layer (dielectric protective layer) 3〇3, #塾3〇4, one Ball bottom solder bumps 3〇8. The 'protective wide 3. 2 series is disposed on the active surface 曰r塾 30'4 for protecting the active surface 301 of the flip chip structure state and exposing the formation-dielectric layer (dielectric protective layer) 3G3 on the protective layer 302 'And violent chrome out of the wafer soldering different 302 its second layer (dielectric protective layer) 3 ° 3 elastic modulus is less than the protection, the dielectric layer (dielectric protective layer) 3 ° 3 system by the ratio of $ 濩 layer 302 is composed of a "man's material. Preferably, a dielectric protective layer" 3 0 3 may be composed of polyamidamine. 9 m and the other two metal layers 306 are formed on the dielectric layer (dielectric protective layer) And the mat 304, and the bottom metal layer 306 is mainly composed of an adhesive layer 3〇6a I1 early layer 3 0 6 b, a wetting layer 3 〇6 C. The wafer 锃埶q 牯 - - red / ^ Tianri Riyue Zinc Pad 304 is an aluminum pad 2: Yes! 曰 广 / / / Wetting layer is better can be Ming / Recording alloy / copper three 曰,,,,,,,,,,,,,,,,,,,, In the case of a copper pad, the adhesion layer/resistance/wetting layer may preferably be titanium/nickel alloy/ _2#β曰+ sound, darkening @9, fish/钔 layer, but regardless of its adhesion. F Ρ Early layer, wet layer 疋 composed of what material Generally disabilities, adhesive ^^^^ "titanium-tungsten alloy, tungsten, chromium, aluminum group consisting of

i中之-種材負;阻障層之材質係選自於由鎳、鎳釩合金i - the material is negative; the material of the barrier layer is selected from nickel, nickel vanadium alloy

第12頁 1300616Page 12 1300616

鎳銅合金及鎳鈦合金所組成 材質係選自於銅、鉻銅及銅 層、阻障層及潤濕層可利用 之0 族群中之—種材質;而潤濕層之 合金所組成族群。其中,黏著 錢錄之方式或電鍍之方式形成 曰曰:Ϊ ’於'潤濕層306c上設置一銲料凸塊308,以作為覆 曰日日日片結構與基板(未繪示於圖中)覆晶接合 連接元 件。 嗜注意的是,球底金屬層30 6亦可於介電層(介電保 凌層)j03上延伸形成一線路重分佈層,並於線路重分佈層 上覆盍另一介電層(介電保護層)以暴露出部分線路重分佈 層作為凸塊銲墊之用。之後,再將銲料凸塊形成於凸塊銲 承上所述,由於銲料凸塊308迴銲球化時,球底金屬層 306之周邊會受銲料凸塊308之牽引而擠壓球底金屬層3〇6十 央部分(即周邊以外部分)下方之介電層(介 惟介電層(介電保護層)3 0 3係由彈性模數較低之材^所組, 成,故介電層(介電保護層)303可吸收球底金屬層3〇6被牵 引而對保護層302所施加之壓應力,以作為介電層(介電保 遵層)3 0 3及保護層3 0 2之緩衝界面,防止保護層3 〇 2之破壞 及造成球底金屬層306之周邊與球底金屬層3Q6周邊下方之 介電層(介電保護層)303間剝落脫離之現象。故藉由上述之 覆晶晶片結構設計,可提高覆晶晶片結構之使用胃壽命。 於本實施例之詳細說明中所提出之具體的實:例僅為 了易於說明本發明之技術内容,而並非將本發明狹義地限 制於該實施例,因此,在不超出本發明之精神及以下申請 1300616The material consisting of nickel-copper alloy and nickel-titanium alloy is selected from the group consisting of copper, chrome-copper and copper layers, barrier layers and wetting layers, and the alloy of the wetting layer. Wherein, the method of bonding the money or the way of electroplating forms a solder bump 308 on the wetting layer 306c as a covering day and day structure and substrate (not shown in the figure) Flip bonded joint elements. It is noted that the bottom metal layer 30 6 may also extend over the dielectric layer (dielectric security layer) j03 to form a line redistribution layer, and over the line redistribution layer to cover another dielectric layer. The electrical protective layer) is used to expose a portion of the wiring redistribution layer as a bump pad. Thereafter, the solder bumps are formed on the bump pads. When the solder bumps 308 are re-sphered, the periphery of the ball metal layer 306 is pulled by the solder bumps 308 to squeeze the ball metal layer. The dielectric layer below the 3 〇6 ten central part (ie, the part outside the perimeter) (the dielectric layer (dielectric protective layer) 3 0 3 is composed of a material with a lower modulus of elasticity, so the dielectric The layer (dielectric protective layer) 303 can absorb the compressive stress applied to the protective layer 302 by the under-ball metal layer 3〇6 to serve as a dielectric layer (dielectric layer) 3 0 3 and a protective layer 3 0 . The buffer interface of 2 prevents the destruction of the protective layer 3 〇 2 and causes the peeling and detachment between the periphery of the bottom metal layer 306 and the dielectric layer (dielectric protective layer) 303 under the periphery of the ball metal layer 3Q6. The above-mentioned flip chip structure design can improve the use of the stomach life of the flip chip structure. The specific examples set forth in the detailed description of the embodiment are merely for ease of description of the technical contents of the present invention, and are not intended to be the present invention. Narrowly limited to this embodiment, therefore, without departing from the spirit of the invention The following application 1300616

1300616 _案號 92117871_年 月_g_修正_ 圖式簡單說明 (五)、【圖式之簡單說明】 圖1為習知之覆晶晶片結構剖面示意圖。 圖2為依照本發明較佳實施例之覆晶晶片結構剖面示意 圖。 圖3為依照本發明另一較佳實施例之覆晶晶片結構剖面 示意圖。 元件符號說明: 10 0· 覆晶晶片結構 101 : 主動表面 102 : 保護層 103 : 苯併環丁烯層 104 : 晶片銲墊 1 0 6 : 球底金屬層 106a: 黏著層 106b: 阻障層 106c: 潤濕層 108 : 銲料凸塊 2 0 0· 覆晶晶片結構 201 : 主動表面 202 : 保護層 204 : 晶片銲墊 205: 第一介電層(介電保護層)(聚亞醯胺層) 2 0 6: 第二介電層(介電保護層)(苯併環丁烯層)1300616 _ Case No. 92117871_Year _g_Revision _ Brief description of the diagram (5), [Simplified description of the drawing] FIG. 1 is a schematic cross-sectional view of a conventional flip chip structure. Figure 2 is a cross-sectional view showing the structure of a flip chip in accordance with a preferred embodiment of the present invention. 3 is a cross-sectional view showing a structure of a flip chip according to another preferred embodiment of the present invention. Description of the component symbols: 10 0· flip chip structure 101: active surface 102: protective layer 103: benzocyclobutene layer 104: wafer pad 1 0 6 : ball metal layer 106a: adhesive layer 106b: barrier layer 106c : Wetting layer 108 : solder bump 2 0 0 · flip chip structure 201 : active surface 202 : protective layer 204 : wafer pad 205 : first dielectric layer (dielectric protective layer) (polyimine layer) 2 0 6: second dielectric layer (dielectric protective layer) (benzocyclobutene layer)

第15頁 1300616Page 15 1300616

第16頁 案號 92117871 年月日_修正 圖式簡單說明 207 : 球 底 金屬層 207a : 黏 著 層 20 7b : 阻 障 層 20 7c : 潤 濕 層 208 銲 料 凸塊 300 覆 晶 晶片結構 301 主 動 表面 3 02 保 護 層 303 介 電 層(介電保護層)(聚亞醯胺層) 304 銲 墊 306 球 底 金屬層 3 0 6a : 黏 著 層 3 0 6b : 阻 障 層 30 6c : 潤 濕 層 308 鲜 料 凸塊Page 16 Case No. 92117871 Date _ Corrective Drawing Simple Description 207: Ball Metal Layer 207a: Adhesive Layer 20 7b : Barrier Layer 20 7c : Wetting Layer 208 Solder Bump 300 Flip Chip Structure 301 Active Surface 3 02 Protective layer 303 Dielectric layer (dielectric protective layer) (polyimide layer) 304 Pad 306 Bottom metal layer 3 0 6a : Adhesive layer 3 0 6b : Barrier layer 30 6c : Wetting layer 308 Fresh material Bump

Claims (1)

1300616 修正 笔號 92117871 六、申請專利範圍 1 · 一種覆晶晶片結構,包含: 一主動表面; 複數個銲墊,其係設置於該主動表面上; 一保護層,其係設置於該主動表面上且暴露出該等銲墊; 一聚亞醯胺層(polyimide,PI),其係形成於該保護層上且 暴露出該等銲墊; 一苯併環丁烯層^⑽別”^讣討⑽^队…’其係形成於該 聚亞醯胺層上且暴露出該等銲墊;及 X 複數個球底金屬層,其係形成於該苯併環丁烯層上且分別 設置於該等晶片銲墊上。 個^ U利:圍第1項所述之覆晶晶片結構,更包含複數 個紅枓凸塊,其係分別形成於該等球底金屬層上。 3層範,第1項所述之覆晶晶片結構,④中該保護 曰 貝,、匕1含氮化物(nitride)。 芦之材二i 範圍第1項所述之覆晶晶片結構,其中該保護 貝’、匕含氮化石夕(silicon nitride)。 厣之材二,利範圍第1項所述之覆晶晶片結構,其中該保護 p曰SG)。貝糸包含磷矽玻璃(phosphosilicate glass,1300616 Correction No. 92117871 VI. Patent Application No. 1 · A flip chip structure comprising: an active surface; a plurality of pads disposed on the active surface; a protective layer disposed on the active surface And exposing the solder pads; a polyimide layer (polyimide, PI) formed on the protective layer and exposing the pads; a benzocyclobutene layer (10) (10) ^ team ... ' is formed on the polyimide layer and exposes the pads; and X plurality of ball-bottom metal layers are formed on the benzocyclobutene layer and are respectively disposed on the The wafer flip-chip structure described in the above item 1 further comprises a plurality of red germanium bumps respectively formed on the metal layer of the ball. The flip chip structure described in the above, wherein the protective mussels, and the niobium 1 contain a nitride. The recrystallized wafer structure according to the above item 1, wherein the protective wafer ', 匕Containing silicon nitride. 厣材材2, the scope of the first paragraph Polycrystalline wafer structure, wherein the said protective p SG). Mi shell comprises phosphorus silicon glass (phosphosilicate glass, 第17頁 1300616 _案號92117871_年月曰 修正_ 六、申請專利範圍 6 ·如申請專利範圍第1項所述之覆晶晶片結構,其中該保護· 層之材質係包含氧化石夕(silicon oxide)。 7·如申請專利範圍第1項所述之覆晶晶片結構,其中該球底 金屬層之材質係選自於由鈦、鎢、鈦鎢合金、鉻、鋁、 鎳、鎳飢合金、鎳銅合金、鎳鈦合金、銅、銅鉻合金所組 成族群中之一種材質。 8 ·如申請專利範圍第1項所述之覆晶晶片結構,其中該球底 金屬層之一係為一線路重分佈層,且更包含一介電層形成 於該線路重分佈層上並暴露出該線路重分佈層以形成一線 路重分佈銲墊。 9 ·如申請專利範圍第8項所述之覆晶晶片結構,更形成一銲 料凸塊於該線路重分佈銲墊上。 1 0.如申請專利範圍第1項所述之覆晶晶片結構,其中該球 底金屬層係為铭/鎳鈒合金/銅三層結構。 11.如申請專利範圍第1項所述之覆晶晶片結構,其中該球 底金屬層係為鈦/鎳釩合金/銅三層結構。 1 2.如申請專利範圍第1項所述之覆晶晶片結構,其中該球 底金屬層係為鈦/銅合金兩層結構。Page 17 1300616 _ Case No. 92117871 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Oxide). The flip chip structure as described in claim 1, wherein the material of the bottom metal layer is selected from the group consisting of titanium, tungsten, titanium tungsten alloy, chromium, aluminum, nickel, nickel alloy, nickel copper A material consisting of alloys, nickel-titanium alloys, copper, and copper-chromium alloys. The flip chip structure as described in claim 1, wherein one of the ball bottom metal layers is a line redistribution layer, and further comprising a dielectric layer formed on the line redistribution layer and exposed The line redistribution layer is formed to form a line redistribution pad. 9. The flip chip structure as described in claim 8 further forms a solder bump on the line redistribution pad. The flip-chip structure as described in claim 1, wherein the spherical metal layer is a three-layer structure of a nickel/niobium alloy/copper. 11. The flip chip structure of claim 1, wherein the spherical metal layer is a titanium/nickel vanadium alloy/copper three-layer structure. The flip chip structure as described in claim 1, wherein the spherical metal layer is a two-layer structure of titanium/copper alloy. 第18頁 1300616 案號 六、申請專利範圍 92117871Page 18 1300616 Case No. VI. Patent Application Range 92117871 1 3 · —種覆晶晶片結構,包含·· 一主動表面; 複數個銲墊,其係設置於該主動表面上; 痒鲜塾; 出該等銲 保遵層’其係設置於該主動表面上且暴露出該 一第一介電層,其係形成於該保護層上且暴露 墊; 一第二介電層,其係形成於第一介電層上並暴露出該等 塾’且該第二介電層之彈性模數係大於該第一、 彈性模數;及 )丨電層之 複數個球底金屬層,其係形成於該第二介電層上八 14·如申請專利範圍第i 3項所述之覆晶晶片結構,其 遵層之彈性模數係大於該第一介電層之彈性模數。μ呆 1 5 ·如申請專利範圍第1 3項所述之覆晶晶片結構,1 φ # 一介電層之材質係為聚亞醯胺層。 八以弟 16·如申請專利範圍第13項所述之覆晶晶片結構,爱 二介電層之材質係為苯併環丁烯層。 〃 ^第 17 ·如申請專利範圍第1 3項所述之覆晶晶片結構,更句人 數個銲料凸塊,其係分別形成於該等球底金屬層上。各不1 3 · a flip chip structure comprising: an active surface; a plurality of pads disposed on the active surface; itch squeezing; the soldering layer is disposed on the active surface And exposing the first dielectric layer on the protective layer and exposing the pad; a second dielectric layer formed on the first dielectric layer and exposing the 塾' and the The second dielectric layer has a modulus of elasticity greater than the first, elastic modulus; and the plurality of ball-bottom metal layers of the tantalum layer are formed on the second dielectric layer. The flip chip structure of item i3, wherein the elastic modulus of the layer is greater than the modulus of elasticity of the first dielectric layer. μ stay 1 5 · The flip chip structure described in claim 13 of the patent application, the material of the 1 φ # dielectric layer is a polyimide layer.八以弟16· As claimed in the thirteenth wafer structure described in claim 13, the material of the second dielectric layer is a benzocyclobutene layer. 〃 ^17. The flip-chip structure as described in claim 13 of the patent application, further comprising a plurality of solder bumps respectively formed on the ball-bottom metal layers. No 第19頁 13 〇〇616 案號 92]178Ή 六、申請專利範圍 月 曰 修正 1 8 ·如申請專利範圍第1 3項所述之覆晶晶片結構,其中該保 遵層之材質係包含氮化物(nitride)。 1 9 ·如申請專利範圍第i 3項所述之覆晶晶片結構,其中該保 濩層之材質係包含氮化矽(silicon nitride )。 2 〇.如申請專利範圍第1 3項所述之覆晶晶片結構’其中該保 瘦層之材質係包含磷矽玻璃(phosphosilicate glass, PSG )。 2 1 ·如申請專利範圍第丨3項所述之覆晶晶片結構,其中該保 瘦層之材質係包含氧化石夕(si 1 icon oxide )。 2 2 ·如申請專利範圍第j 3項所述之覆晶晶片結構,其中該球 底金屬層之材質係選自於由鈦、鎢、鈦鎢合金、鉻、鋁、 鎳、鎳釩合金、鎳銅合金、鎳鈦合金、銅、銅鉻合金所組 成族群中之一種材質。 2 3 ·如申請專利範圍第1 3項所述之覆晶晶片結構,其中該球 底金屬層之一係為一線路重分佈層,且更包含一介電層形 成於該線路重分佈層上並暴露出該線路重分佈層以形成一 線路重分佈銲墊。Page 19 13 〇〇 616 Case No. 92] 178 Ή VI. Patent Application Scope Amendment 1 8 · The flip chip structure described in claim 13 of the patent application, wherein the material of the compliant layer contains nitride (nitride). The flip chip structure as described in claim i, wherein the material of the protective layer comprises silicon nitride. 2. The flip chip structure as described in claim 13 wherein the material of the thin layer comprises phosphosilicate glass (PSG). 2 1. The flip chip structure as described in claim 3, wherein the material of the thin layer comprises a Si 1 icon oxide. 2. The flip chip structure as described in claim j3, wherein the material of the bottom metal layer is selected from the group consisting of titanium, tungsten, titanium tungsten alloy, chromium, aluminum, nickel, nickel vanadium alloy, A material of a group consisting of nickel-copper alloy, nickel-titanium alloy, copper, and copper-chromium alloy. The flip chip structure as described in claim 13 wherein one of the ball bottom metal layers is a line redistribution layer, and further comprising a dielectric layer formed on the line redistribution layer The line redistribution layer is exposed to form a line redistribution pad. 第20頁 13〇〇616 车月曰 修正 ^92117871 /、'申請專利範圍 2 4 申請專利範圍第2 3項所述之覆晶晶片結構,更形成一 干料凸塊於該線路重分佈銲墊上。 2 5 κ 申請專利範圍第1 3項所述之覆晶晶片結構,其中該球 一戍屬層係為紹/鎳飢合金/銅三層結構。 2 g 广·如申請專利範圍第丨3項所述之覆晶晶片結構,其中該球 &金屬層係為鈦/鎳釩合金/銅三層結構。 2 7 广·如申請專利範圍第1 3項所述之覆晶晶片結構,其中該球 &金屬層係為鈦/銅合金兩層結構。 2 g •一種覆晶晶片結構,包含: =主動表面; '复數個銲塾,其係設置於該主動表面上; —保護層’其係設置於該主動表面上且暴露出該等銲塾; 一介電層,其係形成於該保護層上且暴露出該等銲墊,且 °玄電層之彈性模數係小於该晶片保護層之彈性模數· 及 、 複數個球底金屬層,其係形成於該介電層上且分別設於 5玄專晶片鮮塾上。 29.如申請專利範圍第28項所述之覆晶晶片結構,其中該介 電層之材質係為聚亞醯胺層。 〃 ^ 第21頁 1300616 六、申請專利範圍 曰 修」 3 〇 ·如申請專利範圍第2 8項所述之覆晶晶片結構,更包含複 數個銲料凸塊,其係分別形成於該等球底金屬層上。 3 1 ·如申請專利範圍第28項所述之覆晶晶片結構,其中該保 護層之材質係包含氮化物(nitride)。 32·如申請專利範圍第28項所述之覆晶晶片結構,其中該保 °蔓層之材質係包含氮化石夕(silicon nitride)。 ·如申請專利範圍第2 8項所述之覆晶晶片結構,其中該保 °蔓層之材質係包含填石夕玻璃(phosphosilicate glass, PSG ) 〇 3/·如申請專利範圍第28項所述之覆晶晶片結構,其中該保 °蔓層之材質係包含氧化石夕(silicon oxide)。 35·如申請專利範圍第28項所述之覆晶晶片結構,其中該球 氏金屬層之材質係選自於由欽、鶴、欽鶴合金、絡、銘、 _、鎳飢合金、鎳銅合金、鎳鈦合金、銅、銅鉻合金所組 成族群中之一種材質。 36·如申請專利範圍第28項所述之覆晶晶片結構,其中該球 底金屬層之一係為一線路重分佈層,且更包含一介電層形 第22頁 1300616 _案號92117871_年月曰 修正_ 六、申請專利範圍 成於該線路重分佈層上並暴露出該線路重分佈層以形成一^ 線路重分佈銲墊。 3 7 ·如申請專利範圍第3 6項所述之覆晶晶片結構,更形成一 銲料凸塊於該線路重分佈銲墊上。 3 8.如申請專利範圍第28項所述之覆晶晶片結構,其中該球 底金屬層係為铭/鎳飢合金/銅三層結構。 3 9·如申請專利範圍第28項所述之覆晶晶片結構,其中該球 底金屬層係為鈦/鎳鈒合金/銅三層結構。 4 0.如申請專利範圍第28項所述之覆晶晶片結構,其中該球 底金屬層係為鈦/銅合金兩層結構。Page 20 13〇〇616 车月曰 Amendment ^92117871 /, 'Application for patent scope 2 4 The patent application of the flip chip structure described in item 23, further forms a dry bump on the line redistribution pad. 2 5 κ The flip chip structure described in claim 13 wherein the ball layer is a three-layer structure of a smelting/nickel alloy/copper. 2 g 广 · The flip chip structure as described in claim 3, wherein the ball & metal layer is a titanium/nickel vanadium alloy/copper three-layer structure. The crystal chip structure described in claim 13 wherein the ball & metal layer is a two-layer structure of titanium/copper alloy. 2 g • a flip chip structure comprising: an active surface; 'a plurality of solder bumps disposed on the active surface; a protective layer disposed on the active surface and exposing the solder bumps; a dielectric layer formed on the protective layer and exposing the pads, and the elastic modulus of the black layer is less than the elastic modulus of the protective layer of the wafer, and a plurality of spherical metal layers. The system is formed on the dielectric layer and is respectively disposed on the fresh enamel of the 5th. 29. The flip chip structure of claim 28, wherein the dielectric layer is made of a polyimide layer. 〃 ^ Page 21 1300616 VI. Application for Patent Scope Repairs 3 〇 · The flip chip structure described in claim 28, further comprising a plurality of solder bumps formed at the bottom of the sphere On the metal layer. The flip chip structure as described in claim 28, wherein the material of the protective layer comprises a nitride. 32. The flip chip structure of claim 28, wherein the material of the barrier layer comprises silicon nitride. The flip chip structure as described in claim 28, wherein the material of the vine layer comprises a phosphosilicate glass (PSG) 〇 3 / · as described in claim 28 The flip chip structure, wherein the material of the vine layer comprises a silicon oxide. 35. The flip-chip structure as described in claim 28, wherein the material of the spheroidal metal layer is selected from the group consisting of Qin, He, Qinhe alloy, Luo, Ming, _, nickel alloy, nickel copper A material consisting of alloys, nickel-titanium alloys, copper, and copper-chromium alloys. 36. The flip chip structure as described in claim 28, wherein one of the ball metal layers is a line redistribution layer and further comprises a dielectric layer type page 1300616 _ case number 92117871_ Amendment of the year _ _ _, the patent application scope is formed on the redistribution layer of the line and expose the line redistribution layer to form a line redistribution pad. 3 7 . The flip chip structure as described in claim 36, further forming a solder bump on the line redistribution pad. 3. The flip-chip structure as described in claim 28, wherein the spherical metal layer is a three-layer structure of indium/nickel alloy/copper. The flip-chip structure as described in claim 28, wherein the spherical metal layer is a titanium/nickel-niobium alloy/copper three-layer structure. The flip-chip structure as described in claim 28, wherein the spherical metal layer is a two-layer structure of titanium/copper alloy. 第23頁Page 23
TW092117871A 2003-06-30 2003-06-30 Flip chip structure TWI300616B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW092117871A TWI300616B (en) 2003-06-30 2003-06-30 Flip chip structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092117871A TWI300616B (en) 2003-06-30 2003-06-30 Flip chip structure

Publications (2)

Publication Number Publication Date
TW200501374A TW200501374A (en) 2005-01-01
TWI300616B true TWI300616B (en) 2008-09-01

Family

ID=45070010

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092117871A TWI300616B (en) 2003-06-30 2003-06-30 Flip chip structure

Country Status (1)

Country Link
TW (1) TWI300616B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI411079B (en) * 2010-04-16 2013-10-01 Taiwan Semiconductor Mfg Semiconductor die and method for forming a conductive feature

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI411079B (en) * 2010-04-16 2013-10-01 Taiwan Semiconductor Mfg Semiconductor die and method for forming a conductive feature
US8587119B2 (en) 2010-04-16 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive feature for semiconductor substrate and method of manufacture

Also Published As

Publication number Publication date
TW200501374A (en) 2005-01-01

Similar Documents

Publication Publication Date Title
US7253519B2 (en) Chip packaging structure having redistribution layer with recess
US8035226B1 (en) Wafer level package integrated circuit incorporating solder balls containing an organic plastic-core
US6787903B2 (en) Semiconductor device with under bump metallurgy and method for fabricating the same
US20080001288A1 (en) Semiconductor Device and Manufacturing Method Thereof, Semiconductor Package, and Electronic Apparatus
US20060286791A1 (en) Semiconductor wafer package and manufacturing method thereof
US7518241B2 (en) Wafer structure with a multi-layer barrier in an UBM layer network device with power supply
TWI261330B (en) Contact structure on chip and package thereof
US20090057892A1 (en) Electrode structure in semiconductor device and related technology
US20090160052A1 (en) Under bump metallurgy structure of semiconductor device package
US6864168B2 (en) Bump and fabricating process thereof
US6930389B2 (en) Under bump metallization structure of a semiconductor wafer
US20090091028A1 (en) Semiconductor device and method of bump formation
TW589727B (en) Bumping structure and fabrication process thereof
TWI300616B (en) Flip chip structure
US6891274B2 (en) Under-bump-metallurgy layer for improving adhesion
TW583759B (en) Under bump metallurgy and flip chip
US20070080453A1 (en) Semiconductor chip having a bump with conductive particles and method of manufacturing the same
TWI223883B (en) Under bump metallurgy structure
TWI237860B (en) Integrated chip structure for wire bonding and flip chip assembly package and fabrication process thereof
JP2008147367A (en) Semiconductor device and its manufacturing method
JPH09162240A (en) Semiconductor device
TWI305403B (en) Lead-free conductive jointing bump
TWI237369B (en) Bump structure
TWI252548B (en) Bumped wafer structure
TWI221323B (en) Bumping process

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent