TWI462248B - 半導體元件的製作方法 - Google Patents

半導體元件的製作方法 Download PDF

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Publication number
TWI462248B
TWI462248B TW100115563A TW100115563A TWI462248B TW I462248 B TWI462248 B TW I462248B TW 100115563 A TW100115563 A TW 100115563A TW 100115563 A TW100115563 A TW 100115563A TW I462248 B TWI462248 B TW I462248B
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TW
Taiwan
Prior art keywords
layer
metal
substrate
organic compound
semiconductor device
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TW100115563A
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English (en)
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TW201230271A (en
Inventor
Zheng-Yi Lim
yi wen Wu
Wen Hsiung Lu
Chih Wei Lin
Tzong Huann Yang
Hsiu Jen Lin
Ming Da Cheng
Chung Shi Liu
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Taiwan Semiconductor Mfg
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Publication of TW201230271A publication Critical patent/TW201230271A/zh
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Publication of TWI462248B publication Critical patent/TWI462248B/zh

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Description

半導體元件的製作方法
本發明有關於一種積體電路的製作方法，且特別是有關於一種金屬柱的製作方法。
覆晶接合技術係利用多個凸塊電性接觸於晶片的接墊與封裝基板之間。在結構上，凸塊結構實際上包含凸塊本身以及所謂的凸塊下金屬(under bump metallurgy，UBM)層，其中凸塊下金屬層位於凸塊與接墊之間。凸塊下金屬層通常包括在接墊上依序配置的一擴散阻障層(或是一黏著層)以及一晶種層。依據凸塊所使用的材料，可將凸塊分為焊料凸塊、金凸塊、銅柱凸塊、以及混合金屬凸塊。目前，銅柱凸塊技術已被提出。相較於使用焊料凸塊的電路，以銅柱凸塊連接封裝基板的電路具有較小的間距，且凸塊橋接(bridging)的可能性最低，並可減少電路的電容負載，且允許電子元件以較高的頻率運作。
然而，要將前述結構與製程應用於積體電路製造有其困難性。舉例來說，銅柱會氧化而導致電子元件與封裝基板之間接著性不佳。因此，亟需一種保護銅柱的方法。
本發明一實施例提供一種半導體元件的製作方法，包括提供一基板，基板具有一接墊；形成一保護層延伸於基板上並具有一位於接墊上的開口；形成一金屬柱於接墊與部分保護層上；形成一焊料層於金屬柱上；以及使金屬柱的多個側壁與一有機化合物反應，以形成有機化合物的一自組裝單層於金屬柱的側壁上。
本發明另一實施例提供一種半導體元件的製作方法，包括提供一基板，基板具有一接墊；形成一保護層延伸於基板上並具有一位於接墊上的開口；形成一金屬柱於接墊與部分保護層上；形成一焊料層於金屬柱上；以及使金屬柱的多個側壁與一有機化合物反應，以形成有機化合物的自組裝多層於金屬柱的側壁上。
為使本發明之上述目的、特徵和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下。
可以了解的是，下述內容將提供許多不同的實施例，或是例子，以實施不同實施例的不同的特徵。成分(或構件)與排列的特定例子如下所述以簡化本揭露書。當然，在此僅用以作為範例，並非用以限定本發明。舉例來說，當以下述及一第一部分形成於一第二部分之上或上時，可包括第一部分與第二部分是直接接觸地形成的實施例、以及間隔有其他部分於第一部分與第二部分之間的實施例，如此則第一部分可未與第二部分直接接觸。為簡化與清楚起見，各種結構可以不同的尺寸任意繪示。此外，本揭露書在不同實施例中可能使用重複的標號及/或標示。此重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。
請參照第1圖，其繪示本發明多個實施例之半導體元件的製作方法100的流程圖，其中半導體元件包括金屬柱。製作方法100的步驟102為提供一基板，其具有一接墊。製作方法100的步驟104為形成一保護層(passivation layer)，其延伸於基板上，並具有一位於接墊上的開口。製作方法100的步驟106為將一金屬柱形成於接墊與部分保護層上。製作方法100的步驟108為將一焊料層形成在金屬柱上。製作方法100的步驟110為使金屬柱的側壁與一有機化合物(organic compound)反應，以於金屬柱的側壁上形成一有機化合物的自組裝單層(self-assembled monolayer)。以下將介紹第1圖的製作方法的一實施例。
第2A-2H圖繪示一半導體元件200的一金屬柱220在第1圖的製作方法的各製程步驟的剖面圖。值得注意的是，第1圖的製作方法並未製作出一完整的半導體元件200。因此，可以了解的是，可以在第1圖的製作方法100之前、之時或之後提供另外的製程，並且，在此可能僅簡單描述一些其他的製程。再者，為可較佳地了解本發明的發明概念，可簡化第2A圖至第2H圖。舉例來說，雖然圖示繪示一半導體元件200的金屬柱220，可以了解的是，半導體元件200可能是一積體電路封裝的一部分，該積體電路封裝可更包括多個其他的元件，例如底膠(under-fill)、導線架(lead-frame)等。
請參照第2A圖，提供一基板202。提供基板202的步驟可更包括於部分基板202上製作一或多個接墊204。基板202可包括一矽基板。基板202的材質可包括矽鍺(silicon germanium)、砷化鎵、或是其他適合的半導體材料。此外，基板202可為一絕緣層上半導體(semiconductor on insulator)，例如絕緣層上矽(silicon on insulator，SOI)或是藍寶石上矽(silicon on sapphire)。在另一實施例中，基板202可包括一摻雜的磊晶層、一梯度半導體層、及/或可更包括一半導體層位於另一不同種類的半導體層上，例如一矽層位於一矽鍺層上。在其他實施例中，一化合物半導體基板202可包括一多層矽結構，或者是一矽基板可包括一多層化合物半導體結構。
基板202可更包括多個隔離結構(isolation feature，未繪示)，例如淺溝槽隔離(shallow trench isolation，STI)結構或是矽局部氧化(local oxidation of silicon，LOCOS)結構。隔離結構可定義並隔離各種微電子元件(未繪示)。
形成於基板202中的各種微電子元件的例子包括電晶體，例如p型通道/n型通道金屬氧化物半導體場效電晶體(pMOSFETs/nMOSFETs)、雙載子接面電晶體(bipolar junction transistors，BJTs)、高電壓電晶體、高頻率電晶體等；二極體；電阻器；電容；電感；保險絲；及/或其他適合的元件。可進行各種製程以形成各種微電子元件，前述製程包括沉積、微影、佈植(implantation)、蝕刻、退火、及/或其他適合的製程。微電子元件彼此互連以形成積體電路元件，例如一邏輯元件(logic device)、記憶體元件(例如靜態隨機存取記憶體，static random access memory，SRAM)、射頻(radio frequency，RF)元件、輸入/輸出(input/output)元件、系統整合晶片(system-on-chip，SoC)元件、前述之組合、及/或其他適合的元件類型。
基板202更包括位於積體電路元件上的層間介電(inter-layer dielectric，ILD)層、金屬間介電(inter-metal dielectric，IMD)層以及金屬化結構。金屬化結構中的金屬間介電層包括低介電常數的介電材料、未摻雜的矽酸鹽玻璃(un-doped silicate glass，USG)、摻雜氟的矽酸鹽玻璃(fluorine-doped silicate glass，FSG)、摻雜碳的矽酸鹽玻璃、氮化矽、氮氧化矽、或其他常用的材料低介電常數的材料的介電常數(k值)可約小於3.9，或是約小於2.3。金屬化結構中的金屬線的材質可為鋁、鋁合金、銅、銅合金、或是其他導電材料。本領域具有通常知識者當可了解金屬化結構的形成細節。
一接墊204為一頂金屬化層，其形成於一頂層之金屬間介電層203中，接墊204為一部分的導電佈線(conductive route)並具有一外露表面，如果需要的話，可對外露表面進行一平坦化製程(例如為化學機械研磨)處理。
適於用以形成接墊204的材料可例如包括，但不限於，鋁、鋁合金、銅、銅合金、或是其他導電材料。接墊204可用於接合製程中，以連接各晶片中的積體電路至外部結構。
之後，形成一保護層206，其延伸於基板202上，以及圖案化保護層206以於部分接墊204上形成一第一開口208，其暴露部分接墊204，以利於後續的金屬柱凸塊製程。
保護層206係由無機材料組成，無機材料包括未摻雜的矽酸鹽玻璃、氮化矽、氮氧化矽、氧化矽、或前述之組合。在一些替代實施例中，保護層包括一高分子層，例如環氧樹脂、聚亞醯胺、苯并環丁烯(benzocyclobutene，BCB)、聚苯噁唑(polybenzoxazole，PBO)、或其相似物，但亦可使用其他相對較軟的介電材料(常為有機材料)。在至少一實施例中，保護層206的形成方法可包括化學氣相沉積、高密度電漿化學氣相沉積(high density plasma CVD，HDP CVD)、低氣壓化學氣相沉積(subatmospheric CVD，SACVD)、物理氣相沉積、或是旋轉塗佈製程(spin-on process)。
請參照第2B圖，在保護層206中形成第一開口208之後，於接墊204與保護層206上形成一凸塊下金屬化(under-bump-metallurgy，UBM)層210。凸塊下金屬化層210包括適合的凸塊下金屬化材料，其構成一單層或是多層結構。在本實施例中，凸塊下金屬化層210包括一第一凸塊下金屬化次層212與一位於第一凸塊下金屬化次層212上的第二凸塊下金屬化次層214。
在本實施例中，第一凸塊下金屬化次層212形成於接墊204的外露部上，並延伸至部分的保護層206上。第一凸塊下金屬化次層212(亦可稱為擴散阻障層或是黏著層)的材質包括鈦、鉭、氮化鈦、氮化鉭、或其相似物，其形成方法包括物理氣相沉積或是濺鍍。可將第一凸塊下金屬化次層212沉積至一厚度，其約為500埃至1200埃。在至少一實施例中，第二凸塊下金屬化次層214(亦可稱為晶種層)的材質為銅，並可以物理氣相沉積法或是濺鍍法製得。在另一實施例中，第二凸塊下金屬化次層214的材質包括銅合金，其包括銀、鉻、鎳、錫、金、或前述之組合。第二凸塊下金屬化次層214沉積至一厚度，其約為2000埃至7000埃。
之後，在凸塊下金屬化層210上形成一感光層216。感光層216可為一乾膜或是一光阻膜，其厚度約為40微米至120微米。可以了解的是，在一些實施例中，可根據預定要形成的金屬柱凸塊材料的柱體厚度，而控制並選擇感光層216的厚度為一預定值。在本實施例中，可以一般的製程圖案化感光層216，以形成第二開口218，其圍繞保護層206的第一開口208。第二開口218暴露出部分的凸塊下金屬化層210，以定義出一金屬柱220的一窗口(如第2C圖至第2H圖以及第4A圖至第4C圖所示)。
值得注意的是，當金屬柱220具有一較大的截面積時，可為覆晶接合結構提供較高的機械強度與較低的電阻。因此，不僅可使感光層216具有一預定厚度以形成金屬柱220，亦可使第二開口218的寬度大於保護層206的第一開口208的寬度，從而提供一較大的截面積以降低金屬柱220的電阻。
然後，可以一具有焊料潤濕性(solder wettability)的金屬材料部分填滿第二開口218。請參照第2C圖，在一些實施例中，以凸塊下金屬化層210為晶種層，沿著第二開口218向上形成一金屬層220。在本實施例中，金屬層220包括一銅層。銅層大體上包括一膜層，其材質包括純元素銅、含有無法避免的雜質的銅、以及含微量元素的銅合金，微量元素例如為鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁、或鋯。金屬層220以及第二凸塊下金屬化次層214可包括相同的材料，例如銅。
銅層220的形成方法包括濺鍍、印刷、電鍍、無電鍍、及/或化學氣相沉積。舉例來說，進行電化學鍍(electro-chemical plating，ECP)以形成金屬層220。
在一實施例中，金屬層220的厚度大於15微米。在另一實施例中，金屬層220的厚度大於40微米。舉例來說，金屬層220的厚度約為40-60微米，或是約為60-120微米，但金屬層220的厚度也可以是大於或是小於前述厚度。在下文中，金屬層220被稱為金屬柱220。
再者，在金屬柱220的頂面上並在感光層216的開口218中形成一金屬蓋層222。金屬蓋層222可做為一阻障層，以避免金屬柱220中的銅擴散進入接合材料中(例如焊料合金)，接合材料是用來接合基板202至外部元件。防止銅擴散可提升封裝結構的可靠度與接合強度。金屬蓋層222為一金屬化層，其可包括鎳、錫、金、銀、鈀、銦、錫鉛(tin-lead，SnPb)、鎳鈀金(nickel-palladium-gold，NiPdAu)、鎳金、其他相似的材料、或是合金。金屬蓋層222可包括一單層結構或是一多層結構。在至少一實施例中，金屬蓋層222的厚度約為1～5微米。
然後，在金屬蓋層222上並在感光層216的開口218中形成一焊料層224。焊料層224係作為基板202的一連接端子。焊料層224的材質包括錫、錫銀、錫鉛、錫銀銅(銅含量<0.5重量百分比)、錫銀鋅、錫鋅、錫鉍銦、錫銦、錫金、錫鉛、錫銅(銅含量<0.7重量百分比)、錫鋅銦、或是錫銀銻(SnAgSb)等。在至少一實施例中，焊料層224可為無鉛焊料(lead-free solder)材料層。
請參照第2D圖，在感光層216的開口218中形成焊料層224之後，可以適合的濕式蝕刻或是乾式蝕刻製程移除感光層216，以暴露出部分的凸塊下金屬化層210。當感光層216為一乾膜時，可使用鹼性溶液移除感光層216。最終生成的結構包括金屬柱220、金屬蓋層222、以及焊料層224，且暴露出金屬柱220的側壁220s。
之後，以最終生成的結構(包括金屬柱220、金屬蓋層222、以及焊料層224)為硬罩幕，依照凸塊下金屬化材料而以適合的濕式及/或乾式蝕刻製程蝕刻第二凸塊下金屬化次層214的外露部。在至少一實施例中，濕式蝕刻製程包括在一含有亞磷酸(H3 PO3 )與過氧化氫(H2 O2 )的溶液中移除部分的第二凸塊下金屬化次層214(其含銅)。
更進一步地，利用最終生成的結構(現在包括金屬柱220、金屬蓋層222、焊料層224、以及第二凸塊下金屬化次層214)為硬罩幕，以適合的濕式及/或乾式蝕刻製程移除部分的第一凸塊下金屬化次層212，以暴露出保護層206。在至少一實施例中，第一凸塊下金屬化次層212的材質包括鈦、鉭、氮化鈦、或氮化鉭，用以移除部分的第一凸塊下金屬化次層212的乾式蝕刻製程係利用氟、氯、或是溴基蝕刻劑。
之後，對第2D圖的半導體元件200進行一回焊處理(reflow treatment)以熔化焊料層224，以形成一半球狀的焊料凸塊224a於金屬柱220上(如第2E圖所示)，舉例來說，可透過晶圓加熱(wafer heating)或是快速熱處理(rapid thermal processing，RTP)來達成。製程步驟至此已形成具有一凸塊結構230的基板202，凸塊結構230包括金屬柱220、金屬蓋層222、以及半球狀的焊料層224a。
值得注意的是，金屬柱220的材質包括銅，亦可稱為銅柱220，其容易在製程中氧化。氧化的銅柱220會導致電子元件與基板之間的黏著性不佳。黏著性不佳可能會導致高漏電流，而產生嚴重的可靠度問題。氧化的銅柱220亦可能導致底膠沿著底膠與銅柱220的接面裂開。裂痕可能會延伸到下方的低介電常數(低k值)介電層或是延伸到焊料(其係用以接合銅柱220至基板)。
因此，以下描述的製程(如第2F圖至第2H圖以及第4A圖至第4C圖所示)可形成一側壁保護層(sidewall protection layer)以保護銅柱220的外露側壁220s。側壁保護層可保護銅柱220免於氧化並提升元件性能(device performance)。
第2F圖繪示第2E圖的半導體元件200在使金屬柱220的側壁220s與一有機化合物反應而形成一有機化合物的自組裝單層(self-assembled monolayer)226a於金屬柱220的側壁220s上。在至少一實施例中，有機化合物包括，但不限於，一頭部基(head group)、一官能基(functional group)、以及一位於頭部基與官能基之間的尾基(tail group)，其中頭部基為一硫醇基(thiol group，-SH)。在一些實施例中，官能基包括甲基(CH3 )、羥基(OH)、氨基(NH2 )、及/或羧酸基(COOH)；以及尾基包括一具有4～20個碳的碳鏈。
自組裝單層226a的膜層形成機制為液相或是氣相的有機化合物的頭部基化學吸附在金屬柱220的側壁220s上，然後，尾基緩慢的進行二維組織(two-dimensional organization)以於金屬柱220的側壁220s上形成有機化合物的自組裝單層226a。在本實施例中，金屬柱220的側壁220s與有機化合物的反應步驟是在約20℃～50℃下進行的。現在，金屬柱220已預備好進行焊接製程且直到焊接製程進行為止可避免被氧化。
此外，在使金屬柱220的側壁220s與有機化合物反應之前，可用去離子水、檸檬酸(citric acid)、以及異丙醇(isopropyl alcohol，IPA)清潔金屬柱220的側壁220s。再者，可在使金屬柱220的側壁220s與有機化合物反應之後，以異丙醇處理基板202。
之後，切割基板202並連接至另一基板232。第2G圖的結構顯示翻覆基板202並以底部貼附至基板232。基板232可為一封裝基板、板材(例如印刷線路板)、另一晶粒(die)、或是其他適合的基板。在本實施例中，一預焊層(pre-solder layer)236配置於封裝基板232上的一接墊234上。提供一助焊劑(flux)238，以圍繞位於基板202與封裝基板232之間的凸塊結構230與預焊層236。
之後，加熱第2G圖的結構以回焊焊料凸塊224a與預焊層236，從而形成一接點結構240(如第2H圖所示)，其連接基板202與封裝基板232。然後，移除助焊劑238以進行其他製程。基板202、接點結構240、以及封裝基板232可稱為一封裝組合(packaging assembly)，或是在本實施例中，可稱為一覆晶封裝組合(如第2H圖所示)。值得注意的是，在移除助焊劑之前，自組裝單層226a隔離金屬柱220的側壁220s以避免其氧化，故可保護金屬柱220的側壁220s。因此，本發明之半導體元件200的製作方法可製作一金屬柱220，其具有一保護的自組裝單層226a，以避免電子元件與基板的黏著性不佳，並可提升元件性能。
第3圖繪示本發明另一實施例之半導體元件的製作方法300的流程圖，其中半導體元件包括金屬柱。製作方法300的步驟302為提供一基板，其具有一接墊。製作方法300的步驟304為形成一保護層，其延伸於基板上並具有一位於接墊上的開口。製作方法300的步驟306為將一金屬柱形成於接墊與部分保護層上。製作方法300的步驟308為將一焊料層形成在金屬柱上。製作方法300的步驟310為使金屬柱的側壁與一有機化合物反應，以於金屬柱的側壁上形成有機化合物的自組裝多層(self-assembled multi-layers)。以下將介紹第3圖的製作方法的一實施例。
第4A-4C圖繪示本發明一實施例之一半導體元件400的一金屬柱220在各製程步驟的剖面圖。值得注意的是，第3圖的製作方法並未製做出一完整的半導體元件400。因此，可以了解的是，可以在第3圖的製作方法300之前、之時或之後提供另外的製程，並且，在此可能僅簡單描述一些其他的製程。再者，為可較佳地了解本發明的發明概念，可簡化第4A圖至第4C圖。舉例來說，雖然圖示繪示一半導體元件400的金屬柱220，可以了解的是，半導體元件400可能是一積體電路封裝的一部分，該積體電路封裝可更包括多個其他的元件，例如底膠、導線架等。
第4A圖繪示半導體元件400(相似於第2E圖中的半導體元件200)在使金屬柱220的側壁220s與一有機化合物反應而形成有機化合物426的自組裝多層426a於金屬柱220的側壁220s上。在本實施例中，金屬柱220的側壁220s與有機化合物426的反應步驟是在約20℃～50℃下於一溶液中進行的。前述溶液包括有機化合物與金屬離子，包括鋅離子、銅離子、鎳離子、鈷離子、鐵離子、或前述之組合。在至少一實施例中，有機化合物包括苯並咪唑(benzimidazole)或苯並咪唑衍生物(derivative)，舉例來說，1-甲基苯並咪唑(1-methylbenzimidazole)、或2-三氟甲基苯并咪唑(2-trifluoromethylbenzimidazole)。在另一實施例中，有機化合物包括咪唑(imidazole)、或咪唑衍生物，舉例來說，烷基咪唑(alkylimidazole)、或烷基苯并咪唑(alkylbenzimidazole)。
當將含有咪唑的溶液施加在含銅的金屬柱220的側壁220s上時，咪唑與來自於銅表面的銅離子反應，而形成不可溶的銅-咪唑錯合物(complex)，其沉澱並形成自組裝多層426a於金屬柱220的側壁220s上。此外，添加到含有咪唑的溶液中的金屬離子可有助於催化銅-咪唑錯合物的形成速度。現在，金屬柱220已預備好進行焊接製程且直到焊接製程進行為止可避免被氧化。
此外，在使金屬柱220的側壁220s與有機化合物反應之前，可用酸性溶液清潔金屬柱220的側壁220s。再者，在使金屬柱220的側壁220s與有機化合物反應之後，可用惰性氣體(inert gas)乾燥基板202。
之後，切割基板202並連接至另一基板432。第4B圖的結構顯示翻覆基板202並以底部貼附至基板432。基板432可為一封裝基板、板材(例如印刷線路板)、另一晶粒、或是其他適合的基板。在本實施例中，一預焊層436配置於封裝基板432上的一接墊434上。提供一助焊劑438，以圍繞位於基板202與封裝基板432之間的凸塊結構230與預焊層436。
之後，加熱第4B圖的結構以回焊焊料凸塊224a與預焊層436，從而形成一接點結構440(如第4C圖所示)，其連接基板202與封裝基板432。然後，移除助焊劑438以進行其他製程。基板202、接點結構440、以及封裝基板432可稱為一封裝組合，或是在本實施例中，可稱為一覆晶封裝組合(如第4C圖所示)。值得注意的是，在移除助焊劑之前，自組裝多層426a隔離金屬柱220的側壁220s以避免其氧化，故可保護金屬柱220的側壁220s。因此，本發明之半導體元件400的製作方法可製作一金屬柱220，其具有一保護的自組裝多層426a，以避免電子元件與基板的黏著性不佳，並可提升元件性能。
可以了解的是，可對半導體元件200、400進行其他的半導體製程，以形成各種結構，例如底膠、導線架等。
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、300．．．製作方法
102、104、106、108、110、302、304、306、308、310．．．步驟
200、400．．．半導體元件
202．．．基板
203．．．金屬間介電層
204．．．接墊
206．．．保護層
208．．．第一開口
210．．．凸塊下金屬化層
212．．．第一凸塊下金屬化次層
214．．．第二凸塊下金屬化次層
216．．．感光層
218．．．第二開口、開口
220．．．金屬柱、金屬層、銅層、銅柱
220s．．．側壁
222．．．金屬蓋層
224．．．焊料層
224a．．．焊料凸塊、半球狀的焊料凸塊、半球狀的焊料層
226a．．．自組裝單層
230．．．凸塊結構
232、432．．．封裝基板、基板
234、434．．．接墊
236、436．．．預焊層
238、438．．．助焊劑
240、440．．．接點結構
426a．．．自組裝多層
第1圖繪示本發明多個實施例之半導體元件的製作方法的流程圖，其中半導體元件包括金屬柱。
第2A-2H圖繪示本發明多個實施例之一半導體元件的一金屬柱在各製程步驟的剖面圖。
第3圖繪示本發明多個實施例之半導體元件的製作方法的流程圖，其中半導體元件包括金屬柱。
第4A-4C圖繪示本發明多個實施例之一半導體元件的一金屬柱在各製程步驟的剖面圖。
200．．．半導體元件
202．．．基板
203．．．金屬間介電層
204．．．接墊
206．．．保護層
210．．．凸塊下金屬化層
212．．．第一凸塊下金屬化次層
214．．．第二凸塊下金屬化次層
220．．．金屬柱、金屬層、銅層、銅柱
222．．．金屬蓋層
226a．．．自組裝單層
232．．．封裝基板、基板
234．．．接墊
240．．．接點結構

Claims (10)

  1. 一種半導體元件的製作方法，包括：提供一基板，該基板具有一接墊；形成一保護層延伸於該基板上並具有一位於該接墊上的開口；形成一金屬柱於該接墊與部分該保護層上；形成一焊料層於該金屬柱上；以及使該金屬柱的多個側壁與一有機化合物反應，以形成該有機化合物的一自組裝單層於該金屬柱的該些側壁上。
  2. 如申請專利範圍第1項所述之半導體元件的製作方法，其中該有機化合物位於一溶液中。
  3. 如申請專利範圍第2項所述之半導體元件的製作方法，其中該金屬柱的該些側壁與一有機化合物反應的步驟是在約20℃至50℃下進行。
  4. 如申請專利範圍第1項所述之半導體元件的製作方法，其中該有機化合物為液相。
  5. 如申請專利範圍第1項所述之半導體元件的製作方法，其中該有機化合物包括一頭部基、一官能基、以及一位於頭部基與官能基之間的尾基，該頭部基為一硫醇基，該官能基包括甲基、羥基、氨基、或羧酸基，該尾基包括一具有4～20個碳的碳鏈。
  6. 如申請專利範圍第1項所述之半導體元件的製作方法，其中該金屬柱為一銅柱。
  7. 一種半導體元件的製作方法，包括：提供一基板，該基板具有一接墊；形成一保護層延伸於該基板上並具有一位於該接墊上的開口；形成一金屬柱於該接墊與部分該保護層上；形成一焊料層於該金屬柱上；以及使該金屬柱的多個側壁與一有機化合物反應，以形成該有機化合物的自組裝多層於該金屬柱的該些側壁上。
  8. 如申請專利範圍第7項所述之半導體元件的製作方法，其中該有機化合物位於一溶液中，該溶液包括金屬離子，該金屬離子為鋅離子、銅離子、鎳離子、鈷離子、鐵離子、或前述之組合。
  9. 如申請專利範圍第7項所述之半導體元件的製作方法，其中該有機化合物包括苯並咪唑或苯並咪唑衍生物。
  10. 如申請專利範圍第7項所述之半導體元件的製作方法，其中該有機化合物包括咪唑或咪唑衍生物。
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