CN102810506B - 用于芯片级封装的电连接 - Google Patents

用于芯片级封装的电连接 Download PDF

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Publication number
CN102810506B
CN102810506B CN201210020209.5A CN201210020209A CN102810506B CN 102810506 B CN102810506 B CN 102810506B CN 201210020209 A CN201210020209 A CN 201210020209A CN 102810506 B CN102810506 B CN 102810506B
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China
Prior art keywords
bond pad
semiconductor device
width
layer
length
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CN201210020209.5A
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CN102810506A (zh
Inventor
游明志
李福仁
林柏尧
郑嘉仁
游秀美
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供了一种用于提供后钝化和凸块下金属化层的系统和方法。实施例包括大于上部凸块下金属化层的后钝化层。延伸超过凸块下金属化层的后钝化层保护了下层免受由材料的热膨胀系数不匹配而产生的应力的影响。本发明还提供了一种用于芯片级封装的电连接。

Description

用于芯片级封装的电连接
技术领域
本发明涉及半导体领域，更具体地，本发明涉及一种用于芯片级封装的电连接。
背景技术
通常，可以通过利用焊料凸块的封装类型将半导体管芯连接至在该半导体管芯外部的其他器件。可以通过最初在半导体管芯的上方形成凸块下金属化层，然后将焊料设置在凸块下金属化层的上方来形成焊料凸块。在设置焊料以后，为了将焊料成形为期望的凸块形状，可以实施回流操作。然后，可以将焊料凸块设置为与外部器件物理接触，并且为了将焊料凸块与外部器件相接合，可以实施另一回流操作。在这种方法中，可以在半导体管芯和外部器件(例如，印刷电路板、另一半导体管芯等)之间进行物理连接和电连接。
然而，包括凸块下金属化层的材料仅为一种以上类型的材料，将这些材料设置在多种不同材料的叠层(例如，介电材料、金属化材料、蚀刻停止材料、势垒层材料、以及在形成半导体管芯中所利用的其他材料)的上方。这些不同材料中的每一种都可以具有与其他材料不同的唯一的热膨胀系数。当在稍后的处理和使用期间加热半导体管芯时，这种类型的热膨胀系统不匹配使这些材料中的每种材料膨胀了不同距离。同样地，在升高的温度下，存在热膨胀系数不匹配，该热膨胀系数不匹配导致在不同材料和因此半导体管芯的不同部件之间形成应力。这种不匹配在凸块下金属化层和下部金属层之间尤为普遍。尤其当使用的材料包括铜和低k(介电常数)介电层时，如果不控制，则这种应力可能导致在各种不同材料层之间的产生分层。在制作工艺期间，或者在其期望使用期间，这种分层可能损坏，甚至毁坏半导体管芯。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种半导体器件，包括：后钝化互连件，位于衬底上方，其中，所述后钝化互连件包括：接合焊盘区域，具有第一长度和第一宽度；以及互连区域，具有小于所述第一宽度的第二宽度；以及凸块下金属化层，位于所述后钝化互连件上方，所述凸块下金属化层具有与所述接合焊盘区域相接触的界面，所述界面具有小于所述第一宽度和所述第一长度的第二长度，所述凸块下金属化层具有小于所述第一宽度和所述第一长度的第三长度。
在该半导体器件中，所述接合焊盘包括连续导电材料。
在该半导体器件中，所述第一长度大于所述第一宽度。
在该半导体器件中，所述接合焊盘具有与所述衬底的中心对准的纵轴。
在该半导体器件中，进一步包括：钝化层，位于所述后钝化互连件上方，所述凸块下金属化层延伸穿过所述钝化层。
在该半导体器件中，所述接合焊盘在两个相反方向上从所述界面延伸相同距离，所述两个相反方向都与所述接合焊盘的纵轴在同一直线上。
在该半导体器件中，所述接合焊盘在与所述接合焊盘的纵轴平行的第一方向上从所述界面延伸第一距离，并且在与所述第一方向在同一直线上的第二方向上延伸第二距离，所述第二距离与所述第一距离不同，所述第一方向与所述第二方向不同。
在该半导体器件中，所述接合焊盘在两个相反方向上从所述界面延伸相同距离，所述两个相反方向彼此在同一直线上，并且与所述接合焊盘的纵轴垂直。
在该半导体器件中，所述接合焊盘在与所述接合焊盘的纵轴垂直的第一方向上从所述界面延伸第一距离，并且在与所述第一方向在同一直线上的第二方向上延伸第二距离，所述第二距离与所述第一距离不同，所述第一方向与所述第二方向不同。
根据本发明的另一方面，提供了一种半导体器件，包括：接触焊盘，位于衬底上方；再分布层，与所述接触焊盘电接触，所述再分布层包括接合焊盘，所述接合焊盘具有第一长度和第一宽度；凸块下金属化层，与所述接合焊盘物理接触，所述凸块下金属化层具有：大于所述第一长度的第二长度和大于所述第一宽度的第二宽度；以及导电材料的第一外围区域，位于所述凸块下金属化层的外边缘下方，并且与所述再分布层横向分隔开。
在该半导体器件中，进一步包括：钝化层，位于第一层上方，其中，导电材料的所述第一外围区域和所述再分布层位于所述第一层中。
在该半导体器件中，所述第一外围区域为矩形。
在该半导体器件中，所述第一外围区域为月牙形。
在该半导体器件中，所述第一外围区域为椭圆形。
在该半导体器件中，进一步包括：第二外围区域，位于所述凸块下金属化层的所述外边缘的下方；以及第三外围区域，位于所述凸块下金属化层的所述外边缘的下方，所述第二外围区域与所述第三外围区域和所述第一外围区域横向分隔开。
在该半导体器件中，所述接合焊盘为连续导电材料。
根据本发明的又一方面，提供了一种半导体器件，包括：后钝化互连件结构，位于衬底上方，所述后钝化互连结构包括：接合焊盘区域，具有第一长度、小于所述第一长度的第一宽度，和纵轴；以及互连区域，具有第二宽度，所述第二宽度小于所述第一宽度；钝化层，位于所述后钝化互连结构上方；开口，穿过所述钝化层到达所述接合焊盘区域；凸块下金属化层，位于所述接合焊盘区域上方，并且通过所述开口与所述接合焊盘区域相接触，其中，所述接合焊盘区域在与所述纵轴平行的第一方向上延伸超过所述开口，并且还在与所述纵轴垂直的第二方向上延伸超过所述开口。
在该半导体器件中，所述后钝化互连结构为连续的。
在该半导体器件中，所述接合焊盘具有与所述衬底的中心对准的纵轴。
在该半导体器件中，所述凸块下金属化层的中心偏离所述接合焊盘的中心。
附图说明
为了更好地理解实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1示出了根据实施例的后钝化互连件和凸块下金属化层的横截面图；
图2示出了根据实施例的后钝化互连件和凸块下金属化层的俯视图；
图3示出了根据实施例的后钝化互连件的对准的俯视图；
图4示出了根据实施例的后钝化和凸块下金属化层的建模结果；
图5示出了根据实施例的断开的后钝化互连件和凸块下金属化层的横截面图；以及
图6A-图6C示出了根据实施例的不连续的后钝化互连件和凸块下金属化层的俯视图。
除非另有说明，否则不同附图中的相应数字和符号通常指的是相应的部件。为了清楚地示出实施例的相关方面，绘制附图并且没有必要按比例绘制。
具体实施方式
下面，详细讨论本实施例的制造和使用。然而，应该理解，本实施例提供了许多可以在各种具体环境中实现的可应用的发明概念。所讨论的具体实施例仅仅示出制造和使用实施例的具体方式，而不用于限制本实施例的范围。
关于在具体环境下的实施例，即，位于凸块下金属化层下方的后钝化互连件，描述了实施例。然而，还可以将该实施例应用于其他金属层。
现在，参考图1，示出了半导体管芯100的一部分，包括：具有金属层103的半导体衬底101、接触焊盘105、第一钝化层107、第二钝化层109、后钝化互连件(PPI)111、第三钝化层113、凸块下金属化层(UBM)115、以及接触凸块117。半导体衬底101可以包括：掺杂或未掺杂的体硅、或者绝缘体上硅(SOI)衬底的有源层。通常，SOI衬底包括：半导电材料层，例如硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)、或者其组合。可以使用的其他衬底包括：多层衬底、梯度衬底、或者混合定向衬底。
可以在半导体衬底101的上方形成有源器件(未示出的)。本领域普通技术人员之一应该意识到，可以将诸如电容器、电阻器、电感器等的各种无源器件用于生成用于半导体管芯100的设计的期望结构和功能要求。可以使用任何适当方法在半导体衬底101内或半导体衬底的表面上形成有源器件。
在半导体衬底的101和有源器件的上方形成金属化层103，并且将该金属化层设计为连接各种有源器件，从而形成功能电路。虽然在图1中作为单层示出了金属化层103，但是金属化层可以由介电材料(例如，低k介电材料)和导电材料(例如，铜)的交替层形成，并且可以通过任何适当工艺(诸如沉积、镶嵌、双镶嵌等)形成该金属化层。在实施例中，可能具有通过至少一个层间介电层(ILD)与半导体衬底101分隔开的四个金属化层，但是金属化层103的精确数量取决于半导体管芯100的设计。
可以在金属化层103的上方形成接触焊盘105，并且该接触焊盘与该金属化层电连接。接触焊盘105可以包含铝，但是可选地，可以使用其他材料，例如铜。可以使用沉积工艺，例如溅射形成接触焊盘105，从而形成材料层(未示出的)，并且可以通过适当工艺(诸如，光刻、掩模、以及蚀刻)去除材料层的多部分，从而形成接触焊盘105。然而，可以利用任何其他适当工艺，从而形成接触焊盘105。所形成接触焊盘105可以具有处于约0.5μm和约4μm之间的厚度，例如约1.45μm。
可以在半导体衬底101上的金属层103和接触焊盘105的上方形成第一钝化层107。第一钝化层107可以由一种或多种适当介电材料，例如，氧化硅、氮化硅；低k电介质，例如掺碳氧化物；超低k电介质，例如，多孔碳掺杂二氧化硅(porous carbon doped silicon dioxide)；这些材料的组合等制成。可以通过诸如化学汽相沉积(CVD)的工艺形成第一钝化层107，但是可以利用任何适当工艺，并且该第一钝化层可以具有在约0.5μm和约5μm之间的厚度，例如约
在形成了第一钝化层107以后，可以通过去除第一钝化层107的部分制造穿过第一钝化层107的开口，从而暴露出下层接触焊盘105的至少一部分。开口允许接触焊盘105与PPI 111(下文进一步讨论的)之间相接触。可以使用适当光刻掩模和蚀刻工艺形成开口，但是可以使用任何适当工艺，从而暴露出接触焊盘105的部分。
可以在接触焊盘105和第一钝化层107的上方形成第二钝化层109。可以通过诸如聚酰亚胺的聚合物形成第二钝化层109。可选地，第二钝化层109可以由与用作第一钝化层107的材料类似的材料形成，例如，氧化硅、氮化硅、低k电介质、超低k电介质、这些材料的组合等。可以将第二钝化层109形成为具有在约2μm和约15μm之间的厚度，例如约5μm。
在形成了第二钝化层109以后，可以通过去除第二钝化层109的多部分制造穿过第二钝化层109的开口，从而暴露下接触焊盘105的至少一部分。开口允许在接触焊盘105和PPI 111(下文进一步讨论的)之间的接触。可以使用适当光刻掩模和蚀刻工艺形成开口，但是可以使用任何适当工艺，从而暴露接出触焊盘105的部分。
在暴露出接触焊盘105以后，可以将PPI 111形成为沿着第二钝化层109延伸。可以使用PPI 111作为再分布层，使得电连接至接触焊盘105的UBM 115能够被放置在半导体管芯100上的任何期望位置，从而不会对UBM 115的位置产生限制。在实施例中，可以通过最初通过诸如CVD或溅射的适当形成工艺形成钛铜合金的种子层(未示出的)来形成PPI 111。然后，可以形成光刻胶(未示出)，从而覆盖种子层，并且然后，将光刻胶图案化，从而暴露定位在期望设置PPI 111的位置的种子层的这些部分。
一旦形成了光刻胶并且将该光刻胶图案化，可以通过诸如电镀的沉积工艺在种子层上形成诸如铜的导电材料。可以将导电材料形成为具有处于约1μm和约10μm之间的厚度，例如约5μm；并且具有处于约5μm和约300μm之间的沿着衬底101的宽度，例如约15μm。然而，虽然所讨论的材料和方法适用于形成导电材料，这些材料仅为示例性的。可选地，可以使用任何其他适当材料，例如AlCu或Au；以及任何其他适当的形成工艺，诸如CVD或PVD来形成PPI 111。
一旦形成了导电材料，就可以通过诸如灰化的适当去除工艺，去除光刻胶。附加地，在去除光刻胶以后，由光刻胶覆盖的种子层的这些部分可以通过，例如，使用导电材料作为掩模的适当蚀刻工艺来去除。
一旦形成了PPI 111，就可以形成第三钝化层113，从而保护PPI 111和其他下层结构。与第二钝化层109相似，第三钝化层113可以由诸如聚酰亚胺的聚合体形成，或者可选地，可以由与第一钝化层107相似的材料形成(例如，氧化硅、氮化硅、低k电介质、超低k电介质、这些材料的组合等)。所形成的第三钝化层113可以具有处于约2μm和约15μm之间的厚度，例如约5μm。
在形成了第三钝化层113以后，可以通过去除第三钝化层113的部分制造穿过第三钝化层113的PPI开口108。PPI开口108使得UBM 115和PPI 111之间能够相接触。可以使用适当光刻掩模和蚀刻工艺形成PPI开口108，但是可选地，可以使用任何适当工艺暴露出PPI 111的部分。
一旦通过第三钝化层113暴露出PPI 111，UBM 115就可以形成为与PPI 111电接触。UBM 115可以包括三层导电材料，例如，钛层、铜层、以及镍层。然而，本领域普通技术人员应该意识到，可以存在适用于UBM 115的形成的多种材料和多层的适当配置，例如，铬/铬铜合金/铜/金的配置、钛/钛钨/铜的配置、或者铜/镍/金的配置。可以用于UBM 115的任何适当材料或材料层完全旨在包括在本申请的范围内。
可以通过在第三钝化层113的上方并且沿着穿过第三钝化层113的PPI开口108的内部形成每层来制造UBM 115。可以使用电镀工艺，例如，电化学镀层实施形成每层，但是可选地，可以根据期望材料使用诸如溅射、蒸发、或者PECVD工艺的其他形成工艺。可以形成UBM 115，从而具有在约在约0.7μm和约10μm之间的厚度，例如约5μm。一旦已经形成期望层，然后，就可以通过适当光刻掩模和蚀刻工艺去除多层的多部分，从而去除不期望材料并且以期望形状保留UBM 115，例如，圆形、八边形、正方形或者矩形形状，但是可选地，可以形成任何期望形状。
接触凸块117可以包含诸如锡的材料，或者诸如银、无铅锡、或者铜的其他适当材料。在实施例中，其中，接触凸块117为锡焊料凸块，可以通过最初通过这些通用方法(例如，蒸发、电镀、印刷、移焊法(soldertransfer)、焊球置放(ball placement)等)形成例如约100μm的厚度的锡层来形成接触凸块117。一旦在该结构上形成了锡层，为了将材料成型为期望的凸块形状，可以实施回流。
图2示出了沿着线A-A′(在图1中)在PPI 111和PPI开口108的上方的UBM 115的俯视图，其中，为了清楚，从图2中去除了接触凸块117、第三钝化层113、以及在PPI 111下方的层。另外，在该示图中，在PPI开口108内的UBM 115和PPI开口108本身共用相同边界。如在俯视图中所示出，PPI开口108和在PPI开口108内的UBM 115可以具有在约60μm和约500μm之间的第一直径D1，例如约250μm。PPI 111可以具有互连区域204和第一区域202，例如，接合焊盘，位于UBM 115的下方，具有在每个方向上比PPI开口108更大的尺寸，从示图的从上到下的角度来看，有效地围绕PPI开口108和在PPI开口108内的UBM 115。在实施例中，PPI 111可以在一个方向(例如，与A-A′平行)上具有第一长度L1，第一长度大于在另一方向(例如，与B-B′平行)上的第一宽度W1。通过使得第一宽度W1大于第一长度L1，另外地，PPI 111可以具有在图2中通过虚线201所示出的纵轴。另外地，互连区域204可以具有小于第一宽度W1的第二宽度W2，该第二宽度W2可以处于比如约60μm和约550μm之间，例如约300μm。
仅作为实例，在图2中所示的实施例中，PPI 111的第一长度L1可以延伸超出PPI开口108第一距离A1，该第一距离可以处于约0.5μm和约100μm之间，例如约50μm。在相反方向上，PPI 111的第一长度L1可以延伸超出PPI开口108第二距离A2，第二距离可以处于约0.5μm和约100μm之间，例如约50μm。同样地，PPI 111的第一长度L1可以等于PPI开口108的第一直径D1加第一距离A1和第二距离A2。
另外地，PPI 111的第一区域202的第一宽度W1可以延伸第三距离B1，该第三距离处于约0.5μm和约50μm之间，例如约5μm。在与纵轴201垂直的相反方向上，PPI 111可以延伸第四距离B2，该第四距离可以处于约0.5μm和约50μm之间，例如约5μm。同样地，PPI 111的第一区域202的第一宽度W1可以等于PPI开口108的第一直径D1加第三距离B1和第四距离B2。
在实施例中，第一距离A1和第二距离A2可以彼此相等，但是可选地，第一距离和第二距离也可以彼此不相等。类似地，第三距离B1可以与第四距离B2相等，但是可选地，第三距离和第四距离也可以为不同距离。然而，在实施例中，其中，PPI 111的第一区域202具有延长的形状，并且PPI开口108为具有第一直径D1的圆，第一距离A1和第二距离A2的总和大于第三距离B1和第四距离B2的总和。同样地，PPI 111的第一区域202的第一长度L1可以为第一直径D1加第一距离A1和第二距离A2的和，而在UBM115的下方的PPI 111的第一区域202的第一宽度W1可以为第一直径D1加第三距离B1和第四距离B2的和。
通过扩大PPI 111的尺寸，使得PPI 111具有比在第一区域202中的PPI开口108更大的尺寸，甚至超过UBM 115，PPI 111可以通过可能在热处理期间产生的剥离应力有效地保护下层，例如金属化层103(参见图1)，该金属化层为金属和超低k介电层的组合。尤其是，PPI 111可以有效地保护下层免受多层之间的热膨胀不匹配所生成的应力的影响。同样地，不可能产生多层的分层，并且可以提高制造工艺的总成品率。另外地，通过在第一区域202中扩大PPI 111，此外，PPI 111的剩余部分不必放大，使得与如果放大整个PPI 111获得的金属密度相比较，该PPI 111层的金属密度更高。
图3示出了具有位于其上的多个UBM 115的半导体管芯100的俯视图(俯视图仅示出了位于管芯上的UBM 115，而第一实例305和第二实例307示出了UBM 115以及PPI 111)。在实施例中，可以使得热膨胀系数不匹配方向(在图3中通过线303所示出的)与位于UBM 115下方的PPI 111的纵轴201位于同一直线上。仅作为实例，在半导体管芯100上，热膨胀系数不匹配303的方向从半导体管芯100的中心向外扩散。同样地，对于在图3中所示的每个UBM 115，可以通过从半导体管芯100的中心向独立UBM 115的中心绘制线(例如，在图3中的第一线309和第二线311)来确定热膨胀系数不匹配的方向303。一旦已经确定每个单独的UBM 115中的热膨胀系数不匹配方向303，就可以沿着相同线使得位于每个独立UBM115下方的每个PPI 111的纵轴201都在同一直线上。
在图3中示出了这两个实例，其中，通过虚线框305示出了第一实例，并且通过第二虚线框307示出了第二实例。在第一实例中，沿着半导体管芯100的外部边缘设置UBM 115，并且可以通过第一线309从半导体管芯100的中心延伸至在虚线框305内的UBM 115的中心来确定热膨胀系数不匹配方向303。一旦虚线框307内的UBM 115确定了热膨胀系数不匹配方向303，就可以使得PPI 111的纵轴201与热膨胀系数的不匹配的方向303在同一直线上，从而有助于保护下层免受热膨胀系数的差距所产生的应力的影响。
在第二实例中，与第一实例相似，通过将第一线311从半导体管芯100的中心延伸至在虚线框307内的UBM 115的中心来确定热膨胀系数不匹配方向303。一旦对于在虚线框307内的UBM 115已经确定热膨胀系数不匹配方向303，就可以使得下层PPI 111的纵轴201与热膨胀系数的不匹配的方向303在同一直线上，从而也有助于保护下层免受热膨胀系数的差距所产生的应力的影响。
然而，本领域中普通技术人员应该意识到，确定热膨胀系数不匹配方向303的上述方法不是可以使用的唯一方法。可选地，可以利用可选方法，例如用实验方法测量实际的热膨胀系数不匹配方向303。另外，为了具有与热膨胀系数不匹配方向303在同一直线上的第一区域202的纵轴201，可以相对于PPI 111的剩余物旋转第一区域202。可选地，可以使用这些方法和任何其他适当方法，并且完全旨在包括在本实施例的范围内。
图4示出了有助于示出实施例的优点的建模结果。如所示，可以通过使得PPI 111的尺寸大于上部UBM 115的尺寸，降低下部金属化层中的相对应力等级。同样地，PPI 111通过由热膨胀系数的不匹配所产生的应力有效地保护下部金属化层103。同样地，通过降低应力等级，还可以降低分层的可能性。
图5示出了另一实施例，其中，可以形成PPI 111作为具有主体部501和第一外围部503的不连续层。在图5中所示的实施例中，PPI 111的主体部501可以从接触焊盘105延伸至UBM 115的下方，但是可以没有完全延伸超过位于另一侧上的UBM 115。然而，为了通过从PPI开口108横向去除并且具有位于UBM 115的下方的部分和超过UBM 115延伸的部分提供对下层的保护，从而可以形成PPI 111的第一外围部503。在实施例中，PPI111的第一外围部503可以与主体部501分隔开第五距离D5，第五距离处于约0.5μm和约100μm之间，例如约10μm，并且可以从PPI开口108横向去除第六距离D6，该第六距离处于约1μm和约300μm之间，例如约5μm。
图6A示出了在图5中所示的实施例的俯视图，其中，示出了PPI 111、PPI开口108、以及整个UBM 115(包括位于PPI开口108的外部的UBM 115的这些部分)。在该实施例中，主体部501可以具有位于UBM 115的下方的第二区域602，该第二区域具有第二直径D2，该第二直径小于UBM 105的第一直径D1。例如，第二区域602可以具有第二直径D2，第二直径处于约15μm和约450μm之间，例如约250μm。另外，在该实施例中，PPI开口108可以具有第三直径D3，该第三直径D3处于5约μm和约400μm之间，例如约50μm。第二区域602可以为连续导电材料，或者，可以通过介电材料将该第二区域图案化，从而形成不连续导电材料。
在图6A中将第一外围部503示出为矩形，其中，该矩形具有第三宽度W3和第二长度L2，该第三宽度W3处于约3μm和约300μm之间，例如约20μm；该第二长度L2处于约3μm和约300μm之间，例如约20μm。另外，图6A还示出了第二外围部601和第三外围部603，第二外围部和第三外围部具有与主体部501的纵轴201相平行的纵轴605。在实施例中，可以将第二外围部601和第三外围部603形成为具有第四宽度W4和第三长度L3，该第四宽度W4处于约3μm和约300μm之间，例如约20μm；该第三长度L3处于约3μm和约300μm之间，例如约20μm。此外，第二外围部601和第三外围部603可以以第六距离D6与主体部501分隔开，该第六距离D6处于约0.5μm和约100μm之间，例如约10μm。
通过利用具有主体部(primary section)501和外围部(periphery section)(例如第一外围部503、第二外围部601、以及第三外围部603)的不连续的PPI 111，可以扩大PPI 111的设计选项，同时仍保持保护下层的PPI 111的优点。同样地，可以扩大设计可选范围(design option)，从而对于设计者使整体设计更简单。
图6B示出了又一实施例，其中，不是作为矩形(与在上文的图6A中相同的)，而是以月牙形形状设计第一外围部503、第二外围部601、以及第三外围部603。在该实施例中，主体部501可以保持具有第二直径D2的其圆形端部，而没有延伸超过UBM 115。然而，第一外围部503、第二外围部601、以及第三外围部603可以具有内部边缘，该内部边缘通常符合主体部501的外部形状。另外，第一外围部503、第二外围部601、以及第三外围部603外部边缘可以延伸超过UBM 115的外部界限。在实施例中，第一外围部503、第二外围部601、以及第三外围部603可以以第八距离D8与主体部501分隔开，并且可以延伸第四长度L4，该第四长度L4处于约0.5μm和约100μm之间，例如约10μm。另外，诸如第三外围部603的外围部可以与PPI开口108横向分隔开第九距离D9，该第九距离D9处于在约1μm和约300μm之间，例如约5μm。
图6C示出了又一实施例，其中，将第一外围部503、第二外围部601、以及第三外围部603成型为椭圆，并且可以将这些外围部形成为距离主体部501第十距离D10，第十距离D10处于约1μm和约300μm之间，例如约5μm，而诸如第三外围部603的外围部可以与PPI开口108横向分隔开第十一距离D11，第十一距离D11处于约2μm和约500μm之间，例如约8μm。在该实施例中，第一外围部503、第二外围部601、以及第三外围部603可以具有第五长度L5和第五宽度W5，该第五长度L5处于约3μm和约300μm之间，例如约20μm，该第五宽度W5处于约3μm和约300μm之间，例如约20μm。然而，第一外围部503、第二外围部601、以及第三外围部603可以可选地具有不同尺寸。
然而，本领域普通技术人员应该意识到，第一外围部503、第二外围部601、以及第三外围部603的精确形状不旨在限于在图6A-图6C中所描述的矩形、月牙形、以及椭圆形。更确切地，可选地，可以利用任何适当形状，例如，梯形、圆形、或者菱形。这些和任何其他适当形状完全旨在包括在本实施例的范围内。
与第一实施例相似，现有的PPI 111具有主体部501、第一外围部503、第二外围部601、以及第三外围部603，该PPI有助于保护下层免受可能因为不同材料的热膨胀系数不匹配而产生的应力的影响。同样地，通过保护下层免受应力的影响，可以降低分层的可能性，并且可以提高用于制造工艺的总成品率。
根据一个实施例，提供了包括位于衬底上方的后钝化互连件的半导体器件。后钝化互连件包括：接合焊盘区域，具有第一长度和第一宽度；以及互连区域，具有小于第一宽度的第二宽度。凸块下金属位于后钝化互连件上方，凸块下金属化层具有与接合焊盘区域相接触的界面，该界面具有小于第一宽度和第一长度的第二长度，凸块下金属化层具有小于第一宽度和第一长度的第三长度。
根据另一实施例，提供了包括位于衬底上的接触焊盘的半导体器件。再分布层与接触焊盘电接触，再分布层包括凸块下金属化层的接合焊盘，接合焊盘具有第一长度和第一宽度。凸块下金属与接合焊盘物理接触，凸块下金属具有大于第一长度的第二长度和大于第一宽度的第二宽度。导电材料的第一外围区域位于凸块下金属化层的外边缘下方，并且与再分布层横向分隔开。
根据又一实施例，提供了包括位于衬底上方的后钝化互连件结构的半导体器件。后钝化互连件结构包括：接合焊盘区域，具有第一长度(第一宽度小于第一长度)、和纵轴；以及互连区域，具有第二宽度，第二宽度小于第一宽度。钝化层位于后钝化互连件结构上方，并且开口穿过钝化层到达接合焊盘区域。凸块下金属化层位于接合焊盘区域上方，并且与接合焊盘区域相接触，其中，接合焊盘区域在与纵轴平行的第一方向上延伸超过开口，并且还在与纵轴平行的第二方向上延伸超过开口。
尽管已经详细地描述了本实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本实施例的主旨和范围的情况下，做各种不同的改变，替换和更改。例如，可以改变第一外围部件、第二外围部件、以及第三外围部件的精确形状，或者可以改变用于确定热膨胀系数的不匹配的方向的方法。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本实施例的公开，现有的或今后开发的用于执行与本文所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (20)

1.一种半导体器件，包括：
后钝化互连件，位于衬底上方，其中，所述后钝化互连件包括：
接合焊盘区域，具有第一长度和第一宽度；以及
互连区域，具有小于所述第一宽度的第二宽度；以及
凸块下金属化层，位于所述后钝化互连件上方，所述凸块下金属化层具有与所述接合焊盘区域相接触的界面，所述界面具有小于所述第一宽度和所述第一长度的第二长度，所述凸块下金属化层具有小于所述第一宽度和所述第一长度的第三长度，
其中，接合焊盘具有延长的形状，接合焊盘的纵轴与热膨胀系数不匹配方向在同一直线上。
2.根据权利要求1所述的半导体器件，其中，所述接合焊盘包括连续导电材料。
3.根据权利要求1所述的半导体器件，其中，所述第一长度大于所述第一宽度。
4.根据权利要求3所述的半导体器件，其中，所述接合焊盘具有与所述衬底的中心对准的纵轴。
5.根据权利要求1所述的半导体器件，进一步包括：钝化层，位于所述后钝化互连件上方，所述凸块下金属化层延伸穿过所述钝化层。
6.根据权利要求1所述的半导体器件，其中，所述接合焊盘在两个相反方向上从所述界面延伸相同距离，所述两个相反方向都与所述接合焊盘的纵轴在同一直线上。
7.根据权利要求1所述的半导体器件，其中，所述接合焊盘在与所述接合焊盘的纵轴平行的第一方向上从所述界面延伸第一距离，并且在与所述第一方向在同一直线上的第二方向上延伸第二距离，所述第二距离与所述第一距离不同，所述第一方向与所述第二方向不同。
8.根据权利要求1所述的半导体器件，其中，所述接合焊盘在两个相反方向上从所述界面延伸相同距离，所述两个相反方向彼此在同一直线上，并且与所述接合焊盘的纵轴垂直。
9.根据权利要求1所述的半导体器件，其中，所述接合焊盘在与所述接合焊盘的纵轴垂直的第一方向上从所述界面延伸第一距离，并且在与所述第一方向在同一直线上的第二方向上延伸第二距离，所述第二距离与所述第一距离不同，所述第一方向与所述第二方向不同。
10.一种半导体器件，包括：
接触焊盘，位于衬底上方；
再分布层，与所述接触焊盘电接触，所述再分布层包括接合焊盘，所述接合焊盘具有第一长度和第一宽度；
凸块下金属化层，与所述接合焊盘物理接触，所述凸块下金属化层具有：大于所述第一长度的第二长度和大于所述第一宽度的第二宽度；以及
导电材料的第一外围区域，位于所述凸块下金属化层的外边缘下方，并且与所述再分布层横向分隔开，
其中，接合焊盘的纵轴与热膨胀系数不匹配方向在同一直线上。
11.根据权利要求10所述的半导体器件，进一步包括：钝化层，位于第一层上方，其中，导电材料的所述第一外围区域和所述再分布层位于所述第一层中。
12.根据权利要求10所述的半导体器件，其中，所述第一外围区域为矩形。
13.根据权利要求10所述的半导体器件，其中，所述第一外围区域为月牙形。
14.根据权利要求10所述的半导体器件，其中，所述第一外围区域为椭圆形。
15.根据权利要求10所述的半导体器件，进一步包括：
第二外围区域，位于所述凸块下金属化层的所述外边缘的下方；以及
第三外围区域，位于所述凸块下金属化层的所述外边缘的下方，所述第二外围区域与所述第三外围区域和所述第一外围区域横向分隔开。
16.根据权利要求10所述的半导体器件，其中，所述接合焊盘为连续导电材料。
17.一种半导体器件，包括：
后钝化互连件结构，位于衬底上方，所述后钝化互连结构包括：
接合焊盘区域，具有第一长度、小于所述第一长度的第一宽度，和纵轴；以及
互连区域，具有第二宽度，所述第二宽度小于所述第一宽度；
钝化层，位于所述后钝化互连结构上方；
开口，穿过所述钝化层到达所述接合焊盘区域；
凸块下金属化层，位于所述接合焊盘区域上方，并且通过所述开口与所述接合焊盘区域相接触，其中，所述接合焊盘区域在与所述纵轴平行的第一方向上延伸超过所述开口，并且还在与所述纵轴垂直的第二方向上延伸超过所述开口，
其中，热膨胀系数不匹配方向与位于凸块下金属化层下方的接合焊盘区域的纵轴位于同一直线上。
18.根据权利要求17所述的半导体器件，其中，所述后钝化互连结构为连续的。
19.根据权利要求17所述的半导体器件，其中，所述接合焊盘具有与所述衬底的中心对准的纵轴。
20.根据权利要求17所述的半导体器件，其中，所述凸块下金属化层的中心偏离所述接合焊盘的中心。
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