TW201735306A - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

Info

Publication number
TW201735306A
TW201735306A TW105133359A TW105133359A TW201735306A TW 201735306 A TW201735306 A TW 201735306A TW 105133359 A TW105133359 A TW 105133359A TW 105133359 A TW105133359 A TW 105133359A TW 201735306 A TW201735306 A TW 201735306A
Authority
TW
Taiwan
Prior art keywords
semiconductor substrate
layer
semiconductor
dielectric
interconnect structure
Prior art date
Application number
TW105133359A
Other languages
English (en)
Other versions
TWI648837B (zh
Inventor
陳昇照
周世培
李名哲
吳國銘
周正賢
蔡正原
杜友倫
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201735306A publication Critical patent/TW201735306A/zh
Application granted granted Critical
Publication of TWI648837B publication Critical patent/TWI648837B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05017—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05016—Shape in side view
    • H01L2224/05019—Shape in side view being a non conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05088—Shape of the additional element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/0509—Disposition of the additional element of a single via
    • H01L2224/05091—Disposition of the additional element of a single via at the center of the internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05559—Shape in side view non conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H01L2224/06182—On opposite sides of the body with specially adapted redistribution layers [RDL]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本揭露提供一種半導體結構。該半導體結構包含一半導體基板；以及一互連件結構，在該半導體基板上方。該半導體結構也包含一接墊，在該半導體基板中且耦合至該互連件結構。該接墊包含兩個導電層。

Description

半導體結構及其製造方法
本揭露係關於一種半導體結構及其製造方法。
涉及半導體裝置之電子儀器對於許多現代應用來說是必要的。於材料和設計的技術進步已產生其中各代具有比上一代更小且更複雜之電路的數代半導體裝置。在進步和創新的過程中，已普遍增加功能密度(即，每晶片面積被互連裝置的數目)，同時已減少幾何大小(即，使用成形加工製程可創建的最小組件)。此等進步已增加加工以及製造半導體裝置的複雜性。
本揭露提供一種半導體結構。該半導體結構包含一半導體基板；以及一互連件結構，在該半導體基板上方。該半導體結構也包含一接墊，在該半導體基板中且耦合至該金屬層。該接墊包含兩個導電層。 本揭露提供一種半導體結構，其包含一第一半導體裝置以及一第二半導體裝置。該第一半導體裝置包含一第一半導體基板；一第一互連件結構，在該第一半導體基板上方；一終端，在該第一半導體基板中，其中該終端係用以將該第一互連件結構與在該第一半導體基板上方的一連接件電耦合；以及一介電質，環繞該終端。該第二半導體裝置包含一第二半導體基板。該第二半導體裝置也包含一第二互連件結構，在該第二半導體基板上方且用以與該第一互連件結構接合。該終端包含一第一層，連接至該第二互連件結構；以及一第二層，在該介電質上延伸。 本揭露提供一種製造一半導體結構的方法。該方法包含：提供一第一半導體基板；形成一第一互連件結構在該第一半導體基板上方；提供一第二半導體基板；形成一第二互連件結構在該第一半導體基板上方；接合該第一互連件結構與該第二互連件結構；形成一第一通路在該第一半導體基板中，該通路暴露在該第一互連件結構中的一金屬層的一頂部表面的一部份；沉積一介電質在該第一通路中；形成一第二通路在該介電質中；沉積一第一導電層在該第二通路中；以及沉積一第二導電層在該第一導電層上方。
下列揭露提供許多用於實施所提供標的之不同特徵的不同實施例、或實例。為了簡化本揭露，於下描述組件及配置的具體實例。當然這些僅為實例而非意圖為限制性。例如，在下面說明中，形成第一特徵在第二特徵上方或上可包括其中第一及第二特徵係經形成為直接接觸之實施例，以及也可包括其中額外特徵可形成在第一與第二特徵之間而使得第一及第二特徵不可直接接觸之實施例。此外，本揭露可重複參考編號及/或字母於各種實例中。此重複係為了簡單與清楚之目的且其本身並不決定所討論的各種實施例及/或構形之間的關係。 再者，空間相關詞彙，諸如“在...之下”、“下面”、“下”、“上面”、“上”和類似詞彙，可為了使說明書便於描述如圖式繪示的一個元件或特徵與另一個（或多個）元件或特徵的相對關係而使用於本文中。除了圖式中所畫的方位外，這些空間相對詞彙也意圖用來涵蓋裝置在使用中或操作時的不同方位。該設備可以其他方式定向(旋轉90度或於其它方位)，據此在本文中所使用的這些空間相關說明符可以類似方式加以解釋。 本揭露係針對一種半導體結構，具有改善之接墊設計。該接墊係由具有較大對抗應力之抗性的材料所構成，該應力諸如在半導體結構的製造或封裝期間的拉應力或剪切應力。此外，該半導體結構展現較佳接合性質。因此，有效減輕結構裂開或剝離之風險。 圖1A係根據本揭露的一些實施例之半導體結構100的示意圖。半導體結構100包含第一半導體裝置110以及第二半導體裝置120。第一半導體裝置110包含第一半導體基板112以及第一互連件結構114。第二半導體裝置120包含第二半導體基板122以及第二互連件結構124。 第二半導體裝置120係用以實施特定功能且與第一半導體裝置110連通。在一些實施例中，第二半導體裝置120可包括邏輯電路。在一些實施例中，第二半導體裝置120可進一步包括記憶體單元或其它電氣組件。在一些實施例中，第二半導體基板122可包括無數的被動或主動組件(未顯示)，放置在面向第二互連件結構124之表面122A上。 第二半導體基板122包括半導體材料，諸如矽。在一些實施例中，第二半導體基板122可包括其他半導體材料，諸如矽鍺、碳化矽、砷化鎵、或類似物。在一些實施例中，第二半導體基板122係p型半導體基板(受體型)或n型半導體基板(施體型)。替代地，第二半導體基板122包括另一元素型半導體，諸如鍺；化合物半導體，其包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；合金半導體，其包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs，GaInP、及/或GaInAsP；或其組合。在又另一替代實施例中，第二半導體基板122係絕緣體上半導體(semiconductor on insulator，SOI)。在其他替代實施例中，第二半導體基板122可包括摻雜磊晶層、梯度半導體層、及/或在不同種類的另一半導體層上方的半導體層，諸如在矽鍺層上的矽層。 第二互連件結構124係放置在第二半導體基板122上方。在一些實施例中，第二互連件結構124係放置在第一互連件結構114與第二半導體基板122之間。第二互連件結構124係用以將在第二半導體基板122內的電氣組件電耦合。在一些實施例中，第二互連件結構124係用以將第二半導體基板122與在第二半導體裝置120外部的裝置或組件電耦合。在本實施例中，第二互連件結構124係將該第二半導體基板122與第一半導體裝置110的第一互連件結構114電耦合。第二互連件結構124可包括多個金屬層。該等金屬層之各者可包括導電絲或線且係透過至少一個金屬通路電耦合至相鄰之上覆或下方金屬層。在本實施例中，金屬層131、133、135、以及137係放置在層狀結構中且係透過對應金屬通路132、134、以及136互連。第二互連件結構124的金屬層及通路的數目及圖案係為了說明而提供。其它數目的金屬層、通路、或導電絲及替代的配線圖案也在本揭露的涵蓋範疇內。 再者，前述的金屬層及金屬通路係與其它組件電性絕緣。絕緣可藉由絕緣材料達成。在一些實施例中，第二互連件結構124的其餘部分可被金屬間介電(inter-metal dielectric，IMD)123填充。IMD 123的介電材料可以是由氧化物所形成，諸如未摻雜矽酸鹽玻璃(un-doped Silicate Glass，USG)、氟化矽酸鹽玻璃(Fluorinated Silicate Glass，FSG)、低k介電材料、或類似物。低k介電材料可具有k值低於3.8，雖然IMD 123的介電材料也可接近3.8。在一些實施例中，低k介電材料的k值係低於約3.0、以及可低於約2.5。 第一半導體裝置110係用以實施特定功能且與第二半導體裝置120連通。在一些實施例中，第一半導體裝置110可以是感測裝置，例如背面式影像(backside image，BSI)感測器裝置，用以擷取影像數據。在一些實施例中，第一半導體基板112可包括無數的被動或主動組件(未顯示)，放置在面向第一互連件結構114之表面112B上。 第一互連件結構114係抵著第一半導體基板112放置。在一些實施例中，第一互連件結構114係放置在第二互連件結構124與第一半導體基板112之間。在一些實施例中，第一互連件結構114係用以將第一半導體基板112的組件與在第一半導體裝置110外部的裝置或組件電耦合。在本實施例中，第一互連件結構114係將第一半導體基板112與第二半導體裝置120的第二互連件結構124電耦合。第一互連件結構114可包括多個金屬層。該等金屬層之各者包括至少一個導電線且係透過至少一個金屬通路電耦合至相鄰之金屬層。在本實施例中，金屬層141、143、145、以及147係放置在第一互連件結構114中且係透過金屬通路142、144、以及146互連。 在一些實施例中，互連件結構114的其餘部分可被IMD 113填充。IMD 113的介電材料可以是由氧化物所形成，諸如未摻雜矽酸鹽玻璃(USG)、氟化矽酸鹽玻璃(FSG)、低k介電材料、或類似物。低k介電材料可具有k值低於3.8，雖然IMD 113的介電材料也可接近3.8。在一些實施例中，低k介電材料的k值係低於約3.0、以及可低於約2.5。 在一些實施例中，第一互連件結構114進一步包含數個接墊154，在面向第二互連件結構124之表面114A上。在一些實施例中，第二互連件結構124包含數個接墊152，在面向第一互連件結構114之表面124A上。接墊154係對準對應接墊152，而使得第一半導體裝置110與第二半導體裝置120電接合。在一些實施例中，接墊154以及152可分別從表面114A以及124A凸出。在一些實施例中，接墊152係與表面114A齊平。在一些實施例中，接墊154係與表面124A齊平。在一些實施例中，接墊152以及154係分別與表面114A以及124A齊平，而使得表面114A係與表面124A接觸。 第一半導體基板112係放置在第一互連件結構114上面。第一半導體基板112可包括矽、矽鍺、碳化矽、砷化鎵、及/或鍺。替代地，第一半導體基板112可包括化合物半導體，其包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；合金半導體，其包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs，GaInP、及/或GaInAsP；或其組合。在一些實施例中，第一半導體基板112可由相似於第二半導體基板122之材料所形成。在一些實施例中，第一半導體基板112可包括不同於第二半導體基板122之材料。 在一些實施例中，第一半導體裝置110可包括介電層162，在半導體基板112與第一互連件結構114之間。在一些實施例中，第一半導體裝置110可包括介電層164，在半導體基板112外部但抵著半導體基板112。介電層162以及介電層164分別放置在半導體基板112的相對側上。介電質162以及164可包括各種介電材料且可以是例如，氧化物(如Ge氧化物)、氧氮化物(如GaP氧氮化物)、二氧化矽(SiO2 )、攜氮氧化物(如攜氮SiO2 )、摻雜氮之氧化物(如植入N2 之SiO2 )、矽氧氮化物(Six Oy Nz )、及類似物。在一些實施例中，介電質162係由與介電質164所具者相同之材料所形成。在一些實施例中，介電質162係由與介電質164所具者不同之材料所形成。 在一些實施例中，第一半導體基板112包括第一通路160。第一通路160係包含終端168以及介電質166。在一些實施例中，介電質166係在側向方向上環繞終端168，該側向方向實質上平行於第一半導體基板112的頂部表面112A。在一些實施例中，介電質166包括多個介電材料。替代地，介電質166包括多層結構。終端168係延伸通過半導體基板112且用以透過連接件172將第一互連件結構114與外部組件電耦合。在一些實施例中，在第一通路160中的介電質166包括第二通路160'。終端168係放置在第二通路160'中。介電質166係在側向方向上環繞第二通路160'，該側向方向實質上平行於第一半導體基板112的頂部表面112A。在一些實施例中，終端168將連接件172與第一互連件結構114的金屬層141電連接。在一些實施例中，連接件172係焊線或焊料凸塊。 在一些實施例中，半導體結構100可包括凸塊下金屬(under bump metallurgy，UBM)174，在第一通路160與連接件172之間。UBM 174係用以提供連接件172的較佳黏著。在一些實施例中，UBM 174覆蓋第一通路160。在一些實施例中，UBM 174包括頂部表面，其高於介電層164的頂部表面。 圖1B係根據本揭露的一些實施例之圖1A中半導體結構100的一部份的放大示意圖。具體地，係更詳細記地說明第一半導體裝置110。在一些實施例中，第一半導體基板112進一步包含介電質167。在一些實施例中，介電質167係在第一通路160中且沿著第一通路160的側壁內襯。在一些實施例中，介電質167係從側向方向環繞介電質166以及終端168，該側向方向實質上平行於第一半導體基板112的頂部表面112A。參考圖1B，介電質167係環繞介電質166的側面以及底面。 在一些實施例中，第一半導體基板112進一步包含介電質165。介電質165的一部分係在第一通路160中。介電質165係放置在介電質162與介電質167的底面之間。在一些實施例中，介電質165具有頂部表面，其包括大於第一通路160的截面積之面積。在本實施例中，終端168係與金屬層141電連接且穿通過介電質166、167、162、以及165。換言之，終端168在側向方向上被介電質166、167、162、以及165所環繞，該側向方向實質上平行於頂部表面112A。 在一些實施例中，金屬層141包括導電材料，諸如金、銀、以及鎢。金屬層141包括從垂直於表面112A的方向測量的厚度T。在一些實施例中，厚度T係自約500埃(Å)至約3000 Å。在一些實施例中，厚度T係自約1000 Å至約3000 Å。在一些實施例中，厚度T係自約1000 Å至約2000 Å。 在一些實施例中，終端168作為導電插塞，將連接件172與第一互連件結構114電耦合。在一些實施例中，終端168可以是接墊。接墊168具有從底部表面168B至頂部表面168A測量的高度H。在一些實施例中，高度H可以是自約16,000 Å至約35,000 Å。在一些實施例中，高度H可以是自約20,000 Å至約30,000 Å。在一些實施例中，高度H可以是自約24,000 Å至約28,000 Å。 介電質166具有頂部表面166A。在一些實施例中，頂部表面166A具有平坦形狀。在一些實施例中，頂部表面166A具有彎曲形狀，諸如內凹表面。在本實施例中，頂部表面166A具有朝上的內凹表面。頂部表面166A的彎曲形狀可以是由於平坦化製程，諸如化學機械研磨(chemical mechanical polishing，CMP)操作的碟化效果所致。 在一些實施例中，介電質167包括頂部表面167A。在一些實施例中，頂部表面167A包括平坦形狀。在一些實施例中，頂部表面167A包括彎曲形狀，諸如內凹形狀。例如，頂部表面167A可包括朝上的內凹形狀。 在一些實施例中，頂部表面168A具有平坦形狀。在一些實施例中，頂部表面168A具有彎曲形狀。在一些實施例中，頂部表面168A具有內凹形狀，諸如朝下的內凹形狀。 在一些實施例中，接墊168具有側壁168C，與介電質166接面。接墊168具有沿著側壁168C的頂部水平測量的頂部寬度W1，以及沿著底部表面168B測量的底部寬度W2。在一些實施例中，頂部寬度W1大於底部寬度W2。在一些實施例中，從頂部表面168A至底部表面168B，接墊168包括漸縮形狀(或錐形)。 在一些實施例中，頂部表面168A低於介電質166的頂部表面166A。在一些實施例中，頂部表面168A與介電質166的頂部表面166A相會。在一些實施例中，頂部表面168A低於介電質164的頂部表面112A。在一些實施例中，頂部表面168A實質上與介電質164的頂部表面112A共平面或齊平。在一些實施例中，頂部表面168A低於介電質167的頂部表面167A。 接墊168係在底部表面168B電耦合至金屬層141。在一些實施例中，接墊168經由單一接點168B耦合至金屬層141。在一些實施例中，接墊168包含與金屬層141接觸的平坦底部表面168B。 接墊168包含至少兩個層。在本實施例中，接墊168包含第一層169以及第二層170。第一層169係耦合至第一互連件結構114的金屬層141。在一些實施例中，從剖面圖第一層169包括漸縮形狀(或錐形)。在一些實施例中，第一層169可包括導電材料，具有楊氏模數係自約150千兆帕斯卡(GPa)至約250 Gpa。在一些實施例中，第一層169可包括導電材料，具有楊氏模數係自約180 GPa至約220 GPa。在一些實施例中，第一層169可包括導電材料，具有楊氏模數係自約190 GPa至約210 GPa。在一些實施例中，第一層169可包括金屬，諸如金、銀、銅、鎢、或鎳。 在一些實施例中，第一層169可包括具有重量百分比濃度係自約85%至約100%之導電材料。在一些實施例中，第一層169可包括具有重量百分比濃度係自約90%至約100%之導電材料。在一些實施例中，第一層169可包括具有重量百分比濃度係自約93%至約95%之導電材料。在一些實施例中，第一層169的導電材料包括金、銀、銅、鎢、或鎳。 第一層169包括從底部表面168B至上表面169A測量的高度H1。在一些實施例中，高度H1係自約15,000 Å至約30,000 Å。在一些實施例中，高度H1係自約15,000 Å至約25,000 Å。在一些實施例中，高度H1係自約20,000 Å至約25,000 Å。 第二層170係將第一層169與UBM 174電連接。在一些實施例中，第二層170係從介電層166暴露出。第二層170具有頂部表面，其係接墊168的頂部表面且被標作168A。在一些實施例中，第二層170的頂部表面168A與介電質166的頂部表面166A相會。在一些實施例中，頂部表面168A低於介電質166的頂部表面166A。在一些實施例中，第二層170包括四邊形形狀。在一些實施例中，第二層170包括梯形形狀。 在一些實施例中，第二層170的頂部表面168A具有平坦形狀。在一些實施例中，第二層的頂部表面168A具有彎曲形狀。在一些實施例中，第二層的頂部表面168A具有內凹形狀，諸如朝下的內凹形狀。 在一些實施例中，第二層170可包括導電材料，具有楊氏模數係自約50 GPa至約120 GPa。在一些實施例中，第二層170可包括導電材料，具有楊氏模數係自約60 GPa至約100 GPa。在一些實施例中，第二層170可包括導電材料，具有楊氏模數係自約70 GPa至約80 GPa。在一些實施例中，第二層170可包括金屬，諸如金、銀、銅、鎢、或鎳。 在一些實施例中，第二層170可包括具有重量百分比濃度係自約95%至約100%之導電材料。在一些實施例中，第二層170可包括具有重量百分比濃度係自約99%至約100%之導電材料。在一些實施例中，第二層170可包括金屬，諸如金、銀、銅、鎢、或鎳。 第二層170包括從表面169A至上表面168A測量的高度H2。在該等實施例中，高度H2係自約500 Å至約3000 Å。在該等實施例中，高度H2係自約1000 Å至約3000 Å。在該等實施例中，高度H2係自約1000 Å至約2000 Å。 在一些實施例中，在第一層169與第二層170之間的楊氏模數比值係自約1.5至約3.5。在一些實施例中，在第一層169與第二層170之間的楊氏模數比值係自約2.0至約3.0。在一些實施例中，在第一層169與第二層170之間的楊氏模數比值係自約2.4至約2.6。 圖1C係根據本揭露的一些實施例之圖1A中半導體結構100的一部份的放大示意圖。具體地，係更詳細記地說明第一半導體裝置110。參考圖1C，頂部表面168A高於介電質166的頂部表面166A。在一些實施例中，頂部表面168A高於介電質164的頂部表面112A。在一些實施例中，頂部表面168A高於介電質167的頂部表面167A。在一些實施例中，接墊168的一部份覆蓋介電質166的一部份。在一些實施例中，接墊168的帽蓋部份在介電質166上方延伸。在一些實施例中，接墊168的帽蓋部分沿著平行於第一半導體基板112的頂部表面112A的方向延伸。在一些實施例中，介電質166係部分被UBM 174覆蓋且部分被接墊168覆蓋。 在一些實施例中，第二層170覆蓋介電質166的頂部表面166A的一部份。在一些實施例中，第二介電層170在介電層166上方延伸。在一些實施例中，第二層170的頂部表面168A具有平坦形狀。在一些實施例中，第二層170的頂部表面168A具有彎曲形狀，諸如內凹形狀。在一些實施例中，上表面169A與側壁168C的頂部水平相會，而使得第二層170高於介電質166的頂部表面166A。在一些實施例中，第二層170的帽蓋部分包括四邊形形狀。在一些實施例中，第二層170的帽蓋部分包括梯形形狀。在一些實施例中，第二層170的帽蓋部份覆蓋介電質166的一部份。 圖2A至圖2Q係根據本揭露的一些實施例顯示在各種階段成形加工之圖1A之半導體結構100的剖面圖。在圖2A中，係提供第一半導體基板112。在一些實施例中，感測裝置(未顯示)的至少一個結構可形成在第一半導體基板112中。第一半導體基板112具有第一摻雜物型，諸如p型。 在一些實施例中，介電質162係整片沉積在第一半導體基板112的最頂水平。介電質162可藉由氣相沉積或旋轉塗佈形成。"氣相沉積"係指透過蒸氣相沉積材料在基板上的製程。氣相沉積製程包括任何製程，諸如但不限於化學氣相沉積(chemical vapor deposition，CVD)以及物理氣相沉積(physical vapor deposition，PVD)。氣相沉積方法的實例包括熱絲CVD、射頻CVD(radio-frequency CVD，rf-CVD)、雷射CVD(laser CVD，LCVD)、共形鑽石塗佈製程、金屬-有機CVD(metal-organic CVD，MOCVD)、濺鍍、熱蒸發PVD、離子化金屬PVD(ionized metal PVD，IMPVD)、電子束PVD(electron beam PVD，EBPVD)、反應性PVD、原子層沉積(atomic layer deposition，ALD)、電漿增強CVD(plasma-enhanced CVD，PECVD)、高密度電漿CVD(high-density plasma CVD，HDPCVD)、低壓CVD(low-pressure CVD，LPCVD)、及類似物。在一些實施例中，介電質162包括氧化矽或氮化矽。在一些實施例中，介電質162的最上水平也用以作為鈍化層。 參考圖2B，第一互連件結構114係形成在第一半導體基板112上方。第一互連件結構114可由從底層往頂層堆疊之金屬層所形成。例如，金屬層147係藉由沉積遮罩層(未分開顯示)在第一半導體基板112上所形成。遮罩層係透過蝕刻操作圖案化，以形成用於金屬層141的所欲圖案。接著，將導電材料填充在經蝕刻圖案中。在圖案被導電材料填充之後，係藉由移除操作剝除遮罩層。可將IMD材料113填充在金屬層141的導電材料間。類似地，導電通路層142係形成在金屬層141上方，以在金屬層141與上覆金屬層142之間產生導電連接。金屬層143、145以及147係依序伴隨著中介導電通路層144以及146形成。金屬層147的一部份係從第一互連件結構114暴露出。 參考圖2C，數個接墊154係在第一互連件結構114的最頂水平形成。在一些實施例中，接墊154之各者具有頂部表面154A，高於IMD 113的頂部表面113A。在一些實施例中(未顯示)，頂部表面113A可經組態以與頂部表面154A齊平，而使得第一互連件結構114具有圖1A的經平坦化頂部表面114A。第一半導體基板112以及第一互連件結構114係構成第一半導體裝置110。 圖2D至圖2F係根據本揭露的一些實施例顯示在各種階段成形加工之第二半導體裝置120的剖面圖。第二半導體基板122係如圖2D所顯示般提供。在一些實施例中，至少一個主動或被動結構(未顯示)可形成在第二半導體基板122中。第二半導體基板122具有第一摻雜物型，諸如p型。 參考圖2E，第二互連件結構124係形成在第二半導體基板122上方。第二互連件結構124可由堆疊之金屬層所形成。在一些實施例中，第二互連件結構124係從底部往頂部形成，其中此種製程係相似於第一互連件結構114的形成。例如，金屬層131、133、135以及137係在彼此上方伴隨著對應中介導電通路層132、134以及136形成。IMD 123被填充在前述金屬層間以完成第二互連件結構124。金屬層131的一部份係從第一互連件結構114暴露出。 參考圖2F，數個接墊152係在第二互連件結構124的最頂水平形成。在一些實施例中，接墊152之各者具有頂部表面152A，高於IMD 123的頂部表面123A。在一些實施例中(未顯示)，頂部表面123A可經組態以與頂部表面152A齊平，而使得第二互連件結構124具有圖1A的經平坦化頂部表面124A。第二半導體基板122以及第二互連件結構124係構成第二半導體裝置120。 如圖2G所顯示，第一半導體裝置110被倒置並與半導體裝置120接合。接墊154係與對應接墊152電接合。 參考圖2H，第一半導體基板112被往下薄化。被薄化之半導體基板112係被薄化至從底部表面112C至頂部表面112A測量的厚度L。在一些實施例中，厚度L係自約20微米(um)至約500um。在一些實施例中，厚度L係自約20um至約300um。在一些實施例中，厚度L係自約40um至約120um。 在圖2I中，介電質164係形成在第一半導體裝置110上方。在一些實施例中，介電質164可用以作為鈍化層。在一些實施例中，介電質164包括氧化矽或氮化矽。介電質164可藉由沉積操作形成，諸如熱絲CVD、rf-CVD、雷射CVD(LCVD)、共形鑽石塗佈製程、MOCVD、熱蒸發PVD、HDPCVD、LPCVD、及類似物。 在圖2J中，第一通路160係形成在第一半導體基板112中。第一通路160可藉由遮罩層之沉積形成。遮罩層可以是光阻遮罩或硬遮罩，諸如氮化物。接著，以該遮罩層就地實施蝕刻操作。第一通路160係藉由合適的蝕刻製程諸如乾式蝕刻操作形成。在一些實施例中，本操作中之乾式蝕刻包括採用含氟氣體的反應性離子蝕刻(reactive ion etch，RIE)。在完成第一通路160之後，移除遮罩層。 在圖2K中，介電材料167係共形地形成在第一半導體基板112上方。在一些實施例中，介電材料167係與介電質164所具者不同之材料。在一些實施例中，介電質167係形成在介電質164以及第一通路160的側壁與底部表面上方。介電質167可藉由合適的沉積製程形成，諸如CVD或PVD操作。 在圖2L中，介電材料182係整片沉積在介電質167上方。介電材料182係填充第一通路160。在一些實施例中，介電材料182係與介電質167所具者不同。在一些實施例中，介電材料182係與介電質164所具者不同。 在圖2M中，係實施移除操作以移除在介電層164上面的過多材料。在移除操作之後，介電質167的一部份被留在第一通路160的側壁與底部表面上。結果，介電質166係形成在第一通路160中。亦藉由該移除操作暴露出介電質164。在一些實施例中，該移除操作可藉由合適的製程實施，諸如化學機械研磨(CMP)操作。在一些實施例中，經填充之第一通路160的頂部表面的一部份(其包括表面166A及167A)可包括由於碟化效果所致的彎曲表面。在一些實施例中，第一通路160的頂部表面可包括內凹形狀，諸如朝上的內凹形狀。因此，介電質166可包括頂部表面166A，具有彎曲形狀。例如，頂部表面166A可包括朝上的內凹形狀。在一些實施例中，介電質167可包括頂部表面167A，具有彎曲形狀。例如，頂部表面167A可包括朝上的內凹形狀。 在圖2N中，第二通路160'係形成在介電質166中。第二通路160'係向下延伸並暴露出金屬層141。第二通路160'可藉由遮罩層之沉積形成。接著，以該遮罩層就地實施蝕刻操作。第二通路160'係藉由合適的蝕刻製程諸如乾式蝕刻操作形成。在一些實施例中，本操作中之乾式蝕刻包括採用含氟氣體的反應性離子蝕刻RIE。在完成第二通路160'之後，移除遮罩層。 參考圖2O，第一層169係形成在第二通路160'中。第一層169可藉由各種技術形成，如電鍍、無電式電鍍、高密度離子化金屬電漿(ionized metal plasma，IMP)沉積、高密度電感耦合電漿(inductively coupled plasma，ICP)沉積、濺鍍、PVD、CVD、LPCVD、電漿增強化學氣相沈積(PECVD)、及類似物。 參考圖2P，第二層170係形成在第二通路160'上方。亦，第二層170係形成在第一層169上。第二層170可藉由各種技術形成，如電鍍、無電式電鍍、高密度離子化金屬電漿(IMP)沉積、高密度電感耦合電漿(ICP)沉積、濺鍍、PVD、CVD、LPCVD、電漿增強化學氣相沈積(PECVD)、及類似物。 參考圖2Q，UBM 174係形成在第一通路160上方。在一些實施例中，UBM 174覆蓋介電質164的一部份。接著，連接件172係形成在UBM 174上方。 鑒於前述，本揭露提供一種半導體結構，其中係提出改善之接墊，以增進對抗外來應力之結構抗性。該接墊可包含至少兩層導電材料。該接墊係放置在通路中。在該接墊的兩層中，第一層包含導電材料，諸如鎳。亦，第二層包含導電材料，諸如金。此外，第二層包含帽蓋部分，覆蓋該通路。因此，該接墊展現較大應力抗性。據此減輕結構裂開或剝離之風險。 本揭露提供一種半導體結構。該半導體結構包含一半導體基板；以及一互連件結構，在該半導體基板上方。該半導體結構也包含一接墊，在該半導體基板中且耦合至該金屬層。該接墊包含兩個導電層。 本揭露提供一種半導體結構，其包含一第一半導體裝置以及一第二半導體裝置。該第一半導體裝置包含一第一半導體基板；一第一互連件結構，在該第一半導體基板上方；一終端，在該第一半導體基板中，其中該終端係用以將該第一互連件結構與在該第一半導體基板上方的一連接件電耦合；以及一介電質，環繞該終端。該第二半導體裝置包含一第二半導體基板。該第二半導體裝置也包含一第二互連件結構，在該第二半導體基板上方且用以與該第一互連件結構接合。該終端包含一第一層，連接至該第二互連件結構；以及一第二層，在該介電質上延伸。 本揭露提供一種製造一半導體結構的方法。該方法包含：提供一第一半導體基板；形成一第一互連件結構在該第一半導體基板上方；提供一第二半導體基板；形成一第二互連件結構在該第一半導體基板上方；接合該第一互連件結構與該第二互連件結構；形成一第一通路在該第一半導體基板中，該通路暴露在該第一互連件結構中的一金屬層的一頂部表面的一部份；沉積一介電質在該第一通路中；形成一第二通路在該介電質中；沉積一第一導電層在該第二通路中；以及沉積一第二導電層在該第一導電層上方。 前面列述了數個實施例的特徵以便本技術領域具有通常知識者可更佳地理解本揭露之態樣。本技術領域具有通常知識者應了解他們可輕易地使用本揭露作為用以設計或修改其他製程及結構之基礎以實現本文中所介紹實施例的相同目的及/或達成本文中所介紹實施例的相同優點。本技術領域具有通常知識者也應體認到此等均等構造不會悖離本揭露之精神及範疇，以及他們可在不悖離本揭露之精神及範疇下做出各種改變、取代、或替代。
100‧‧‧半導體結構
110‧‧‧第一半導體裝置
112‧‧‧第一半導體基板
112A、166A‧‧‧頂部表面/表面
112B、122A‧‧‧表面
112C‧‧‧底部表面
113‧‧‧金屬間介電(IMD)/IMD材料
113A、123A、152A、‧‧‧頂部表面
154A、167A 114‧‧‧第一互連件結構
114A、124A‧‧‧表面
120‧‧‧第二半導體裝置
122‧‧‧第二半導體基板
123‧‧‧金屬間介電(IMD)
124‧‧‧第二互連件結構
131、133、135、137、‧‧‧金屬層
141、143、145、147 132、134、136、144、146‧‧‧金屬通路/中介導電通路層
142‧‧‧金屬通路/導電通路層/上覆金屬層
152、154‧‧‧接墊
160‧‧‧第一通路
160'‧‧‧第二通路
162、164‧‧‧介電層/介電質
165、166‧‧‧介電質
167‧‧‧介電材料/介電質
168‧‧‧終端/接墊
168A‧‧‧頂部表面/上表面
168B‧‧‧底部表面/單一接點
168C‧‧‧側壁
169‧‧‧第一層
169A‧‧‧表面/上表面
170‧‧‧第二層
172‧‧‧連接件
174‧‧‧凸塊下金屬(UBM)
182‧‧‧介電材料
H、H1、H2 ‧‧‧高度
W1‧‧‧頂部寬度
W2‧‧‧底部寬度
T、L‧‧‧厚度
本揭露之態樣將在與隨附圖式一同閱讀下列詳細說明下被最佳理解。請注意，根據業界標準作法，各種特徵未依比例繪製。事實上，為了使討論內容清楚，各種特徵的尺寸可刻意放大或縮小。 圖1A係根據本揭露的一些實施例之半導體結構的示意圖。 圖1B係根據本揭露的一些實施例之半導體結構的示意圖。 圖1C係根據本揭露的一些實施例之半導體結構的示意圖。 圖2A至2Q係根據本揭露的一些實施例製造半導體結構的示意圖。
100‧‧‧半導體結構
110‧‧‧第一半導體裝置
112‧‧‧第一半導體基板
112A‧‧‧頂部表面/表面
112B、122A‧‧‧表面
113‧‧‧金屬間介電層(IMD)/IMD材料
114‧‧‧第一互連件結構
114A、124A‧‧‧經平坦化頂部表面/表面
120‧‧‧第二半導體裝置
122‧‧‧第二半導體基板
123‧‧‧金屬間介電(IMD)
124‧‧‧第二互連件結構
131、133、135、137、141、143、145、147‧‧‧金屬層
132、134、136、144、146‧‧‧金屬通路/中介導電通路層
142‧‧‧金屬通路/導電通路層/上覆金屬層
152、154‧‧‧接墊
160‧‧‧第一通路
160'‧‧‧第二通路
162、164‧‧‧介電層/介電質
166‧‧‧介電質
168‧‧‧終端/接墊
172‧‧‧連接件
174‧‧‧凸塊下金屬(UBM)

Claims (10)

  1. 一種半導體結構，其包含： 一半導體基板； 一互連件結構，在該半導體基板上方；以及 一接墊，在該半導體基板中且耦合至該互連件結構，該接墊包含兩個導電層。
  2. 如請求項1之半導體結構，其中該接墊包含一導電材料，具有楊氏模數係自約180千兆帕斯卡(GPa)至約220 GPa。
  3. 如請求項1之半導體結構，其中該接墊包含一金層，在一鎳層上方，該金層係用以連接至一焊料凸塊。
  4. 如請求項1之半導體結構，其中在該兩個導電層之間的一楊氏模數比值係自約1.5至約3.5。
  5. 如請求項1之半導體結構，其中該半導體基板包含一通路，以及該接墊係放置在該通路中。
  6. 如請求項1之半導體結構，其中該接墊包含一帽蓋部分，沿著實質上平行於該第一半導體基板的一頂部表面的一方向延伸。
  7. 如請求項1之半導體結構，其中該接墊包含一漸縮形狀。
  8. 如請求項1之半導體結構，進一步包含一介電質，在一側向方向上環繞該接墊，其中該側向方向係實質上平行於該第一半導體基板的一頂部表面。
  9. 一種半導體結構，其包含： 一第一半導體裝置，其包含： 一第一半導體基板； 一第一互連件結構，在該第一半導體基板上方； 一終端，在該第一半導體基板中，該終端係用以將該第一互連件結構與在該第一半導體基板上方的一連接件電耦合；以及 一介電質，環繞該終端；以及 一第二半導體裝置，其包含： 一第二半導體基板；以及 一第二互連件結構，在該第二半導體裝置上方且用以與該第一互連件結構接合， 該終端包含一第一層，連接至該第二互連件結構；以及一第二層，在該介電質上方延伸。
  10. 一種製造一半導體結構之方法，其包含： 提供一第一半導體基板； 形成一第一互連件結構在該第一半導體基板上方； 形成一第一通路在該第一半導體基板中，該通路暴露在該第一互連件結構中的一金屬層的一頂部表面的一部份； 沉積一介電質在該第一通路中； 沉積一第一導電層在該第一通路中；以及 沉積一第二導電層在該第一導電層上方， 在該第一導電層與該第二導電層之間的一楊氏模數比值係約1.5至約3.5。
TW105133359A 2015-12-31 2016-10-14 半導體結構及其製造方法 TWI648837B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562273461P 2015-12-31 2015-12-31
US62/273,461 2015-12-31
US15/156,764 2016-05-17
US15/156,764 US9786619B2 (en) 2015-12-31 2016-05-17 Semiconductor structure and manufacturing method thereof

Publications (2)

Publication Number Publication Date
TW201735306A true TW201735306A (zh) 2017-10-01
TWI648837B TWI648837B (zh) 2019-01-21

Family

ID=59226802

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105133359A TWI648837B (zh) 2015-12-31 2016-10-14 半導體結構及其製造方法

Country Status (3)

Country Link
US (3) US9786619B2 (zh)
CN (1) CN107039394B (zh)
TW (1) TWI648837B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6800788B2 (ja) * 2017-03-15 2020-12-16 キオクシア株式会社 半導体記憶装置
US20180342473A1 (en) * 2017-05-25 2018-11-29 Advanced Semiconductor Engineering, Inc. Via structure, substrate structure including the same, and method for manufacturing the same
US10867891B2 (en) * 2018-10-24 2020-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Ion through-substrate via
US11955444B2 (en) * 2021-03-12 2024-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7056820B2 (en) * 2003-11-20 2006-06-06 International Business Machines Corporation Bond pad
US6992389B2 (en) * 2004-04-28 2006-01-31 International Business Machines Corporation Barrier for interconnect and method
KR101295551B1 (ko) 2006-07-14 2013-08-12 삼성디스플레이 주식회사 광조절 조립체와 이의 제조방법 및 이를 포함하는액정표시장치
JP5034740B2 (ja) * 2007-07-23 2012-09-26 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US8034702B2 (en) * 2007-08-16 2011-10-11 Micron Technology, Inc. Methods of forming through substrate interconnects
US8932906B2 (en) * 2008-08-19 2015-01-13 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via bonding structure
US8552563B2 (en) * 2009-04-07 2013-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional semiconductor architecture
US8275118B2 (en) 2009-08-28 2012-09-25 Rockstar Bidco, L.P. Method and system for controlling establishment of communication channels in a contact centre
US8492878B2 (en) * 2010-07-21 2013-07-23 International Business Machines Corporation Metal-contamination-free through-substrate via structure
US8330274B2 (en) * 2010-09-29 2012-12-11 Infineon Technologies Ag Semiconductor structure and method for making same
US20120193785A1 (en) * 2011-02-01 2012-08-02 Megica Corporation Multichip Packages
US8487410B2 (en) * 2011-04-13 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon vias for semicondcutor substrate and method of manufacture
US8373282B2 (en) * 2011-06-16 2013-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package with reduced stress on solder balls
US8593334B2 (en) 2011-07-29 2013-11-26 The Boeing Company Split aperture monopulse antenna system
US8742574B2 (en) * 2011-08-09 2014-06-03 Maxim Integrated Products, Inc. Semiconductor device having a through-substrate via
US8803316B2 (en) * 2011-12-06 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. TSV structures and methods for forming the same
US8742591B2 (en) * 2011-12-21 2014-06-03 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer in notches around conductive TSV for stress relief
US9058455B2 (en) * 2012-01-20 2015-06-16 International Business Machines Corporation Backside integration of RF filters for RF front end modules and design structure
KR101867961B1 (ko) * 2012-02-13 2018-06-15 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법
KR101916225B1 (ko) * 2012-04-09 2018-11-07 삼성전자 주식회사 Ｔｓｖ를 구비한 반도체 칩 및 그 반도체 칩 제조방법
US8865585B2 (en) * 2012-07-11 2014-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming post passivation interconnects
US9076785B2 (en) * 2012-12-11 2015-07-07 Invensas Corporation Method and structures for via substrate repair and assembly
JP6195102B2 (ja) 2013-02-28 2017-09-13 キョーラク株式会社 包装袋
US9041206B2 (en) * 2013-03-12 2015-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method
US9142501B2 (en) * 2013-03-14 2015-09-22 International Business Machines Corporation Under ball metallurgy (UBM) for improved electromigration
US20140332952A1 (en) * 2013-05-09 2014-11-13 United Microelectronics Corp. Semiconductor structure and method for testing the same
KR102136844B1 (ko) * 2013-09-30 2020-07-22 삼성전자 주식회사 웨이퍼 가공 방법 및 그 가공 방법을 이용한 반도체 소자 제조방법
KR102094473B1 (ko) * 2013-10-15 2020-03-27 삼성전자주식회사 Ｔｓｖ 구조를 구비한 집적회로 소자 및 그 제조 방법
US9704781B2 (en) * 2013-11-19 2017-07-11 Micron Technology, Inc. Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods
KR20150058940A (ko) * 2013-11-21 2015-05-29 삼성전자주식회사 히트 스프레더를 갖는 반도체 패키지
US9666520B2 (en) 2014-04-30 2017-05-30 Taiwan Semiconductor Manufactuing Company, Ltd. 3D stacked-chip package
US9299663B2 (en) * 2014-05-19 2016-03-29 Micron Technology, Inc. Semiconductor devices and methods for backside photo alignment
US20150348871A1 (en) * 2014-05-29 2015-12-03 Inotera Memories, Inc. Semiconductor device and method for manufacturing the same
KR102279729B1 (ko) * 2014-12-01 2021-07-21 삼성전자주식회사 Ｔｓｖ, 전면 범핑 패드 및 후면 범핑 패드를 갖는 반도체 소자
KR20160080526A (ko) * 2014-12-29 2016-07-08 삼성전기주식회사 인쇄회로기판 및 그 제조방법
KR102379165B1 (ko) * 2015-08-17 2022-03-25 삼성전자주식회사 Tsv 구조를 구비한 집적회로 소자 및 그 제조 방법
US9780052B2 (en) * 2015-09-14 2017-10-03 Micron Technology, Inc. Collars for under-bump metal structures and associated systems and methods
US9553058B1 (en) * 2015-09-15 2017-01-24 Globalfoundries Inc. Wafer backside redistribution layer warpage control
KR20170050678A (ko) * 2015-10-30 2017-05-11 삼성전자주식회사 Tsv 구조를 구비한 집적회로 소자 및 그 제조 방법
US10242968B2 (en) * 2015-11-05 2019-03-26 Massachusetts Institute Of Technology Interconnect structure and semiconductor structures for assembly of cryogenic electronic packages
KR102570582B1 (ko) * 2016-06-30 2023-08-24 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
KR102605618B1 (ko) * 2016-11-14 2023-11-23 삼성전자주식회사 이미지 센서 패키지

Also Published As

Publication number Publication date
US20180033749A1 (en) 2018-02-01
CN107039394B (zh) 2020-05-15
US10522487B2 (en) 2019-12-31
CN107039394A (zh) 2017-08-11
US20170194273A1 (en) 2017-07-06
US20200144207A1 (en) 2020-05-07
US9786619B2 (en) 2017-10-10
US11189583B2 (en) 2021-11-30
TWI648837B (zh) 2019-01-21

Similar Documents

Publication Publication Date Title
JP5271985B2 (ja) 集積回路構造
TWI553824B (zh) 具有再分配線的堆疊式積體電路以及其形成方法
US9953941B2 (en) Conductive barrier direct hybrid bonding
US11791243B2 (en) Semiconductor device and method of manufacture
TWI492354B (zh) 半導體裝置及其製造方法
TWI416693B (zh) 半導體裝置及其製造方法
US8513119B2 (en) Method of forming bump structure having tapered sidewalls for stacked dies
US8450206B2 (en) Method of forming a semiconductor device including a stress buffer material formed above a low-k metallization system
US8097953B2 (en) Three-dimensional integrated circuit stacking-joint interface structure
US11189583B2 (en) Semiconductor structure and manufacturing method thereof
JP2010045371A (ja) 導電性保護膜を有する貫通電極構造体及びその形成方法
CN101740484A (zh) 形成穿透硅通孔的方法
US9437578B2 (en) Stacked IC control through the use of homogenous region
TW201505140A (zh) 半導體裝置
CN109712953B (zh) 一种半导体器件的制造方法和半导体器件
CN105742193A (zh) 晶圆与晶圆接合的工艺及结构
TWI732670B (zh) 半導體結構及其形成方法
CN113644039A (zh) 半导体结构及其形成方法
TWI792433B (zh) 半導體裝置以及其製造方法
TW202410378A (zh) 具有電感器的半導體裝置及其製造方法