CN107039394B - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
CN107039394B
CN107039394B CN201611189878.XA CN201611189878A CN107039394B CN 107039394 B CN107039394 B CN 107039394B CN 201611189878 A CN201611189878 A CN 201611189878A CN 107039394 B CN107039394 B CN 107039394B
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layer
dielectric
semiconductor substrate
top surface
semiconductor
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CN107039394A (zh
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陈升照
周世培
李名哲
吴国铭
周正贤
蔡正原
杜友伦
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本揭露实施例提供一种半导体结构及其制造方法。所述半导体结构包括半导体衬底；以及互连件结构，其在所述半导体衬底上方。所述半导体结构也包括接垫，所述接垫在所述半导体衬底中且耦合到所述互连件结构。所述接垫包括两个导电层。

Description

半导体结构及其制造方法
技术领域
本揭露实施例涉及一种半导体结构及其制造方法。
背景技术
涉及半导体装置的电子仪器对于许多现代应用来说是必要的。于材料和设计的技术进步已产生其中各代具有比上一代更小且更复杂的电路的数代半导体装置。在进步和创新的过程中，已普遍增加功能密度(即，每芯片面积被互连装置的数目)，同时已减少几何大小(即，使用成形加工工艺可创建的最小组件)。此些进步已增加加工以及制造半导体装置的复杂性。
发明内容
本揭露实施例提供一种半导体结构。所述半导体结构包括半导体衬底；以及互连件结构，在所述半导体衬底上方。所述半导体结构也包括接垫，在所述半导体衬底中且耦合到所述金属层。所述接垫包括两个导电层。
本揭露实施例提供一种半导体结构，其包括第一半导体装置以及第二半导体装置。所述第一半导体装置包括第一半导体衬底；第一互连件结构，其在所述第一半导体衬底上方；端子，其在所述第一半导体衬底中，其中所述端子是用以将所述第一互连件结构与在所述第一半导体衬底上方的连接件电耦合；以及电介质，其环绕所述端子。所述第二半导体装置包括第二半导体衬底。所述第二半导体装置也包括第二互连件结构，在所述第二半导体衬底上方且用以与所述第一互连件结构接合。所述端子包括第一层，其连接到所述第二互连件结构；以及第二层，其在所述电介质上延伸。
本揭露实施例提供一种制造半导体结构的方法。所述方法包括：提供第一半导体衬底；在所述第一半导体衬底上方形成第一互连件结构；提供第二半导体衬底；在所述第一半导体衬底上方形成第二互连件结构；接合所述第一互连件结构与所述第二互连件结构；在所述第一半导体衬底中形成第一通路，所述通路暴露在所述第一互连件结构中的金属层的顶部表面的部分；在所述第一通路中沉积电介质；在所述电介质中形成第二通路；在所述第二通路中沉积第一导电层；以及在所述第一导电层上方沉积第二导电层。
附图说明
本揭露实施例的方面将在与随附图式一同阅读下列详细说明下被最佳理解。请注意，根据业界标准作法，各种特征未依比例绘制。事实上，为了使讨论内容清楚，各种特征的尺寸可刻意放大或缩小。
图1A为根据本揭露的一些实施例的半导体结构的示意图。
图1B为根据本揭露的一些实施例的半导体结构的示意图。
图1C为根据本揭露的一些实施例的半导体结构的示意图。
图2A到2Q为根据本揭露的一些实施例制造半导体结构的示意图。
具体实施方式
下列揭露提供许多用于实施所提供目标的不同特征的不同实施例、或实例。为了简化本揭露实施例，于下描述组件及配置的具体实例。当然这些仅为实例而非意图为限制性。例如，在下面说明中，形成第一特征在第二特征上方或上可包含其中第一及第二特征是经形成为直接接触的实施例，以及也可包含其中额外特征可形成在第一与第二特征之间而使得第一及第二特征不可直接接触的实施例。此外，本揭露实施例可重复参考编号及/或字母于各种实例中。此重复是为了简单与清楚的目的且其本身并不决定所讨论的各种实施例及/或构形之间的关系。
再者，空间相关词汇，例如“在…之下”、“下面”、“下”、“上面”、“上”和类似词汇，可为了使说明书便于描述如图式绘示的一个组件或特征与另一个(或多个)组件或特征的相对关系而使用于本文中。除了图式中所画的方位外，这些空间相对词汇也意图用来覆盖装置在使用中或操作时的不同方位。所述设备可以其他方式定向(旋转90度或于其它方位)，据此在本文中所使用的这些空间相关说明符可以类似方式加以解释。
本揭露实施例是针对一种半导体结构，具有改善的接垫设计。所述接垫是由具有较大对抗应力的抗性的材料所构成，所述应力例如在半导体结构的制造或包装期间的拉应力或剪切应力。此外，所述半导体结构展现较佳接合性质。因此，有效减轻结构裂开或剥离的风险。
图1A是根据本揭露的一些实施例的半导体结构100的示意图。半导体结构100包括第一半导体装置110以及第二半导体装置120。第一半导体装置110包括第一半导体衬底112以及第一互连件结构114。第二半导体装置120包括第二半导体衬底122以及第二互连件结构124。
第二半导体装置120是用以实施特定功能且与第一半导体装置110连通。在一些实施例中，第二半导体装置120可包含逻辑电路。在一些实施例中，第二半导体装置120可进一步包含内存单元或其它电气组件。在一些实施例中，第二半导体衬底122可包含无数的无源或有源组件(未显示)，放置在面向第二互连件结构124的表面122A上。
第二半导体衬底122包含半导体材料，例如硅。在一些实施例中，第二半导体衬底122可包含其他半导体材料，例如硅锗、碳化硅、砷化镓、或类似物。在一些实施例中，第二半导体衬底122是p型半导体衬底(受体型)或n型半导体衬底(供体型)。替代地，第二半导体衬底122包含另一元素型半导体，例如锗；化合物半导体，其包含碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟；合金半导体，其包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs，GaInP、及/或GaInAsP；或其组合。在又另一替代实施例中，第二半导体衬底122为绝缘体上半导体(semiconductor on insulator，SOI)。在其他替代实施例中，第二半导体衬底122可包含掺杂外延层、梯度半导体层、及/或在不同种类的另一半导体层上方的半导体层，例如在硅锗层上的硅层。
第二互连件结构124经放置在第二半导体衬底122上方。在一些实施例中，第二互连件结构124经放置在第一互连件结构114与第二半导体衬底122之间。第二互连件结构124是用以将在第二半导体衬底122内的电气组件电耦合。在一些实施例中，第二互连件结构124是用以将第二半导体衬底122与在第二半导体装置120外部的装置或组件电耦合。在本实施例中，第二互连件结构124是将所述第二半导体衬底122与第一半导体装置110的第一互连件结构114电耦合。第二互连件结构124可包含多个金属层。所述金属层中的各者可包含导电丝或线且是透过至少一个金属通路电耦合到相邻的上覆或下方金属层。在本实施例中，金属层131、133、135、以及137经放置在层状结构中且是透过对应金属通路132、134、以及136互连。第二互连件结构124的金属层及通路的数目及图案是为了说明而提供。其它数目的金属层、通路、或导电丝及替代的配线图案也在本揭露实施例的覆盖范围内。
再者，前述的金属层及金属通路是与其它组件电性绝缘。绝缘可通过绝缘材料达成。在一些实施例中，第二互连件结构124的其余部分可被金属间电介质(inter-metaldielectric，IMD)123填充。IMD 123的电介质材料可以是由氧化物所形成，例如未掺杂硅酸盐玻璃(un-doped Silicate Glass，USG)、氟化硅酸盐玻璃(Fluorinated SilicateGlass，FSG)、低k电介质材料、或类似物。低k电介质材料可具有k值低于3.8，虽然IMD 123的电介质材料也可接近3.8。在一些实施例中，低k电介质材料的k值为低于约3.0、以及可低于约2.5。
第一半导体装置110是用以实施特定功能且与第二半导体装置120连通。在一些实施例中，第一半导体装置110可以是感测装置，例如背面式图像(backside image，BSI)传感器装置，用以撷取图像数据。在一些实施例中，第一半导体衬底112可包含无数的无源或有源组件(未显示)，放置在面向第一互连件结构114的表面112B上。
第一互连件结构114是抵着第一半导体衬底112放置。在一些实施例中，第一互连件结构114是放置在第二互连件结构124与第一半导体衬底112之间。在一些实施例中，第一互连件结构114是用以将第一半导体衬底112的组件与在第一半导体装置110外部的装置或组件电耦合。在本实施例中，第一互连件结构114是将第一半导体衬底112与第二半导体装置120的第二互连件结构124电耦合。第一互连件结构114可包含多个金属层。所述金属层中的各者包含至少一个导电线且是透过至少一个金属通路电耦合到相邻的金属层。在本实施例中，金属层141、143、145、以及147经放置在第一互连件结构114中且是透过金属通路142、144、以及146互连。
在一些实施例中，互连件结构114的其余部分可被IMD 113填充。IMD 113的电介质材料可以是由氧化物所形成，例如未掺杂硅酸盐玻璃(USG)、氟化硅酸盐玻璃(FSG)、低k电介质材料、或类似物。低k电介质材料可具有k值低于3.8，虽然IMD 113的电介质材料也可接近3.8。在一些实施例中，低k电介质材料的k值为低于约3.0、以及可低于约2.5。
在一些实施例中，第一互连件结构114进一步包括数个接垫154，在面向第二互连件结构124的表面114A上。在一些实施例中，第二互连件结构124包括数个接垫152，在面向第一互连件结构114的表面124A上。接垫154是对准对应接垫152，而使得第一半导体装置110与第二半导体装置120电接合。在一些实施例中，接垫154以及152可分别从表面114A以及124A凸出。在一些实施例中，接垫152是与表面114A齐平。在一些实施例中，接垫154是与表面124A齐平。在一些实施例中，接垫152以及154是分别与表面114A以及124A齐平，而使得表面114A与表面124A接触。
第一半导体衬底112经放置在第一互连件结构114上面。第一半导体衬底112可包含硅、硅锗、碳化硅、砷化镓，及/或锗。替代地，第一半导体衬底112可包含化合物半导体，其包含碳化硅、砷化镓、磷化镓、磷化铟、砷化铟，及/或锑化铟；合金半导体，其包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs，GaInP，及/或GaInAsP；或其组合。在一些实施例中，第一半导体衬底112可由相似于第二半导体衬底122的材料所形成。在一些实施例中，第一半导体衬底112可包含不同于第二半导体衬底122的材料。
在一些实施例中，第一半导体装置110可包含电介质层162，在半导体衬底112与第一互连件结构114之间。在一些实施例中，第一半导体装置110可包含电介质层164，在半导体衬底112外部但抵着半导体衬底112。电介质层162以及电介质层164分别放置在半导体衬底112的相对侧上。电介质162以及164可包含各种电介质材料且可以是例如，氧化物(如Ge氧化物)、氧氮化物(如GaP氧氮化物)、二氧化硅(SiO2)、携氮氧化物(如携氮SiO2)、掺杂氮的氧化物(如植入N2的SiO2)、硅氧氮化物(SixOyNz)，及类似物。在一些实施例中，电介质162是由与电介质164所具者相同的材料所形成。在一些实施例中，电介质162是由与电介质164所具者不同的材料所形成。
在一些实施例中，第一半导体衬底112包含第一通路160。第一通路160包括端子168以及电介质166。在一些实施例中，电介质166是在侧向方向上环绕端子168，所述侧向方向基本上平行于第一半导体衬底112的顶部表面112A。在一些实施例中，电介质166包含多个电介质材料。替代地，电介质166包含多层结构。端子168是延伸通过半导体衬底112且用以透过连接件172将第一互连件结构114与外部组件电耦合。在一些实施例中，在第一通路160中的电介质166包含第二通路160'。端子168是放置在第二通路160'中。电介质166是在侧向方向上环绕第二通路160'，所述侧向方向基本上平行于第一半导体衬底112的顶部表面112A。在一些实施例中，端子168将连接件172与第一互连件结构114的金属层141电连接。在一些实施例中，连接件172为焊线或焊料凸块。
在一些实施例中，半导体结构100可包含凸块下金属(under bump metallurgy，UBM)174，在第一通路160与连接件172之间。UBM 174是用以提供连接件172的较佳粘合。在一些实施例中，UBM 174覆盖第一通路160。在一些实施例中，UBM 174包含顶部表面，其高于电介质层164的顶部表面。
图1B为根据本揭露的一些实施例的图1A中半导体结构100的部分的放大示意图。具体地，更详细地说明第一半导体装置110。在一些实施例中，第一半导体衬底112进一步包括电介质167。在一些实施例中，电介质167是在第一通路160中且沿着第一通路160的侧壁内衬。在一些实施例中，电介质167是从侧向方向环绕电介质166以及端子168，所述侧向方向基本上平行于第一半导体衬底112的顶部表面112A。参考图1B，电介质167是环绕电介质166的侧面以及底面。
在一些实施例中，第一半导体衬底112进一步包括电介质165。电介质165的一部分是在第一通路160中。电介质165经放置在电介质162与电介质167的底面之间。在一些实施例中，电介质165具有顶部表面，其包含大于第一通路160的截面积的面积。在本实施例中，端子168是与金属层141电连接且穿通过电介质166、167、162、以及165。换句话说，端子168在侧向方向上被电介质166、167、162、以及165所环绕，所述侧向方向基本上平行于顶部表面112A。
在一些实施例中，金属层141包含导电材料，例如金、银、以及钨。金属层141包含从垂直于表面112A的方向测量的厚度T。在一些实施例中，厚度T是从约500埃
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在一些实施例中，厚度T是从约
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在一些实施例中，厚度T是从约
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Figure BDA0001186984960000066
在一些实施例中，端子168作为导电插塞，将连接件172与第一互连件结构114电耦合。在一些实施例中，端子168可以是接垫。接垫168具有从底部表面168B到顶部表面168A测量的高度H。在一些实施例中，高度H可以是从约
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在一些实施例中，高度H可以是从约
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到约
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在一些实施例中，高度H可以是从约
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到约
Figure BDA00011869849600000612
电介质166具有顶部表面166A。在一些实施例中，顶部表面166A具有平坦形状。在一些实施例中，顶部表面166A具有弯曲形状，例如内凹表面。在本实施例中，顶部表面166A具有朝上的内凹表面。顶部表面166A的弯曲形状可以是由于平坦化工艺，例如化学机械抛光(chemical mechanical polishing，CMP)操作的碟化效果所致。
在一些实施例中，电介质167包含顶部表面167A。在一些实施例中，顶部表面167A包含平坦形状。在一些实施例中，顶部表面167A包含弯曲形状，例如内凹形状。例如，顶部表面167A可包含朝上的内凹形状。
在一些实施例中，顶部表面168A具有平坦形状。在一些实施例中，顶部表面168A具有弯曲形状。在一些实施例中，顶部表面168A具有内凹形状，例如朝下的内凹形状。
在一些实施例中，接垫168具有侧壁168C，与电介质166接面。接垫168具有沿着侧壁168C的顶部水平测量的顶部宽度W1，以及沿着底部表面168B测量的底部宽度W2。在一些实施例中，顶部宽度W1大于底部宽度W2。在一些实施例中，从顶部表面168A到底部表面168B，接垫168包含渐缩形状(或锥形)。
在一些实施例中，顶部表面168A低于电介质166的顶部表面166A。在一些实施例中，顶部表面168A与电介质166的顶部表面166A相会。在一些实施例中，顶部表面168A低于电介质164的顶部表面112A。在一些实施例中，顶部表面168A基本上与电介质164的顶部表面112A共平面或齐平。在一些实施例中，顶部表面168A低于电介质167的顶部表面167A。
接垫168是在底部表面168B电耦合到金属层141。在一些实施例中，接垫168经由单一接点168B耦合到金属层141。在一些实施例中，接垫168包括与金属层141接触的平坦底部表面168B。
接垫168包括至少两个层。在本实施例中，接垫168包括第一层169以及第二层170。第一层169为耦合到第一互连件结构114的金属层141。在一些实施例中，从横截面图第一层169包含渐缩形状(或锥形)。在一些实施例中，第一层169可包含导电材料，具有杨氏模数是从约150千兆帕斯卡(GPa)到约250Gpa。在一些实施例中，第一层169可包含导电材料，具有杨氏模数是从约180GPa到约220GPa。在一些实施例中，第一层169可包含导电材料，具有杨氏模数是从约190GPa到约210GPa。在一些实施例中，第一层169可包含金属，例如金、银、铜、钨、或镍。
在一些实施例中，第一层169可包含具有重量百分比浓度是从约85％到约100％的导电材料。在一些实施例中，第一层169可包含具有重量百分比浓度是从约90％到约100％的导电材料。在一些实施例中，第一层169可包含具有重量百分比浓度是从约93％到约95％的导电材料。在一些实施例中，第一层169的导电材料包含金、银、铜、钨、或镍。
第一层169包含从底部表面168B到上表面169A测量的高度H1。在一些实施例中，高度H1是从约
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在一些实施例中，高度H1是从约
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在一些实施例中，高度H1是从约
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第二层170是将第一层169与UBM 174电连接。在一些实施例中，第二层170是从电介质层166暴露出。第二层170具有顶部表面，其是接垫168的顶部表面且被标作168A。在一些实施例中，第二层170的顶部表面168A与电介质166的顶部表面166A相会。在一些实施例中，顶部表面168A低于电介质166的顶部表面166A。在一些实施例中，第二层170包含四边形形状。在一些实施例中，第二层170包含梯形形状。
在一些实施例中，第二层170的顶部表面168A具有平坦形状。在一些实施例中，第二层的顶部表面168A具有弯曲形状。在一些实施例中，第二层的顶部表面168A具有内凹形状，例如朝下的内凹形状。
在一些实施例中，第二层170可包含导电材料，具有杨氏模数是从约50GPa到约120GPa。在一些实施例中，第二层170可包含导电材料，具有杨氏模数是从约60GPa到约100GPa。在一些实施例中，第二层170可包含导电材料，具有杨氏模数是从约70GPa到约80GPa。在一些实施例中，第二层170可包含金属，例如金、银、铜、钨、或镍。
在一些实施例中，第二层170可包含具有重量百分比浓度是从约95％到约100％的导电材料。在一些实施例中，第二层170可包含具有重量百分比浓度是从约99％到约100％的导电材料。在一些实施例中，第二层170可包含金属，例如金、银、铜、钨、或镍。
第二层170包含从表面169A到上表面168A测量的高度H2。在所述实施例中，高度H2是从约
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在所述实施例中，高度H2是从约
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在所述实施例中，高度H2是从约
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Figure BDA0001186984960000086
在一些实施例中，在第一层169与第二层170之间的杨氏模数比值是从约1.5到约3.5。在一些实施例中，在第一层169与第二层170之间的杨氏模数比值是从约2.0到约3.0。在一些实施例中，在第一层169与第二层170之间的杨氏模数比值是从约2.4到约2.6。
图1C是根据本揭露的一些实施例的图1A中半导体结构100的部分的放大示意图。具体地，更详细记地说明第一半导体装置110。参考图1C，顶部表面168A高于电介质166的顶部表面166A。在一些实施例中，顶部表面168A高于电介质164的顶部表面112A。在一些实施例中，顶部表面168A高于电介质167的顶部表面167A。在一些实施例中，接垫168的部分覆盖电介质166的部分。在一些实施例中，接垫168的帽盖部分在电介质166上方延伸。在一些实施例中，接垫168的帽盖部分沿着平行于第一半导体衬底112的顶部表面112A的方向延伸。在一些实施例中，电介质166是部分被UBM 174覆盖且部分被接垫168覆盖。
在一些实施例中，第二层170覆盖电介质166的顶部表面166A的部分。在一些实施例中，第二电介质层170在电介质层166上方延伸。在一些实施例中，第二层170的顶部表面168A具有平坦形状。在一些实施例中，第二层170的顶部表面168A具有弯曲形状，例如内凹形状。在一些实施例中，上表面169A与侧壁168C的顶部水平相会，而使得第二层170高于电介质166的顶部表面166A。在一些实施例中，第二层170的帽盖部分包含四边形形状。在一些实施例中，第二层170的帽盖部分包含梯形形状。在一些实施例中，第二层170的帽盖部分覆盖电介质166的部分。
图2A到图2Q为根据本揭露的一些实施例显示在各种阶段成形加工的图1A的半导体结构100的横截面图。在图2A中，提供第一半导体衬底112。在一些实施例中，感测装置(未显示)的至少一个结构可形成在第一半导体衬底112中。第一半导体衬底112具有第一掺杂物型，例如p型。
在一些实施例中，电介质162是整片沉积在第一半导体衬底112的最顶水平。电介质162可通过气相沉积或旋转涂布形成。“气相沉积”是指透过蒸气相沉积材料在衬底上的工艺。气相沉积工艺包含任何工艺，例如但不限于化学气相沉积(chemical vapordeposition，CVD)以及物理气相沉积(physical vapor deposition，PVD)。气相沉积方法的实例包含热丝CVD、射频CVD(radio-frequency CVD，rf-CVD)、激光CVD(laser CVD，LCVD)、共形钻石涂布工艺、金属-有机CVD(metal-organic CVD，MOCVD)、溅镀、热蒸发PVD、离子化金属PVD(ionized metal PVD，IMPVD)、电子束PVD(electron beam PVD，EBPVD)、反应性PVD、原子层沉积(atomic layer deposition，ALD)、等离子增强CVD(plasma-enhancedCVD，PECVD)、高密度等离子CVD(high-density plasma CVD，HDPCVD)、低压CVD(low-pressure CVD，LPCVD)，及类似物。在一些实施例中，电介质162包含氧化硅或氮化硅。在一些实施例中，电介质162的最上水平也用以作为钝化层。
参考图2B，第一互连件结构114是形成在第一半导体衬底112上方。第一互连件结构114可由从底层往顶层堆叠的金属层所形成。例如，金属层147是通过沉积屏蔽层(未分开显示)在第一半导体衬底112上所形成。屏蔽层是透过蚀刻操作图案化，以形成用于金属层141的所要图案。接着，将导电材料填充在经蚀刻图案中。在图案被导电材料填充之后，通过移除操作剥除屏蔽层。可将IMD材料113填充在金属层141的导电材料间。类似地，导电通路层142是形成在金属层141上方，以在金属层141与上覆金属层142之间产生导电连接。金属层143、145以及147是依序伴随着中介导电通路层144以及146形成。金属层147的一部分是从第一互连件结构114暴露出。
参考图2C，数个接垫154是在第一互连件结构114的最顶水平形成。在一些实施例中，接垫154中的各者具有顶部表面154A，高于IMD 113的顶部表面113A。在一些实施例中(未显示)，顶部表面113A可经配置以与顶部表面154A齐平，而使得第一互连件结构114具有图1A的经平坦化顶部表面114A。第一半导体衬底112以及第一互连件结构114构成第一半导体装置110。
图2D到图2F为根据本揭露的一些实施例显示在各种阶段成形加工的第二半导体装置120的横截面图。第二半导体衬底122是如图2D所显示般提供。在一些实施例中，至少一个有源或无源结构(未显示)可形成在第二半导体衬底122中。第二半导体衬底122具有第一掺杂物型，例如p型。
参考图2E，第二互连件结构124是形成在第二半导体衬底122上方。第二互连件结构124可由堆叠的金属层所形成。在一些实施例中，第二互连件结构124是从底部往顶部形成，其中此种工艺是相似于第一互连件结构114的形成。例如，金属层131、133、135以及137是在彼此上方伴随着对应中介导电通路层132、134以及136形成。IMD 123被填充在前述金属层间以完成第二互连件结构124。金属层131的一部分是从第一互连件结构114暴露出。
参考图2F，数个接垫152是在第二互连件结构124的最顶水平形成。在一些实施例中，接垫152中的各者具有顶部表面152A，高于IMD 123的顶部表面123A。在一些实施例中(未显示)，顶部表面123A可经配置以与顶部表面152A齐平，而使得第二互连件结构124具有图1A的经平坦化顶部表面124A。第二半导体衬底122以及第二互连件结构124是构成第二半导体装置120。
如图2G所显示，第一半导体装置110被倒置并与半导体装置120接合。接垫154是与对应接垫152电接合。
参考图2H，第一半导体衬底112被往下薄化。被薄化的半导体衬底112是被薄化到从底部表面112C到顶部表面112A测量的厚度L。在一些实施例中，厚度L是从约20微米(um)到约500um。在一些实施例中，厚度L是从约20um到约300um。在一些实施例中，厚度L是从约40um到约120um。
在图2I中，电介质164是形成在第一半导体装置110上方。在一些实施例中，电介质164可用以作为钝化层。在一些实施例中，电介质164包含氧化硅或氮化硅。电介质164可通过沉积操作形成，例如热丝CVD、rf-CVD、激光CVD(LCVD)、共形钻石涂布工艺、MOCVD、热蒸发PVD、HDPCVD、LPCVD，及类似物。
在图2J中，第一通路160是形成在第一半导体衬底112中。第一通路160可通过屏蔽层的沉积形成。屏蔽层可以是光阻屏蔽或硬屏蔽，例如氮化物。接着，以所述屏蔽层就地实施蚀刻操作。第一通路160是通过合适的蚀刻工艺例如干式蚀刻操作形成。在一些实施例中，本操作中的干式蚀刻包含采用含氟气体的反应性离子蚀刻(reactive ion etch，RIE)。在完成第一通路160之后，移除屏蔽层。
在图2K中，电介质材料167是共形地形成在第一半导体衬底112上方。在一些实施例中，电介质材料167是与电介质164所具者不同的材料。在一些实施例中，电介质167是形成在电介质164以及第一通路160的侧壁与底部表面上方。电介质167可通过合适的沉积工艺形成，例如CVD或PVD操作。
在图2L中，电介质材料182是整片沉积在电介质167上方。电介质材料182是填充第一通路160。在一些实施例中，电介质材料182是与电介质167所具者不同。在一些实施例中，电介质材料182是与电介质164所具者不同。
在图2M中，实施移除操作以移除在电介质层164上面的过多材料。在移除操作之后，电介质167的部分被留在第一通路160的侧壁与底部表面上。结果，电介质166是形成在第一通路160中。还通过所述移除操作暴露出电介质164。在一些实施例中，所述移除操作可通过合适的工艺实施，例如化学机械抛光(CMP)操作。在一些实施例中，经填充的第一通路160的顶部表面的部分(其包含表面166A及167A)可包含由于碟化效果所致的弯曲表面。在一些实施例中，第一通路160的顶部表面可包含内凹形状，例如朝上的内凹形状。因此，电介质166可包含顶部表面166A，具有弯曲形状。例如，顶部表面166A可包含朝上的内凹形状。在一些实施例中，电介质167可包含顶部表面167A，具有弯曲形状。例如，顶部表面167A可包含朝上的内凹形状。
在图2N中，第二通路160'是形成在电介质166中。第二通路160'是向下延伸并暴露出金属层141。第二通路160'可通过屏蔽层的沉积形成。接着，以所述屏蔽层就地实施蚀刻操作。第二通路160'是通过合适的蚀刻工艺例如干式蚀刻操作形成。在一些实施例中，本操作中的干式蚀刻包含采用含氟气体的反应性离子蚀刻RIE。在完成第二通路160'之后，移除屏蔽层。
参考图2O，第一层169是形成在第二通路160'中。第一层169可通过各种技术形成，如电镀、无电式电镀、高密度离子化金属等离子(ionized metal plasma，IMP)沉积、高密度电感耦合等离子(inductively coupled plasma，ICP)沉积、溅镀、PVD、CVD、LPCVD、等离子增强化学气相沈积(PECVD)，及类似物。
参考图2P，第二层170是形成在第二通路160'上方。此外，第二层170是形成在第一层169上。第二层170可通过各种技术形成，如电镀、无电式电镀、高密度离子化金属等离子(IMP)沉积、高密度电感耦合等离子(ICP)沉积、溅镀、PVD、CVD、LPCVD、等离子增强化学气相沈积(PECVD)，及类似物。
参考图2Q，UBM 174是形成在第一通路160上方。在一些实施例中，UBM 174覆盖电介质164的部分。接着，连接件172是形成在UBM 174上方。
鉴于前述，本揭露实施例提供一种半导体结构，其中提出改善的接垫，以增进对抗外来应力的结构抗性。所述接垫可包括至少两层导电材料。所述接垫经放置在通路中。在所述接垫的两层中，第一层包括导电材料，例如镍。此外，第二层包括导电材料，例如金。此外，第二层包括帽盖部分，覆盖所述通路。因此，所述接垫展现较大应力抗性。据此减轻结构裂开或剥离的风险。
本揭露实施例提供一种半导体结构。所述半导体结构包括半导体衬底；以及互连件结构，在所述半导体衬底上方。所述半导体结构也包括接垫，在所述半导体衬底中且耦合到所述金属层。所述接垫包括两个导电层。
本揭露实施例提供一种半导体结构，其包括第一半导体装置以及第二半导体装置。所述第一半导体装置包括第一半导体衬底；第一互连件结构，在所述第一半导体衬底上方；端子，在所述第一半导体衬底中，其中所述端子是用以将所述第一互连件结构与在所述第一半导体衬底上方的连接件电耦合；以及电介质，环绕所述端子。所述第二半导体装置包括第二半导体衬底。所述第二半导体装置也包括第二互连件结构，在所述第二半导体衬底上方且用以与所述第一互连件结构接合。所述端子包括第一层，连接到所述第二互连件结构；以及第二层，在所述电介质上延伸。
本揭露实施例提供一种制造半导体结构的方法。所述方法包括：提供第一半导体衬底；形成第一互连件结构在所述第一半导体衬底上方；提供第二半导体衬底；形成第二互连件结构在所述第一半导体衬底上方；接合所述第一互连件结构与所述第二互连件结构；形成第一通路在所述第一半导体衬底中，所述通路暴露在所述第一互连件结构中的金属层的顶部表面的部分；沉积电介质在所述第一通路中；形成第二通路在所述电介质中；沉积第一导电层在所述第二通路中；以及沉积第二导电层在所述第一导电层上方。
前面列述了数个实施例的特征以便本技术领域具有通常知识者可更佳地理解本揭露实施例的方面。本技术领域具有通常知识者应了解他们可轻易地使用本揭露实施例作为用以设计或修改其他工艺及结构的基础以实现本文中所介绍实施例的相同目的及/或达成本文中所介绍实施例的相同优点。本技术领域具有通常知识者也应体认到此些均等构造不会悖离本揭露实施例的精神及范围，以及他们可在不悖离本揭露实施例的精神及范围下做出各种改变、取代、或替代。
符号说明
100 半导体结构
110 第一半导体装置
112 第一半导体衬底
112A、166A 顶部表面/表面
112B、122A 表面
112C 底部表面
113 金属间电介质(IMD)/IMD材料
113A、123A、152A、 顶部表面
154A、167A
114 第一互连件结构
114A、124A 表面
120 第二半导体装置
122 第二半导体衬底
123 金属间电介质(IMD)
124 第二互连件结构
131、133、135、137、 金属层
141、143、145、147
132、134、136、144、146 金属通路/中介导电通路层
142 金属通路/导电通路层/上覆金属层
152、154 接垫
160 第一通路
160' 第二通路
162、164 电介质层/电介质
165、166 电介质
167 电介质材料/电介质
168 端子/接垫
168A 顶部表面/上表面
168B 底部表面/单一接点
168C 侧壁
169 第一层
169A 表面/上表面
170 第二层
172 连接件
174 凸块下金属(UBM)
182 电介质材料
H、H1、H2 高度
W1 顶部宽度
W2 底部宽度
T、L 厚度

Claims (20)

1.一种半导体结构，其包括：
半导体衬底，其包含第一表面以及相对于所述第一表面的第二表面；
第一电介质层，其位于所述半导体衬底的所述第二表面上方；
互连件结构，其从所述半导体衬底的所述第一表面延伸；
第二电介质层，其在所述半导体衬底内部并从所述半导体衬底的所述第一表面延伸到所述第二表面，其中所述第二电介质层包含与所述半导体衬底的所述第二表面相邻的第一顶部表面，其中所述第一顶部表面为一内凹表面；以及
接垫，其耦合到所述互连件结构，所述接垫包括通路，所述通路延伸穿过所述半导体衬底到所述互连件结构并具有由所述第二电介质层限定的侧壁，其中第一导电层填充所述通路的底部部分到所述第一导电层的第二顶部表面，所述第二顶部表面在所述通路内，且第二导电层设置在所述第一导电层的所述第二顶部表面上并延伸至所述第二导电层的第三顶部表面，其中所述第二导电层在所述第二电介质层上方延伸，所述第二电介质层的所述第一顶部表面连接所述第二导电层的边缘，所述第三顶部表面具有弯曲形状，其中所述第三顶部表面的顶部与所述第一电介质层齐平；
凸块下金属层，其直接位于所述第二导电层的所述第三顶部表面上且在所述边缘上方延伸而直接连接所述第二电介质层的所述第一顶部表面；以及
凸块，其位于所述凸块下金属层上方。
2.根据权利要求1所述的半导体结构，其中所述第一导电层的材料具有杨氏模数是从180千兆帕斯卡到220千兆帕斯卡。
3.根据权利要求2所述的半导体结构，其中所述第二导电层具有从50千兆帕斯卡到120千兆帕斯卡的杨氏模数。
4.根据权利要求1所述的半导体结构，其中所述第二导电层是金层且所述第一导电层是镍层，所述金层经配置以连接到所述凸块。
5.根据权利要求4所述的半导体结构，其中所述镍层包括高度是从20,000埃到25,000埃。
6.根据权利要求1所述的半导体结构，其中在所述第一导电层及所述第二导电层之间的杨氏模数比值是从1.5到3.5。
7.根据权利要求1所述的半导体结构，其中所述边缘连接所述第三顶部表面的所述顶部与所述第二电介质层的所述第一顶部表面。
8.根据权利要求1所述的半导体结构，其中所述通路的所述底部部分接触所述互连件结构的表面。
9.根据权利要求1所述的半导体结构，其中所述接垫包括渐缩形状。
10.根据权利要求1所述的半导体结构，其中所述凸块下金属层在所述第一电介质层上方延伸且连接所述第一电介质层。
11.根据权利要求1所述的半导体结构，其中所述半导体衬底进一步包括第三电介质层侧向环绕所述第二电介质层。
12.根据权利要求11所述的半导体结构，其中所述凸块下金属层连接所述第三电介质层。
13.一种半导体结构，其包括：
第一半导体衬底；
第一互连件结构，其在所述第一半导体衬底的第一表面上方，所述第一半导体衬底具有相对于所述第一表面的第二表面；
第一电介质层，其穿过所述第一半导体衬底并具有第三表面，所述第三表面相邻于所述第一半导体衬底的所述第二表面；
第一通路，其从所述第二表面延伸穿过所述半导体衬底到所述第一互连件结构的表面，所述第一通路包含由所述第一电介质层限定的第一侧壁以及由所述第一电介质层限定的第二侧壁，其中所述第一侧壁相对于所述第二侧壁，所述第一通路具有以第一导电材料填满的底部部分，所述第一导电材料从所述第一通路的所述第一侧壁延伸至所述第一通路的所述第二侧壁；
第二导电材料，在所述第一导电材料上方，所述第二导电材料填满所述第一通路的上方部份，其中所述第二导电材料置于所述第一通路的第一边及第二边上方并在所述第一通路上方延伸，所述第二导电材料在所述第一边上具有第一边缘且在所述第二边上具有第二边缘，其中所述第二导电材料包含与一第二电介质层齐平的弯曲顶部表面，所述第二电介质层直接位于所述第一半导体衬底的所述第二表面上；
凸块下金属层，其在所述第二导电材料上方并直接置于所述第一边缘以及所述第二边缘上并且连接所述第一电介质层的所述第三表面；以及
连接件，其在所述凸块下金属层上方。
14.根据权利要求13所述的半导体结构，其中所述底部部分包括渐缩形状。
15.根据权利要求13所述的半导体结构，其进一步包括第二电介质层，所述第二电介质层环绕所述第一电介质层。
16.根据权利要求15所述的半导体结构，其中所述第二电介质层具有顶部表面，所述顶部表面具有弯曲形状。
17.根据权利要求13所述的半导体结构，其中所述连接件为焊线或焊料凸块。
18.一种制造半导体结构的方法，其包括：
提供第一半导体衬底；
在所述第一半导体衬底上方形成第一互连件结构；
在所述第一半导体衬底中形成第一通路，所述第一通路暴露在所述第一互连件结构中的金属层的顶部表面的部分；
沉积电介质填充所述第一通路；
蚀刻填充所述第一通路的所述电介质以形成第二通路，所述第二通路具有第一电介质侧壁及与所述第一电介质侧壁相对的第二电介质侧壁；
在所述第二通路中沉积第一导电层，其中所述第一导电层从所述第一电介质侧壁延伸至所述第二电介质侧壁而填充所述第二通路，且所述第一导电层延伸至第一高度；以及
在所述第一导电层上方沉积第二导电层，其中所述第二导电层从所述第一电介质侧壁延伸至所述第二电介质侧壁，
在所述第一导电层与所述第二导电层之间的杨氏模数比值是1.5到3.5。
19.根据权利要求18所述的方法，其中所述第二导电层的部分覆盖所述电介质的顶部表面的部分。
20.根据权利要求18所述的方法，其中所述沉积所述电介质填充所述第一通路包括将填充所述第一通路的所述电介质的顶部表面形成为内凹形状。
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