CN101740484B - 形成穿透硅通孔的方法 - Google Patents

形成穿透硅通孔的方法 Download PDF

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Publication number
CN101740484B
CN101740484B CN200910126308XA CN200910126308A CN101740484B CN 101740484 B CN101740484 B CN 101740484B CN 200910126308X A CN200910126308X A CN 200910126308XA CN 200910126308 A CN200910126308 A CN 200910126308A CN 101740484 B CN101740484 B CN 101740484B
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dielectric layer
substrate
stacked structure
recess
dielectric
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CN101740484A (zh
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林全益
李松柏
黄庆坤
林生元
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种形成具有穿透硅通孔(TSV)的半导体器件的方法。包括以下步骤：提供在其上形成有第一电介质层的半导体器件。在该第一电介质层上形成一个或多个电介质层，由此，每一个电介质层具有一个堆叠结构，其中一个或多个电介质层中的堆叠结构的垂直对齐。堆叠结构可能是，例如，金属环。该堆叠结构然后被去除从而形成第一凹口。由第一凹口延伸到到衬底中形成第二凹口。在第二凹口中填充导电物质从而形成TSV。

Description

形成穿透硅通孔的方法
技术领域
本发明通常涉及集成电路的制造，并且具体地，涉及一种在半导体管芯和最终的管芯堆叠结构中形成穿透硅通孔的方法。
背景技术
自从发明了集成电路(IC)，由于各种电子元件(例如，晶体管、二极管、电阻器、电容器等)的集成度的不断提高，半导体工业经历了持续的快速增长。就绝大部分而言，这种对集成度的改善来自于一再削减最小特征尺寸，使得更多的元件集成到一个给定的区域。
这些集成化的改善在实质上基本是二维(2D)的，其中那些被集成的组部件所占用的空间基本在半导体晶圆(wafer)的表面。虽然光刻技术的显著改善已经在2D集成电路的制造上引起了相当大的改进，但是在二维上存在可以达到密度的物理极限。这些极限的其中一个就是制造这些组部件所需要的最小尺寸。此外，当更多的器件被放入在一块芯片上，更复杂的设计是必需的。
为了进一步增加电路密度，三维(3D)集成电路已进行了研究。在一个典型3D IC的制造过程中，两个管芯被键合在一起并且在每个管芯和在基板上的接触焊盘之间形成电连接。例如，一种尝试包括把两个管芯焊接在彼此的顶部。堆叠的管芯然后键合到承载基板，并且引线键合把每个管芯上的接触焊盘电连接到承载基板上的接触焊盘。然而，为了引线键合，这种尝试需要一个比管芯大的承载基板。
最近更多尝试是把重点放在穿透硅通孔(TSV)。一般来说，TSV是通过蚀刻一个纵向通孔穿透衬底并且在该通孔中填充导电材料如铜形成的。该TSV可用于提供半导体衬底背面到该衬底的相对面的半导体电路的电连接，或者提供到堆叠的管芯的半导体电路的电连接。在这种方式下，管芯可以在被堆叠的同时保持一个较小的封装尺寸。
一般来说，用于形成TSV的工序中包含了蚀刻至少部分地穿透了硅衬底和其上可能覆盖的电介质层的沟槽，然后在沟槽中沉积铜。然而，这种方法要求硬掩膜和蚀刻模块的能力。此外，由于晶圆的形貌，铜残留物可能保留在晶圆的表面。
发明内容
因此，本发明的目的是提供形成TSV的更有效的方法和系统。
通过本发明提供的具有穿透硅通孔(TSV)半导体器件的实施例通常可以获得技术的优点，通常可以解决或规避上述的这些问题及其他问题。
在一个实施例中，本发明提供了一种形成具有TSV的半导体器件的方法。提供一个其上具有半导体器件的半导体衬底。形成第一电介质层，并且第一互连部件(interconnect feature)被形成在第一电介质层中。第二电介质层形成在第一电介质层上，第二互连部件是形成在第二电介质层中。在第二电介质层中还形成一堆叠结构。此后，堆叠结构被去除，从而在第二电介质层形成第一凹口。第二凹口是由第一凹口扩展进入了至少一部分半导体衬底中而形成的。第二凹口填充了导电材料。
在另一实施例中，本发明提供了另一种形成具有TSV的半导体器件的方法。提供了一衬底以及第一电介质层形成在该衬底上。一个或多个第二电介质层形成在第一电介质层上，其中的该一个或多个第二电介质层具有延伸穿透该一个或多个第二电介质层的牺牲堆叠结构。该牺牲堆叠结构将被去除，形成第一开口，并且穿透该一个或多个第二电介质层暴露出第一介电层。暴露在第一开口的第一电介质层被去掉，从而暴露了部分衬底。暴露的部分衬底被去除从而在衬底中形成凹口。该凹口填充了导电材料。
在又一实施例中，本发明提供一种形成具有TSV的半导体器件的方法。提供衬底并且在其上形成多个电介质层。堆叠结构形成在该多个电介质层的一个或多个中。该堆叠结构被去除，形成了延伸通过该多个电介质层的一个或多个的凹口。该凹口延伸到衬底中并被填充了导电材料。
附图说明
为了更加完整地理解本发明及其优点，结合与之相应的附图，现对以下说明做出了介绍，其中：
图1-10是根据一个说明性实施例的具有在衬底和电介质层中形成的穿透硅通孔的晶圆的剖视图；
图11示出了根据一个说明性实施例的在具有穿透硅通孔的晶圆上形成的键合接触；和
图12是根据一个说明性实施例示出的堆叠晶圆配置的剖视图。
具体实施方式
本发明实施例的制作和使用详细地讨论如下。应该理解，虽然，本发明提供了许多适用的发明概念，但可以在各种各样的具体情况中实施。所讨论的具体实施例只是本发明的制作和使用的具体方式的说明，并没有限制本发明的范围。
现参照图1，表现出了晶圆10的剖视图。晶圆10包括半导体衬底100，其典型地是硅(Si)，但也可能是砷化镓(GaAs)，磷砷化镓(GaAsP)，磷化铟(InP)，镓铝砷(GaAlAs)，铟镓磷化物(InGaP)等制成的，并且示出了器件101形成在衬底100中。虽然只有三个器件101表示出来，但可能有许多的有源和无源的半导体器件101中形成在衬底100中。
绝缘层(有时也被称为层间电介质层ILD)102被沉积在晶圆10的衬底100上。在一实施例中，形成ILD层102所用的材料包括二氧化硅(SiO2)和磷硅酸盐玻璃(PSG)。在另一实施例中，ILD层102包括一低介电常数(低-k)材料，如碳掺杂氧化硅或氟掺杂硅酸盐玻璃(FSG)层，但其他低-k介质材料也可用于ILD层102。光刻工序可用于图案化ILD层102，限定通向先前在半导体衬底100中形成的器件101的电连接(接触)105。蚀刻工序，如各向异性干蚀刻工序，可在光刻完成后进行，在ILD层102中形成接触开口。随后，通向器件101的电接触105的形成是通过在接触开口填充导电材料和金属化工序，如金属化学气相沉积(CVD)工序。用于形成接触105的导电材料包括铝(Al)、铜(Cu)、钨(W)、钴(Co)、其他金属或金属合金，但其他合适的导电材料或工序也可以用来形成接触105。平坦化工序，如化学机械抛光(CMP)，在衬底表面上执行，以消除过剩的接触材料，提供了适合于后续的处理步骤的基本上平坦的衬底表面。在一实施例中，一阻隔层，如氮化钛(氮化钛)层(未显示)，在形成接触105之前通过适当的工序形成在接触开口的底部。阻隔层可以防止任何在金属化工序中沉积的金属浸到衬底100中。
正如图2a-2c所示，第一互连金属层(有时也称为M1层)110形成在来自前面处理步骤的平坦化的衬底之上。第一金属互连层110可包括各种导电材料，如铜，钨，铝，金，银等，通过如CVD的工序形成。按照本发明实施例，第一金属互联层110随后用所述技术领域已知的光刻工序图案化。在一实施例中，该光刻工序包括沉积光致抗蚀剂材料(图2a和2b指示为PR的)和按照预先确定的图案辐照该光致抗蚀剂材料。此后，光致抗蚀剂材料可以被显影从而暴露下层的M1层中要在随后的蚀刻步骤中去除的部分，而其余的光致抗蚀剂材料在蚀刻过程中保护M1层的所需的部分。在一实施例中，在目前的光刻工序中的在光致抗蚀剂材料中记载的图案包括用来限定M1部件(features)的光致抗蚀剂图案111，该M1部件通常被用来提供形成在衬底100中的各种半导体器件101的电连接或在衬底100的器件101之间的电连接以及在其上的互连层中的导电部件。注意到，在目前的光刻工艺中在光致抗蚀剂材料中记载的图案还包括用于限定在随后的处理步骤中被用于在衬底100上形成穿透硅通孔的部分衬底表面的光致抗蚀剂图案112。通过光致抗蚀剂图案112形成衬底区域中的穿透硅通孔的加工步骤将详细讨论如下。
蚀刻工序，如各向异性等离子体刻蚀工序，接着在晶圆10上进行，去除了第一层金属互连层110的暴露部分。其结果是，留在第一互连金属层的M1部件包括光致抗蚀剂图案111界定的金属迹线M111，以及光致抗蚀剂图案112界定的金属板M112，如图2c所示。应该指出的是图2a-2c所示的实施例显示的方块光致抗蚀剂图案112仅供说明之用。其他实施例中可以使用任何合适的形状光致抗蚀剂图案112，包括矩形，圆形，椭圆形，三角形，多边形的形状，和/或类似形状。此外，M1金属板12可形成衬底表面，而穿透通孔将会在其下层的衬底区域根据预先的穿透通孔安排形成，不局限于任何特定的衬底表面区域。
图3a和3b示出了按照本发明实施例在衬底100上形成第一金属间电介质(IMD)层202。在一实施例中，低k材料，如碳掺杂氧化硅或FSG层，被用来组成第一IMD层202，但其他合适的介质材料，如氧化硅(SiO2)和磷硅酸盐玻璃(PSG)也可以使用。执行光刻和蚀刻工序流程从而在第一IMD层202中形成通孔开口。随后，可以执行一金属沉积工序，如CVD工序，从而在通孔开口中填充导电材料，如铝，铜，钨，钴，或其他合适的导电材料，从而在第一IMD层的202形成通孔，构成通向第一互连层中金属迹线M1 11和金属板M1 12的电连接。同样，在衬底上执行CMP工序从而为后续的处理步骤提供所需的平坦的衬底表面。形成在第一IMD层202中的通孔包括耦合到金属迹线M1 11的通孔205和耦合到金属板M1 12的通孔环205R(图3b)，重叠并基本上对准的金属板M1 12边缘。
应当指出的是，通孔205连接到下层金属迹线M1 11，在图3a和3b中为了仅供说明之用只显示了一个单独的通孔。其他实施例中可使用其他通孔配置，如用于电连接到金属迹线M1 11的一个通孔205阵列，目的是为了，例如，增加导电性。此外，通孔环205R在图3a和3b中为了仅供说明之用只显示了一个方形的通孔环。其他实施例中可能有不同的通孔环形状，最好是匹配下层金属板M1 12的外围，如矩形，圆形，椭圆形，三角形，多边形的形状，和/或类似的形状。通孔环205R并不局限于任何特定的形状，但最好，是基本对准下层金属板M112边缘的一个封闭的环。在一个实施例中，通孔环205R的宽度与通孔205相同。
图4表述了一个实施例中在上层的第二互连金属层中(有时也被称为M2层)形成导电部件。可以采用本领域中已知的例如用在第一层的互连层中形成金属迹线M1 11和金属板M112的材料和工序。金属迹线M211可被形成为覆盖在通孔205上并且电耦合到通孔205。金属部件M212在通孔环205R上形成堆叠。在一个实施例中，金属部件M212是环状的，金属部件M212的外边缘基本上对准一下层通孔环205R的外边缘。在其他实施例中，金属部件M212是其边缘基本对准一下层通孔环205R的外边缘的平板。
图5显示另一实施例中，在执行本领域中众所周知的双镶嵌工序流程来同步地形成M211，M212，通孔205，和在第一IMD层202的通孔环205R。当使用双镶嵌工序时候，第一IMD层202最好是低-k材料，如碳掺杂氧化硅层或FSG层，但其他合适的介质材料也可使用。此外，优选用铜来形成M211，M212，通孔205，和通孔环205R，虽然其他合适的导电材料也可使用。
在图6中，它表述了可以重复类似的处理步骤来形成在第二IMD层302中的通孔305、通孔环305R、金属迹线M311、金属部件M312，以及在第三IMD层402中形成通孔405、通孔环405R、金属迹线M411和金属部件M412。金属部件M412，M312，M212和M112彼此重叠，并分别耦合到通孔环405R，305R，205R。在一实施例中，金属部件M412，M312，M212和M112的外边缘和通孔环405R，305R，205R基本对齐。虽然图6只显示有四个互连金属层，可以理解的是，类似金属部件也可形成在更上层的互连金属层中以及直到最上层的互连金属层中。因此，在图6中M411和M412也指示为在上层互连金属层中形成的类似的金属迹线和金属部件。至此，堆叠结构50已形成在晶圆10的互连层中，在其下方穿透硅通孔将形成在衬底100中，如前所述。
在图7中，掩膜层形成在晶圆10上。使用本领域已知的光刻和蚀刻工艺图案化和蚀刻掩膜层，从而形成图案化的掩膜层430，形成暴露出晶圆表面堆叠结构50的区域的开口。在一实施例中，这些暴露的晶圆表面区域也通常被称为TSV区域，因为在随后的处理步骤中TSV要形成在衬底100中的这些区域的下面。在单个或多个层的配置中，虽然其他合适的有机或无机材料的硬掩膜材料也可以使用，该图案化的掩膜层430最好是包含电介质材料的硬掩膜层，如氮化硅(SiNx)或二氧化硅(SiO2)。另一种情况，图案化的光致抗蚀剂也可用于制造图案化的掩膜层430。在一个实施例中，氮化硅用于图案化的掩膜层430，它最好是有约50微米至500微米的厚度。
正如图8a及8b，根据本发明中的实施例，堆叠结构50，例如，牺牲性的堆积结构，随后被剥离并被从晶圆10去除。通过第一湿法化学蚀刻工序去除晶圆10上的堆叠结构50。在此实施例中，硫酸和过氧化氢溶液约30℃至60℃可能被用来蚀刻来自堆叠结构50的铜，因为相对于IMD层和ILD层，硫酸具有对铜的较高的蚀刻选择率。堆叠结构50上的第一湿法化学蚀刻工序从最顶层金属部件M412开始，并且沿着通孔环进入晶圆10和底部金属板M112中(由箭头在图8a中指示)，直至用来形成堆积结构50的铜被基本去除。漂洗工序接着剥离了从堆叠结构50的铜蚀刻中留下的IMD材料，在IMD层中生成一个凹口445，如图8b所示。
在图9中，晶圆10被进行第二蚀刻工序，从而去除在凹口445底部的ILD层102。在一实施例中，ILD层102包括低-k介质材料，并可被本领域公知的各向异性蚀刻工艺去除，其相对于半导体衬底100对低-k介质材料具有较高的蚀刻选择率。此后，晶圆10在前面工序产生的凹口中被执行了第三蚀刻工序，从而去除衬底100材料，如硅，并且该凹口延伸到衬底100中。在一实施例中，时间控制的各向异性等离子体刻蚀工序引入到晶圆10上，从而在衬底100中生成了具有约2-75微米深度的深TSV凹口450。在另一实施例中，是各向异性等离子体刻蚀工艺在衬底100中创建了蚀刻的图案，其达到了大于衬底100一半厚度的深度，如图9所示。
在图10中显示了，图案化的掩膜层430被用已知的工艺去除并且隔离层446被沉积在晶圆10上，包括TSV凹口450上。在TSV凹口450中的446层可阻止任何导电材料浸入到晶圆10的电路的任何有源部分中。在一实施例中，PSG、非掺杂的硅酸盐玻璃(USG)或通过等离子体增强化学气相沉积(PECVD法)沉积的氮化硅来形成隔离层446，但其他合适的材料和工序也可使用。
金属化工序，如铜电镀，可紧接着在晶圆上10执行，在TSV凹口中填充铜(Cu)从而形成晶圆10中的TSV 470。其他合适的导电材料，如铝(Al)，铜(Cu)、钨(W)、钴(Co)、金(Au)、银(Ag)，以及其他合适的沉积工艺，如金属化学气相沉积工艺，也可用来形成TSV 470。同样，后续可以在衬底上进行CMP工序从而为以后的处理步骤提供所需要的平坦的衬底表面。另一方面，在形成TSV 470的金属化工序之前，阻隔层，如氮化钛(TiN)层和/或金属种子层(未显示)，可通过适当的工序保形地形成在TSV凹口450上，如CVD或物理气相沉积(PVD)。
在一个实施例中，经上文所述工艺步骤处理过的晶圆10通过一个用于形成堆叠管芯配置的典型的后端(BEOL)工序流程从而可被键合到其他半导体集成电路管芯或晶圆上。
图11中，键合接触490是通过沉积电介质层475形成的，其把晶圆10中的器件和互联迹线与键合到晶圆10的其他晶圆中的其他任何电路或器件隔离开。蚀刻凹口进入到电介质层475中，其被沉积导电材料从而形成键合接触490。键合接触490电耦合到晶圆10中的金属迹线M411和TSV 470。该绝缘材料构成的电介质层475最好被去除或蚀刻，从而露出略微突出到电介质层475上方的键合接触490。此外，衬底100通过已知的技术被从背面130减薄，如背面研磨，蚀刻，CMP，或类似的技术，并且衬底100的一部分被去除从而露出TSV 470构成的接触点。在衬底100背面130的TSV 470的突出部分便于把晶圆10键合到另一集成电路晶圆或管芯。
另外，类似键合接触490的键合接触键也能以如上所述同样的方式形成在晶圆10的背面130(被减薄侧)。如此所形成的键合接触(未显示)从晶圆10背面130被电耦合到TSV 470，以及可被用于把晶圆10键合到另一集成电路晶圆或管芯。
图12阐述了在当前发明中的一个实施例，其中晶圆10键合到晶圆11从而形成堆叠管芯结构15。晶圆11包括衬底600、电介质层604、绝缘层606和键合接触610。衬底600可包括一个或多个预先形成的半导体器件，电介质层604可用于隔离形成在不同互连层中的互连迹线，并且绝缘层606可用来嵌入键合接触610和限制晶圆中的各种器件之间的干扰。晶圆10和11在键合焊盘610和突出的接触点TSV 470处被对准并且被键合在一起。在一实施例中，键合媒介物，如铜，钨，铜，锡合金，金，锡合金的铟金合金，铅锡合金，或类似的，被施加在将要键合的晶圆10和11的键合接触之间。
应当指出的是，虽然描述了晶圆10和11形成堆叠晶圆配置，用于此处的具体的晶圆并不打算以任何方式限定本发明的实施例。在实践中，结构10和11可以是晶圆或管芯，因此堆叠结构可能有管芯对管芯的键合配置、管芯对晶圆的键合配置或晶圆对晶圆的键合配置。
还应该指出，任何数量的不同的器件，组部件，连接器等，可集成到晶圆10和11中。此处表述的具体的器件或器件的缺失不企图以任何方式限制本发明中实施例。
图12还表明，堆叠管芯结构15被附着在一个封装基板55上，从而形成倒装芯片球栅阵列(BGA)配置的IC封装20。在形成堆叠管芯结构15后，大量键合接触，如键合接触490被布置在键合表面75上，一般布置成阵列的形式。键合表面75通过焊料凸块(例如，焊球)58附着在封装衬底55上，其反过来通过封装引线65构成通向到印刷电路板(未显示)的电连接。注意到，在实施例中其他IC封装形式也可被用来封装堆叠的管芯15。作为另一例子，在堆叠的管芯可以被直接焊接到印刷电路板上。此处表述的具体的器件或器件缺失不企图以任何方式限制本发明中的实施例。
应当指出的是，为便于说明和清楚起见，只有为数有限的有源器件，如器件101，和通孔，如通孔105，205和305，以及TSVs 470被显示出来。然而，本领域普通技术人员可以理解，在实践中，联合了集成电路和堆叠管芯的集成电路系统可能包括数百万甚至上千万或更多的有源和无源器件以及，进一步地，在最上部的电介质层中互连结构可包括数十个甚至数百个或更多的导线。同样，本领域普通技术人员可以理解，在实践中每个堆叠管芯将包括几十个(dozens)或更多的背面连接，如键合接触或引线。另外，例如，尽管只显示出一些键合接触490，在实施例中堆叠管芯结构可能包含数十个甚至数百个或更多的用于构成电连接到IC封装的接触。
还应该指出，可以给上文所描述和图示的例子的晶圆和管芯的每一个的提供可替代的接触、通孔、TSV以及键合接触的实现形式，其可用于本发明中的各种实施例。在本发明的更多的和/或可选择的实施例中，所表述的选项的任何组合都可以采用。所表述的实施例不企图限制本发明实施例的各种更多的和/或替代性的实现形式。
还应该进一步指出，所描述的实施例中所述的不同层包括各种不同的材料取决于所需要的功能或取决于由制造商确定的适用性。用于金属键合接触的金属可能是任何合适的金属或合金，如铜，钨，铝，铝铜等。此外，根据所需要的不同电介质或绝缘层的用途或功能，可使用任何此类电介质材料，如二氧化硅，氮化硅，USG，PSG，低K电介质材料等。本发明不限于只使用某一有限数量的化合物和材料。
还应该指出，在示例性的实施例中的不同层和凹口可以使用任意数量的各种已知的工艺来沉积或创建。例如，各层的氧化物、电介质或其他层的创建可以是通过PVD、CVD、PECVD、原子层沉积(ALD)或类似的工艺来完成的。此外，从晶圆去除材料可以是通过干法或湿法蚀刻、化学机械抛光或类似的工艺来完成的。本发明不局限于任何单个的这种方法。
虽然本发明及其优势已详细地描述，应该理解，可以做出不离开所附权利要求所限定的本发明精神和范围的各种改变、替换和改进。此外，本申请的范围并不打算被限于说明书中所描述的工序，机器，制造，以及物质、手段、方法和步骤的组合。从本发明所公开的，作为本领域普通技术人员可以很容易地理解，目前现有的或以后开发的那些执行与所描述的相应实施例的基本相同的功能或实现大致相同的结果的工序，机械，制造，以及物质、手段、方法或步骤的组合，根据本发明在这里都可以使用。因此，所附的权利要求企图包括在这些工序，机械，制造，以及物质、手段、方法或步骤的组合的范围内。

Claims (15)

1.一种形成半导体器件的方法，该方法包括：
提供一半导体衬底，其上形成有半导体器件；
在该半导体衬底上形成第一电介质层；
在第一电介质层中形成第一互连部件，该第一互连部件被电耦合到半导体器件；
在第一电介质层上形成第二电介质层；
在第二电介质层中形成第二互连部件；
在第二电介质层中形成一堆叠结构；
去除堆叠结构，从而在第二电介质层中形成第一凹口；
通过把第一凹口延伸到半导体衬底的至少一部分中从而形成第二凹口；和用导电材料填充第二凹口。
2.根据权利要求1的方法，其中第二电介质层包括多个电介质层，多个电介质层的每一个具有一堆叠结构，该多个电介质层的堆叠结构与该多个电介质层的一个相邻电介质层中的堆叠结构直接接触，其中堆叠结构包括金属环。
3.根据权利要求1的方法，进一步形成了包括在形成第二电介质层之前在第一电介质层上形成一金属区域，堆积结构、直接在金属区域上。
4.根据权利要求1的方法，其中在第二电介质层中形成第二互连部件包括形成多个电耦合到半导体器件的金属迹线。
5.根据权利要求1的方法，其中第二凹口的形成至少部分地是通过第一蚀刻工序去除在第一凹口的底部的第一电介质层，随后进行第二蚀刻工序蚀刻该半导体衬底来实现的。
6.根据权利要求1的方法，其中第二互连部件的形成是与堆叠结构的形成同步进行的。
7.根据权利要求1的方法，其中导电材料包括铜，钨，铝，钴，金，银，或其组合物。
8.一种形成半导体器件的方法，该方法包括：
提供一衬底；
在衬底上形成第一电介质层；
在第一电介质层上形成一个或多个第二电介质层，所述一个或多个第二介质层具有延伸穿透它的一个牺牲堆叠结构；
去除该牺牲堆叠结构，从而形成穿透所述一个或多个第二电介质层并暴露出第一绝缘层的一部分的第一开口；
沿着第一开口的底部去除第一电介质层，从而形成穿透第一电介质层并暴露出衬底的外露部分的第二开口；
沿第二开口的底部去除衬底的一部分，从而在衬底中形成凹口；和
在所述凹口中填充导电材料。
9.根据权利要求8的方法，其中牺牲堆叠结构包括在一个或多个第二电介质层的每个中的一个堆叠部件，每个堆叠部件包括第一材料，该第一材料具有与该一个或多个第二电介质层不同的蚀刻率，其中第一材料是一种金属。
10.根据权利要求8的方法，其中在一个或多个第二电介质层的每一个中的牺牲堆叠结构具有一个形状，该形状能完全把第二电介质层的一部分与第二电介质层的其余部分隔离开。
11.根据权利要求8的方法，进一步包括在第一电介质层上形成一个底层，该底层与最低的牺牲堆叠结构相接触，其中在形成该一个或多个第二电介质层之前，形成该底层。
12.一种形成半导体器件的方法，该方法包括：
提供一衬底；
在该衬底上形成多个电介质层；
在该多个电介质层的一个或多个中形成堆叠结构；
去除所述堆叠结构，形成了延伸穿透该多个电介质层的一个或多个的凹口；
将该凹口延伸到衬底中；和
在该凹口中填充导电材料。
13.根据权利要求12的方法，其中一个层间电介质(ILD)层被插入到该多个电介质层和衬底之间，其中延伸所述凹口的步骤包括穿透该ILD层的第一蚀刻和刻入衬底中的第二蚀刻。
14.根据权利要求12的方法，其中每个堆叠结构包括金属和电介质，其中每个堆叠结构具有比顶部窄的底部。
15.根据权利要求12的方法，其中每个堆叠结构包括在平面视图上围绕着另一种材料的一个金属形状。
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