CN102088014A - 3d集成电路结构、半导体器件及其形成方法 - Google Patents
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Abstract
本发明公开了一种半导体器件,包括:衬底;形成在所述衬底上的扩散停止层;形成在所述扩散停止层上的绝缘体上硅SOI层;形成在所述SOI层上的MOSFET晶体管;贯穿所述衬底、所述扩散停止层、所述SOI层以及所述MOSFET晶体管层形成的硅通孔TSV;以及连接所述MOSFET晶体管与所述硅通孔TSV的互连结构。本发明的半导体器件可以具有良好的性能。
Description
技术领域
本发明涉及半导体制造技术领域,尤其涉及一种3D集成电路结构及其形成方法。
背景技术
在传统的器件按比例缩减将在未来10-15年之内到达其自身物理极限,而在这段时间内,新型器件结构,比如碳纳米管(CNT)、自旋电子器件以及分子开关等,还不能发展到可被实际使用的水平。因此,在继续使用铜和低k介电材料进行集成的情况下,对器件和系统级组装方式的担心促使工业界的领导者们寻求更新的组装方法,以满足近期的需求。站在这类技术最前端的是3D(3维)集成电路(IC),这一技术可以缩短互连长度,从而提高电路速度,降低功耗,并增加系统存储带宽。
目前的3D IC集成被描述为一种系统级架构,由多个晶片(wafer)结合形成,其中每个晶片的内部含有多个平面器件层的叠层,并经由硅通孔(TSV,Through-Silicon-Via)在Z方向相互连接。伴随3D的应用,TSV尺寸将不断变小,硅层厚度也将不断地变薄,3D集成电路也将得到越来越广泛的应用。
但是,在形成3D集成电路结构的部分工艺过程中,例如在形成TSV孔的工艺中,会在TSV孔中填充金属材料,例如铜、铝、钨等。此外,在研磨晶片底部从而引出TSV孔中的金属材料与其他晶片结合的工艺中,由于研磨处理会造成TSV孔底部暴露出的金属材料或者其他杂质,例如铁、钠等金属离子扩散到晶片内部的金属氧化物半导体场效应晶体管(MOSFET)中。并且在后续的晶片间互相结合的工艺中,由于粘合高温更导致上述各种金属离子快速地扩散到MOSFET内部。这样,导致形成的MOSFET出现故障。
发明内容
本发明的目的旨在至少解决现有技术中的上述问题之一。
为此,本发明的实施例提出一种3D集成电路结构、半导体器件及其制造方法,以提高3D集成电路的性能。
根据本发明的一个方面,本发明实施例提出了一种3D集成电路结构,所述集成电路结构包括:第一晶片,所述第一晶片包括:衬底;形成在所述衬底上的扩散停止层;形成在所述扩散停止层上的绝缘体上硅SOI层;形成在所述SOI层上的金属氧化物半导体场效应晶体管MOSFET;贯穿所述衬底、所述扩散停止层、所述SOI层以及所述MOSFET晶体管层形成的硅通孔TSV;以及连接所述MOSFET晶体管与所述硅通孔TSV的第一互连结构;其中,研磨所述第一晶片的底部以暴露出填充有金属材料的所述TSV孔,并通过所述TSV孔连接所述第一晶片底部到外部电路或者第二晶片的第二互连结构上。
根据本发明的另一方面,本发明的实施例提出一种形成3D集成电路的方法,所述方法包括以下步骤:形成第一晶片,其中形成所述第一晶片包括:形成衬底;在所述衬底上形成扩散停止层;在所述扩散停止层上形成SOI层;在所述SOI层上形成MOSFET晶体管;形成贯穿所述衬底、所述扩散停止层、所述SOI层以及所述MOSFET晶体管层的TSV孔;以及形成连接所述MOSFET晶体管与所述硅通孔TSV的互连结构。本发明还包括研磨所述第一晶片的底部以暴露出填充有金属材料的所述TSV孔;以及通过所述TSV孔连接所述第一晶片底部到外部电路或者第二晶片的互连结构上。
根据本发明的再一方面,本发明的实施例提出一种半导体器件,所述半导体器件包括:衬底;形成在所述衬底上的扩散停止层;形成在所述扩散停止层上的SOI层;形成在所述SOI层上的MOSFE T晶体管;贯穿所述衬底、所述扩散停止层、所述SOI层以及所述MOSFET晶体管层形成的硅通孔TSV;以及连接所述MOSFET晶体管与所述硅通孔TSV的互连结构。
在本发明中,对于构建在SOI层上的MOSFET器件,通过在SOI层下方设置扩散停止层可以防止在研磨晶片或后续的晶片结合工艺中,填充到TSV孔中的金属材料或者晶片中存在的其他金属杂质的离子扩散到MOSFET晶体管中,从而能够提供具有良好性能的MOSFET器件及其相应构成的3D集成电路。
本发明附加的方面和优点将在下面的描述中部分给出,部分将从下面的描述中变得明显,或通过本发明的实践了解到。
附图说明
本发明的上述和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解,其中:
图1a到图1e为本发明实施例在制造3D集成电路的晶片器件过程中不同阶段的截面结构示意图;
图2和图3为利用图1实施例的晶片器件形成的第一实施例的3D集成电路的部分结构示意图;
图4为利用图1实施例的晶片器件形成的第二实施例的3D集成电路的部分结构示意图。
具体实施方式
下面详细描述本发明的实施例,所述实施例的示例在附图中示出,其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的,仅用于解释本发明,而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开,下文中对特定例子的部件和设置进行描述。当然,它们仅仅为示例,并且目的不在于限制本发明。此外,本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施例和/或设置之间的关系。此外,本发明提供了的各种特定的工艺和材料的例子,但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外,以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例,也可以包括另外的特征形成在第一和第二特征之间的实施例,这样第一和第二特征可能不是直接接触。
参考图1a到图1e,该图显示了在制造本发明实施例的3D集成电路晶片过程中不同阶段的截面结构。
如图1a所示,该晶片器件包括衬底2,在本发明的一个实施例中,该半导体衬底2可包括任何半导体衬底材料,具体可以是但不限于体硅层(bulk wafer)。该晶片器件还包括:形成在衬底2上的第一氧化层4,第一氧化层4可以是通过本领域公知的沉积工艺形成在衬底2上的较薄氧化层,厚度范围在5-10nm之间,设置第一氧化层4的作用是为了改善衬底2和后续形成的扩散停止层6的接触性能。当然,本发明不局限于该具体实施例中,例如在一个实施例中,该晶片器件可以不包括第一氧化层4。然后,在第一氧化层4上沉积用于防止金属离子扩散的扩散停止层6。
在一个实施例中,扩散停止层6为氮化物层,氮化物具有良好的致密性,因此可以更好地用于防止金属离子扩散。所述氮化物包括但不局限于Si3N4或者SiCN。对于用来防止金属离子扩散的氮化物若沉积的太薄,则其防止扩散的功能不够,若太厚则会产生过大的电容。在一个实施例中,沉积的氮化物厚度范围在5~100nm之间。
在扩散停止层6的上方可以进一步沉积第二氧化层8,第二氧化层8可以是较厚氧化层,其厚度范围在5-200nm之间,设置第二氧化层8的目的是为了减小电容。通过上述步骤,从而得到图1a所示的晶片结构。当然,本发明不局限于该具体实施例中,例如在一个实施例中,该晶片器件可以不包括第二氧化层8。
如图1b所示,在图1a形成的晶片结构上方形成绝缘体上硅(SOI)层10,SOI层10可以通过例如智能切割(Smart-Cut)方法与第二氧化层8结合在一起,从而将SOI层10设置在晶片结构的顶部。然后,在SOI层10上构建金属氧化物半导体场效应晶体管(MOSFET)14及其后道互连(BEOL)16,后道互连结构16可以利用金属布线工艺形成的铜互连。MOSFET晶体管14及其后道互连结构16形成于在SOI层10上方沉积的氧化层12中,这里构建MOSFET晶体管14及其后道互连结构16可以利用本领域公知的任何适于使用的方法。
图1c显示了在图1b所示半导体结构中进一步形成硅通孔(TSV)的剖面结构图,TSV孔的形成步骤包括:首先贯穿衬底2、第一氧化层4、扩散停止层6、第二氧化层8、SOI层10以及MOSFET晶体管14所在氧化层12形成过孔17,过孔17可以通过干蚀刻,例如反应离子等离子体蚀刻等方法形成。然后在过孔17的侧壁上首先可以形成隔离层18,例如将氧化物或者Si3N4等隔离材料沉积到过孔17中。接着,在隔离层18的侧壁上可沉积埋层20,埋层20可以防止后续工艺中填充到过孔17中的金属导电材料向外迁移,而进入半导体器件中从而破坏MOSFET晶体管14的性能。在一个实施例中,埋层20包含的材料选自包括Ru、Ta、TaN、Ti、TiN、TaSiN、TiSiN、TiW以及WN的组合。
最后,在过孔17中填充导电材料22,例如铜(Cu)、铝(Al)或者钨(W)的金属,也可以是导电聚合物、金属硅化物等等,从而形成用于3D集成电路晶片互连的TSV孔。在本发明实施例中,导电材料22为金属材料,然后对沉积到过孔17中的金属材料进行平整化,以及化学机械抛光(CMP),从而形成TSV孔。关于TSV孔的形成可以是现有任意合适的工艺方法,这里不再赘述。
图1d显示了连接MOSFET晶体管14与TSV孔的互连结构的结构示意图,其中互连结构包括形成在TSV孔上方并与TSV孔连通的过孔26、形成在MOSFET晶体管14对应的后道互连结构16上方的过孔24、以及连接过孔24和过孔26的金属互连线28。这样,通过上述互连结构可以将TSV孔与MOSFET晶体管14连接起来。从而,通过进一步将该晶片器件上的互连结构与其他晶片对应的互连结构进行多晶片连接,则可以实现3D集成电路结构。
为了将图1d结构的晶片器件与其他晶片连接形成3D集成电路,或者为形成的3D集成电路供电或进行外部信号的输入/输出(I/O),需要将对应的晶片底部的TSV孔进行研磨或者变薄处理,从而暴露出TSV孔中的金属材料以进行相应的导电连接。
如图1e所示,首先需要将晶片器件翻转过来,并对其底部进行研磨或减薄处理,从而暴露晶片底部的TSV孔中的金属材料22。因此,在该研磨工艺中,暴露出的金属离子会从底部扩散到晶片中。通过本发明的扩散停止层6,金属离子被阻挡而不能够进入到SOI层10,从而进入其上方的MOSFET晶体管14中。这样,可以增加MOSFET晶体管14的可靠性。
通过上述步骤,即得到图1e所示用于3D集成电路的晶片器件100。
图2和图3给出了利用图1实施例的晶片器件100形成的第一实施例的3D集成电路的部分结构。
在图2中,显示了形成3D集成电路的晶片器件100与外部电路300的连接示意图,这里外部电路300可以是外部电源或者外部信号I/O,其中晶片器件100暴露的导电材料22连接到外部电路300,从而为3D集成电路供电或进行外部信号传输。
在图3中,除了显示3D集成电路的晶片器件100与外部电路300的连接之外,还显示了晶片器件100与3D集成电路的另一个晶片器件200的连接示意图。如图3所示,晶片器件200被翻转,其上设置有过孔42,过孔42与晶片器件200上构建的MOSFET晶体管45的后道互连43连接。晶片器件200的MOSFET晶体管45、后道互连43以及过孔42的构建与晶片器件100相同,即MOSFET晶体管45设置在SOI层44上方的氧化层46,过孔42设置在氧化层46上方的氧化层48中。
这样,晶片器件100通过其互连结构(即过孔24、26以及金属互连线28)与过孔42连接,从而将晶片器件100的TSV孔连接到晶片器件200上,即以顶对底的形式连接晶片器件100和晶片器件200,实现3D集成电路的多晶片堆叠结构。
在一个实施例中,晶片器件200可以具有与晶片器件100相同的半导体结构设置。这样,当晶片器件200的底部与形成3D集成电路的其他晶片结合时,通过其内部布设的扩散停止层,也可以来防止底部TSV孔中暴露的金属离子扩散到其MOSFET器件45中。尤其是在高温结合工艺中,该扩散停止层更有效地防止了金属离子向MOSFET器件45的扩散。
图4给出了利用图1实施例的晶片器件100形成的第二实施例的3D集成电路的部分结构示意图。
在图4中,显示了形成3D集成电路的晶片器件100与另一个晶片器件400的连接示意图。如图4所示,晶片器件400被翻转,其上设置有过孔52,过孔52与晶片器件400上构建的MOSFET晶体管55的后道互连53连接。晶片器件400的MOSFET晶体管55、后道互连53以及过孔52的构建与晶片器件100相同,即MOSFET晶体管55设置在SOI层54上方的氧化层56,过孔52设置在氧化层56上方的氧化层58中。
这样,晶片器件100通过其TSV孔暴露的金属导电材料与过孔52连接,从而将晶片器件100的TSV孔连接到晶片器件200上,即以底对顶的形式连接晶片器件100和晶片器件400,实现3D集成电路的多晶片堆叠结构。尤其是在高温结合工艺中,该扩散停止层更有效地防止了金属离子向MOSFET器件14中的扩散。
在一个实施例中,晶片器件400可以具有与晶片器件100相同的半导体结构设置。这样,当晶片器件400的底部再与形成3D集成电路的其他晶片或外部电路结合时,通过其内部布设的扩散停止层,可以来防止其对应底部TSV孔中暴露的金属离子扩散到其MOSFET器件14中。
在本发明中,对于构建在SOI层上的MOSFET器件,在研磨晶片或后续的晶片结合工艺中,通过设置扩散停止层可以防止填充到TSV孔中的金属材料例如Cu、Al、W等,或者晶片中存在的其他金属杂质,例如Fe、Na等的离子扩散到MOSFET晶体管中,从而能够提供具有良好性能的MOSFET器件及相应构成的3D集成电路。
尽管已经示出和描述了本发明的实施例,对于本领域的普通技术人员而言,可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型,本发明的范围由所附权利要求及其等同限定。
Claims (27)
1.一种3D集成电路结构,其特征在于,所述集成电路结构包括:
第一晶片,包括:
衬底;
形成在所述衬底上的扩散停止层;
形成在所述扩散停止层上的绝缘体上硅SOI层;
形成在所述SOI层上的金属氧化物半导体场效应晶体管MOSFET;
贯穿所述衬底、所述扩散停止层、所述SOI层以及所述MOSFET晶体管层形成的硅通孔TSV;以及
连接所述MOSFET晶体管与所述硅通孔TSV的第一互连结构;
其中,研磨所述第一晶片的底部以暴露出填充有金属材料的所述TSV孔,并通过所述TSV孔连接所述第一晶片底部到外部电路或者第二晶片的第二互连结构上。
2.如权利要求1所述的集成电路结构,其特征在于,所述扩散停止层为氮化物。
3.如权利要求2所述的集成电路结构,其特征在于,所述氮化物包括Si3N4或者SiCN。
4.如权利要求1到3中任意一项所述的集成电路结构,其特征在于,所述扩散停止层的厚度范围在5~100nm之间。
5.如权利要求1所述的集成电路结构,其特征在于,所述第一晶片还包括形成在所述衬底与所述扩散停止层之间的第一氧化层。
6.如权利要求5所述的集成电路结构,其特征在于,所述第一氧化层的厚度范围在5~10nm之间。
7.如权利要求1所述的集成电路结构,其特征在于,所述第一晶片还包括形成在所述扩散停止层与所述SOI层之间的第二氧化层。
8.如权利要求7所述的集成电路结构,其特征在于,所述第二氧化层的厚度范围在5~200nm之间。
9.如权利要求1所述的集成电路结构,其特征在于,所述TSV孔还包括在填充所述金属材料之前沉积的埋层。
10.如权利要求9所述的集成电路结构,其特征在于,所述埋层包含的材料选自包括Ru、Ta、TaN、Ti、TiN、TaSiN、TiSiN、TiW以及WN的组。
11.一种形成3D集成电路的方法,其特征在于,所述方法包括以下步骤:
形成第一晶片,其中形成所述第一晶片包括:
形成衬底;
在所述衬底上形成扩散停止层;
在所述扩散停止层上形成SOI层;
在所述SOI层上形成MOSFET晶体管;
形成贯穿所述衬底、所述扩散停止层、所述SOI层以及所述MOSFET晶体管层的TSV孔;以及
形成连接所述MOSFET晶体管与所述硅通孔TSV的互连结构;
研磨所述第一晶片的底部以暴露出填充有金属材料的所述TSV孔;以及
通过所述TSV孔连接所述第一晶片底部到外部电路或者第二晶片的互连结构上。
12.如权利要求11所述的方法,其特征在于,所述扩散停止层为氮化物。
13.如权利要求12所述的方法,其特征在于,所述氮化物包括Si3N4或者SiCN。
14.如权利要求11到13中任意一项所述的方法,其特征在于,所述扩散停止层的厚度范围在5~100nm之间。
15.如权利要求11所述的方法,其特征在于,还包括在所述衬底与所述扩散停止层之间形成第一氧化层的步骤。
16.如权利要求15所述的方法,其特征在于,所述第一氧化层的厚度范围在5~10nm之间。
17.如权利要求11所述的方法,其特征在于,还包括在所述扩散停止层与所述SOI层之间形成第二氧化层的步骤。
18.如权利要求17所述的方法,其特征在于,所述第二氧化层的厚度范围在5~200nm之间。
19.如权利要求11所述的方法,其特征在于,还包括在填充所述金属材料到所述TSV孔之前沉积埋层到所述TSV孔中的步骤。
20.如权利要求19所述的方法,其特征在于,所述埋层包含的材料选自包括Ru、Ta、TaN、Ti、TiN、TaSiN、TiSiN、TiW以及WN的组。
21.一种半导体器件,其特征在于,所述半导体器件包括:
衬底;
形成在所述衬底上的扩散停止层;
形成在所述扩散停止层上的SOI层;
形成在所述SOI层上的MOSFET晶体管;
贯穿所述衬底、所述扩散停止层、所述SOI层以及所述MOSFET晶体管层形成的硅通孔TSV;以及
连接所述MOSFET晶体管与所述硅通孔TSV的互连结构。
22.如权利要求21所述的半导体器件,其特征在于,所述扩散停止层为氮化物。
23.如权利要求22所述的半导体器件,其特征在于,所述氮化物包括Si3N4或者SiCN。
24.如权利要求21到23中任意一项所述的半导体器件,其特征在于,所述扩散停止层的厚度范围在5~100nm之间。
25.如权利要求21所述的半导体器件,其特征在于,还包括形成在所述衬底与所述扩散停止层之间的第一氧化层,所述第一氧化层的厚度范围在5~10nm之间。
26.如权利要求21所述的半导体器件,其特征在于,还包括形成在所述扩散停止层与所述SOI层之间的第二氧化层,所述第二氧化层的厚度范围在5~200nm之间。
27.如权利要求21所述的半导体器件,其特征在于,所述TSV孔还包括在填充所述金属材料之前沉积的埋层。
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US9064849B2 (en) | 2015-06-23 |
US20110227158A1 (en) | 2011-09-22 |
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