CN112534553B - Rf半导体装置及其制造方法 - Google Patents
Rf半导体装置及其制造方法 Download PDFInfo
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- CN112534553B CN112534553B CN201980050433.9A CN201980050433A CN112534553B CN 112534553 B CN112534553 B CN 112534553B CN 201980050433 A CN201980050433 A CN 201980050433A CN 112534553 B CN112534553 B CN 112534553B
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Classifications
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Abstract
本公开涉及一种射频装置,其包含:具有后段工艺部分和前段工艺部分的装置区、第一凸块结构、第一模制化合物,以及第二模制化合物。所述FEOL部分包含有源层、接触层和隔离区段。所述有源层和所述隔离区段位于所述接触层上方,且所述有源层由所述隔离区段围绕。所述BEOL部分形成于所述FEOL部分下方,且所述第一凸块结构和所述第一模制化合物形成于所述BEOL部分下方。每个第一凸块结构由所述第一模制化合物部分地囊封,且经由所述BEOL部分内的连接层电耦合到所述FEOL部分。所述第二模制化合物位于所述有源层上方而无硅材料,其电阻率介于5欧姆‑厘米与30000欧姆‑厘米之间。
Description
相关申请案
本申请要求于2018年7月2日提交的第62/692,945号临时专利申请的权益,所述临时专利申请的公开内容特此以全文引用的方式并入本文中。
本申请关于标题为“具有增强性能的RF装置及其形成方法(RF DEVICES WITHENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME)”的同时提交的第___号美国专利申请,所述美国专利申请的公开内容特此以全文引用的方式并入本文中。
技术领域
本公开涉及一种射频(RF)装置及其制造方法,且更确切地说,涉及具有增强的热和电性能的RF装置以及用以提供具有增强的性能的RF装置的晶片级封装工艺。
背景技术
蜂窝式及无线装置的广泛利用驱动射频(RF)技术的快速发展。在其上制造RF装置的衬底在实现RF技术的高水平性能方面起着重要作用。在常规硅处置衬底上制造RF装置可能会受益于硅材料的低成本、大规模的晶片生产能力、完善的半导体设计工具以及完善的半导体制造技术。
尽管将常规硅处置衬底用于RF装置制造具有益处,但在工业中众所周知,常规硅处置衬底对于RF装置可能具有两个不合需要的特性:谐波失真和低电阻率值。谐波失真是在硅处置衬底上构建的RF装置中实现高水平线性度的关键障碍。此外,高速且高性能的晶体管更紧密地集成在RF装置中。因此,由于集成在RF装置中的大量晶体管、通过晶体管的大量电力和/或晶体管的高操作速度,RF装置生成的热量将显著增大。因此,需要以实现更好散热的配置来封装RF装置。
为了适应RF装置的增大的热生成且减小RF装置的有害谐波失真,因此,本公开的目的是提供一种改进的封装工艺以增强热和电性能。另外,还需要在不增大封装大小的情况下增强RF装置的性能。
发明内容
本公开涉及一种具有增强的热和电性能的射频(RF)装置及其制造方法。所公开的RF装置包含装置区、数个第一凸块结构、第一模制化合物和第二模制化合物。所述装置区包含具有数个连接层的后段工艺(BEOL)部分和位于所述BEOL部分上方的前段工艺(FEOL)部分。所述FEOL部分包含有源层、接触层和隔离区段。本文中,所述有源层和所述隔离区段两者皆位于所述接触层上方。所述有源层由所述隔离区段围绕,且不在竖直上延伸超出所述隔离区段。所述第一凸块结构形成于所述BEOL部分的底表面处,且经由所述BEOL部分内的所述连接层电耦合到所述FEOL部分。所述第一模制化合物形成于所述BEOL部分的所述底表面上,且部分地囊封每个第一凸块结构,使得每个第一凸块结构的底部部分不由所述第一模制化合物覆盖。所述第二模制化合物位于所述FEOL部分的所述有源层上方而无硅材料,其电阻率介于5欧姆-厘米与30000欧姆-厘米之间。
在所述RF装置的一个实施例中,所述第二模制化合物的一部分位于所述隔离区段上方。
在所述RF装置的一个实施例中,所述隔离区段在竖直上延伸超出所述有源层的顶表面,以在所述隔离区段内且在所述有源层上方界定开口,其中所述第二模制化合物填充所述开口。
根据另一个实施例,所述RF装置进一步包含直接在所述有源层的所述顶表面上方且在所述开口内的钝化层。本文中,所述钝化层由二氧化硅、氮化硅或两者的组合形成,且与所述第二模制化合物接触。
根据另一实施例,所述RF装置进一步包含直接在所述有源层的所述顶表面上方且在所述开口内的界面层。本文中,所述界面层由硅锗(SiGe)形成,且直接连接到第二模具。
在所述RF装置的一个实施例中,所述第二模制化合物与所述有源层的所述顶表面接触。
在所述RF装置的一个实施例中,每个隔离区段的顶表面与所述有源层的顶表面是共面的。本文中,所述第二模制化合物位于所述有源层和所述隔离区段两者上方。
根据另一实施例,所述RF装置进一步包含数个第二凸块结构。每个第二凸块结构与对应的第一凸块结构接触,且从所述第一模制化合物突出。
在所述RF装置的一个实施例中,所述第二凸块结构由焊膏、导电环氧树脂或可回流金属形成。
在所述RF装置的一个实施例中,所述第一凸块结构是焊球或铜柱。
在所述RF装置的一个实施例中,所述第一模制化合物由与所述第二模制化合物相同的材料形成。本文中,所述第一模制化合物和所述第二模制化合物的热导率大于1W/m·K,且介电常数小于8或介电常数在3与5之间。
在所述RF装置的一个实施例中,所述第一模制化合物与所述第二模制化合物由不同的材料形成。
在所述RF装置的一个实施例中,所述第一模制化合物是透明的。
在所述RF装置的一个实施例中,所述FEOL部分经配置以提供开关场效应晶体管(FET)、二极管、电容器、电阻器和电感器中的至少一个。
根据示例性过程,首先提供具有数个装置裸片的装置晶片。本文中,每个装置裸片包含第一凸块结构和装置区,所述装置区具有BEOL部分和在所述BEOL部分上方的FEOL部分。所述FEOL部分包含有源层、接触层和隔离区段。本文中,所述有源层和所述隔离区段位于所述接触层上方,所述隔离区段围绕所述有源层,且所述有源层不在竖直上延伸超出所述隔离区段。每个BEOL部分的底表面的组合形成所述装置晶片的底表面。所述第一凸块结构形成于每个BEOL部分的所述底表面处。此外,由SiGe形成的界面层直接在每个装置裸片的所述有源层上方。硅处置衬底直接在每个界面层的上方。接下来,将第一模制化合物涂覆在所述装置晶片的所述底表面上方以囊封每个装置裸片的所述第一凸块结构。接着完全移除所述硅处置衬底。在移除了所述硅处置衬底的每个装置裸片的所述有源层上方形成第二模制化合物。在所述第二模制化合物与每个有源层之间不存在硅材料。在形成所述第二模制化合物之后,将所述第一模制化合物减薄,直到暴露每个第一凸块结构的底部部分。
根据另一实施例,所述示例性过程进一步包含在涂覆所述第二模制化合物之前移除所述界面层。本文中,在涂覆所述第二模制化合物之后,每个装置裸片的所述有源层与所述第二模制化合物接触。
根据另一实施例,所述示例性过程进一步包含在涂覆所述第二模制化合物之前,移除所述界面层且直接在每个装置裸片的所述有源层上方施加钝化层。本文中,所述钝化层由二氧化硅、氮化硅或两者的组合形成。在涂覆所述第二模制化合物之后,所述钝化层与所述第二模制化合物接触。
根据另一实施例,所述示例性过程进一步包含在使所述第一模制化合物减薄之后形成数个第二凸块结构。本文中,每个第二凸块结构与对应的第一凸块结构的暴露底部部分接触,且从所述第一模制化合物突出。
根据另一实施例,所述示例性过程进一步包含在涂覆所述第一模制化合物之前,在所述装置晶片的所述底表面的外围处形成至少一个窗口组件。本文中,在涂覆所述第一模制化合物之后,所述至少一个窗口组件由所述第一模制化合物囊封。
在所述示例性过程的一个实施例中,所述至少一个窗口组件比每个第一凸块结构高,使得在所述减薄过程期间,所述至少一个窗口组件在所述第一凸块结构之前暴露。
在所述示例性过程的一个实施例中,提供所述装置晶片开始于提供Si-SiGe-Si晶片,所述Si-SiGe-Si晶片包含公共硅外延层、在所述公共硅外延层上方的公共界面层以及在所述公共界面层上方的所述硅处置衬底。所述公共界面层由SiGe形成。接着执行互补金属氧化物半导体(CMOS)过程以提供包含数个装置区的前体晶片。本文中,所述隔离区段延伸穿过所述公共硅外延层和所述公共界面层且延伸到所述硅处置衬底中,使得所述公共界面层分离为数个个别界面层,且所述公共硅外延层分离成数个个别硅外延层。所述装置区的每个有源层由对应的个别硅外延层形成。每个个别界面层直接位于对应有源层的顶表面上方,且所述硅处置衬底直接位于所述个别界面层上方。接下来,在每个BEOL部分的所述底表面处形成所述第一凸块结构,以从所述装置区完成所述装置裸片。
在所述示例性过程的一个实施例中,提供所述装置晶片开始于提供Si-SiGe-Si晶片,所述Si-SiGe-Si晶片包含公共硅外延层、在所述公共硅外延层上方的公共界面层以及在所述公共界面层上方的所述硅处置衬底。所述公共界面层包含SiGe,且具有连接的数个界面层。接着执行CMOS过程以提供包含数个装置区的前体晶片。本文中,所述隔离区段延伸穿过所述公共硅外延层且延伸到所述公共界面层中,使得所述公共硅外延层分离成数个个别硅外延层,且所述界面层保持连接。所述装置区的每个有源层由对应的个别硅外延层形成。每个界面层直接位于对应有源层的顶表面上方,且所述硅处置衬底保持直接位于所述公共界面层上方。接下来,在每个BEOL部分的所述底表面处形成所述第一凸块结构,以从所述装置区完成所述装置裸片。
本领域的技术人员在结合附图阅读优选实施例的以下详细描述之后,将了解本公开的范围且认识到本公开的额外方面。
附图说明
并入在本说明书中并且形成本说明书的一部分的附图说明本公开的若干方面,且与描述一起用以解释本公开的原理。
图1展示根据本公开的一个实施例的具有增强的热和电性能的示例性射频(RF)装置。
图2至图13提供示例性晶片级封装工艺,其说明制造图1所示的示例性RF装置的步骤。
应理解,为了清楚地说明,图1至图13可能未按比例绘制。
具体实施方式
下文阐述的实施例表示使本领域的技术人员能够实践实施例的必要信息,且说明实践实施例的最佳模式。在根据附图阅读以下描述后,本领域的技术人员将理解本公开的概念且将认识到本文中并未特定阐释的这些概念的应用。应理解,这些概念和应用落入本公开和所附权利要求书的范围内。
应理解,虽然术语第一、第二等可在本文中用以描述各种元件,但这些元件不应受这些术语限制。这些术语仅用于区分一个元件与另一元件。举例来说,在不脱离本公开的范围的情况下,第一元件可称为第二元件,且类似地,第二元件可称为第一元件。如本文中所使用,术语“和/或”包含相关联所列项目中的一或多者的任何和所有组合。
将理解,当例如层、区或衬底的元件被称为在另一元件“上”或延伸“到”另一元件“上”时,其可以直接在所述另一元件上或直接延伸到另一元件上,或也可能存在介入元件。相比之下,当元件被称为“直接在”另一元件“上”或“直接”延伸“到”另一元件“上”时,不存在介入元件。同样,应理解,当例如层、区或衬底的元件被称为在另一元件“上方”或在其“上方”延伸时,其可直接在另一元件上方或在另一元件上方延伸,或也可存在介入元件。相比之下,当元件被称为“直接在”另一元件“上方”或“直接”在另一元件“上方”延伸时,不存在介入元件。还应理解,当元件被称为“连接”或“耦合”到另一元件时,其可直接连接或耦合到另一元件,或可存在介入元件。相比之下,当元件被称作“直接连接”或“直接耦合”到另一元件时,不存在插入元件。
在本文中可使用例如“下方”或“上方”或“上部”或“下部”或“水平”或“垂直”的相对术语来描述一个元件、层或区与另一元件、层或区的关系,如图所示。应理解,这些术语和上文所论述的术语既定涵盖除图式中所描绘的定向以外的装置的不同定向。
本文中所使用的术语仅出于描述特定实施例的目的,且并非意在限制本公开。如本文中所使用,除非上下文另外明确指示,否则单数形式“一”和“所述”既定还包含复数形式。应进一步理解,术语“包括(comprises、comprising)”、“包含(includes及/或including)”在本文中使用时指定所陈述的特征、整数、步骤、操作、元件及/或组件的存在,但并不排除一或多个其它特征、整数、步骤、操作、元件、组件及/或其群组的存在或添加。
除非另外定义,否则本文中所使用的所有术语(包含技术和科学术语)具有与本公开所属领域的普通技术人员通常所理解的相同的意义。将进一步理解,本文中所使用的术语应解释为在本说明书及相关技术的上下文中具有与其含义一致的含义且将不在理想化或过度正式意义上进行解释,除非本文中明确地如此定义。
预计在未来几年内常规射频绝缘体上硅(RFSOI)晶片会逐渐出现短缺,正在设计替代技术,以解决对使用硅晶片的高电阻率、富阱层形成和智能切割SOI晶片过程的需要。这些替代技术中的一个是基于使用硅锗(SiGe)界面层代替硅衬底与硅外延层之间的内埋氧化物层(BOX),然而,这些替代技术也会由于硅衬底而遭受有害的失真效应,类似于RFSOI技术中观察到的失真效应。本公开涉及具有增强的热性能和电性能的射频(RF)装置及用于制造其的晶片级封装工艺,其基于此Si-SiGe-Si结构,而没有来自硅衬底的有害失真效应。
图1展示根据本公开的一个实施例的由Si-SiGe-Si晶片形成的示例性RF装置10(在以下段落中描述处理细节)。出于此说明的目的,示例性RF装置10包含装置区12、第一凸块结构14、第一模制化合物16和第二模制化合物18。
详细地说,装置区12包含前段工艺(FEOL)部分20和在FEOL部分20下方的后段工艺(BEOL)部分22。在一个实施例中,FEOL部分20经配置以提供开关场效应晶体管(FET),且包含有源层24和接触层26。本文中,有源层24具有源极28、漏极30以及在源极28与漏极30之间的通道32。源极28、漏极30和通道32由相同的硅外延层形成。接触层26形成于有源层24的下方,且包含栅极结构34、源极触点36、漏极触电38和栅极触电40。栅极结构34可由氧化硅形成,且在通道32下方水平(从源极28下方到漏极30下方)延伸。源极触点36连接到源极28且在其下方,漏极触点38连接到漏极30且在其下方,且栅极触点40连接到栅极结构34且在其下方。绝缘材料42可形成于源极触点36、漏极触点38、栅极结构34和栅极触点40周围以电分离源极28、漏极30和栅极结构34。在不同应用中,FEOL部分20可具有不同的FET配置或提供不同的装置组件,例如二极管、电容器、电阻器和/或电感器。
此外,FEOL部分20还包含隔离区段44,其位于接触层26的绝缘材料42上方且围绕有源层24。隔离区段44经配置以将RF装置10,特别是将有源层24与形成于公共晶片(未展示)中的其它装置电分离。本文中,隔离区段44可从接触层26的顶表面延伸,且在竖直上延伸超出有源层24的顶表面,以界定在隔离区段44内且在有源层24上方的开口46。第二模制化合物18填充开口46,且可在隔离区段44上方延伸。隔离区段44可由二氧化硅形成,二氧化硅可抵抗例如氢氧化钾(KOH)、氢氧化钠(NaOH)和乙酰胆碱(ACH)的蚀刻化学物质。
在一些应用中,RF装置10可进一步包含直接在有源层24的顶表面上方且在开口46内的钝化层48,其由二氧化硅、氮化硅或两者的组合形成。由此,第二模制化合物18直接在钝化层48上方。钝化层48经配置以终止有源层24的表面结合,这可能导致不希望的泄漏。钝化层还可充当屏障,且经配置以保护有源层24免受湿气或离子污染。如果省略钝化层48,则第二模制化合物18可能会与有源层24的顶表面接触。在一些应用中,RF装置10可进一步包含界面层(在以下段落中描述且未在本文中展示),其由SiGe直接形成于有源层24的顶表面上方和开口46内。由此,第二模制化合物18可直接在界面层上方。界面层来自用于制造RF装置10的Si-SiGe-Si晶片(在以下段落中描述处理细节)。如果省略界面层,则第二模制化合物18可能会与有源层24的顶表面接触。注意,无关于钝化层48或界面层,在第二模制化合物18与有源层24的顶表面之间不存在没有锗含量的硅晶体。钝化层48和界面层两者皆为硅合金。
另外,在一些应用中,每个隔离区段44的顶表面与有源层24的顶表面是共面的(未展示),且省略了开口46。第二模制化合物18位于有源层24和FEOL部分20的隔离区段44两者上方。注意,有源层24从不在竖直上超出隔离区段44。
BEOL部分22在FEOL部分20下方,且包含形成于介电层52内的多个连接层50。第一凸块结构14形成于BEOL部分22的底表面上,且经由BEOL部分22的连接层50电耦合到FEOL部分20(在此图示中为源极触点36和漏极触点38)。第一模制化合物16形成于BEOL部分22下方,且囊封每个第一凸块结构14的各侧,使得每个第一凸块结构14的底部部分不由第一模制化合物16覆盖。
本文中,第一凸块结构14不从第一模制化合物16的底表面突出。在一些应用中,希望在RF装置10的底表面具有突出结构,以促进且改进裸片附接(到印刷电路板)操作的可靠性。因此,RF装置10可进一步包含数个第二凸块结构54。每个第二凸块结构54与对应的第一凸块结构14接触,且从第一模制化合物16的底表面突出。第一凸块结构14可为焊球或铜柱。第二凸块结构54可由焊膏、导电环氧树脂或可回流金属形成。
在装置区12中生成的热可向上行进到第二模制化合物18的在有源层24上方的底部部分,且接着将向下穿过装置区12和第一凸块结构14,其将耗散所述热。另外,在装置区12中生成的热也可直接行进通过第一模制化合物16进行传导。因此,非常希望第一模制化合物16和第二模制化合物18两者皆具有高热导率。第一模制化合物16和第二模制化合物18可具有大于1W/m·K或大于10W/m·K的热导率。此外,第一模制化合物16和第二模制化合物18可具有小于8或在3与5之间的低介电常数以产生低RF耦合。第一模制化合物16可由与第二模制化合物18相同或不同的材料形成。在一个实施例中,第一模制化合物16和第二模制化合物18两者皆可由热塑性塑料或热固性聚合物材料(例如PPS(聚苯硫醚),掺杂有氮化硼、氧化铝、碳纳米管或类金刚石热添加剂的包覆模制环氧树脂等)形成。另外,第一模制化合物16可为透明的,且可具有在25μm与500μm之间的厚度(基于第一凸块结构14的大小)。第二模制化合物18的厚度是基于RF装置10的所需热性能、装置布局、与第一凸块结构14的距离以及封装和组装的细节。第二模制化合物18可具有在200μm与500μm之间的厚度。
图2至图13提供示例性晶片级封装工艺,其说明制造图1所示的示例性RF装置10的步骤。尽管示例性步骤说明为系列,但示例性步骤不一定取决于次序。一些步骤可能以与所呈现的次序不同的次序进行。另外,本公开的范围内的过程可包含比图2至图13中说明的过程更少或更多的步骤。
首先,如图2如中所说明,提供Si-SiGe-Si晶片56。Si-SiGe-Si晶片56包含公共硅外延层58、在公共硅外延层58上方的公共界面层60,和在公共界面层60上方的硅处置衬底62。本文中,由SiGe形成的公共界面层60将公共硅外延层58与硅处置衬底62分离。
本文中,公共硅外延层58由具有所需硅外延特性以形成电子装置的装置级硅材料形成。公共界面层60由具有任何摩尔比的Si和Ge的合金形成。Ge浓度越高,硅处置衬底62与公共界面层60之间的蚀刻选择性越好,但公共硅外延层58的外延生长也变得越困难。在一个实施例中,公共界面层60可具有大于15%或大于25%的Ge浓度。Ge浓度在整个公共界面层60中可为均一的。在一些应用中,Ge浓度可在竖直上递变(在1%与50%之间),以便为公共硅外延层58的生长产生必要的应变消除。硅处置衬底62可由常规的低成本、低电阻率和高介电常数硅组成。公共硅外延层58的电阻率高于硅处置衬底62,且公共硅外延层58的谐波生成率低于硅处置衬底62。公共硅外延层58的厚度可在700nm与2000nm之间,公共界面层60的厚度可在100nm与1000nm之间,且硅处置衬底62的厚度可在200μm与500μm之间。
接下来,如图3A中所说明,对Si-SiGe-Si晶片56执行互补金属氧化物半导体(CMOS)处理,以提供具有数个装置区12的前体晶片64。出于此说明的目的,每个装置区12的FEOL部分20经配置以提供开关FET。在不同应用中,FEOL部分20可具有不同的FET配置或提供不同的装置组件,例如二极管、电容器、电阻器和/或电感器。
在此实施例中,每个装置区12的隔离区段44延伸穿过公共硅外延层58和公共界面层60,且延伸到硅处置衬底62中。由此,公共界面层60分离成数个个别界面层60I,且公共硅外延层58分离成数个个别硅外延层58I,其中的每一个用于在一个装置区12中形成对应有源层24。
有源层24的顶表面与对应的界面层60I接触。硅处置衬底62位于每个个别界面层60I上方,且硅处置衬底62的部分可位于隔离区段44上方。装置区12的至少包含多个连接层50和介电层52的BEOL部分22形成于FEOL部分20下方。某些连接层50的底部部分经由介电层52暴露于BEOL部分22的底表面处。
在另一实施例中,隔离区段44不延伸到硅处置衬底62中。相反,隔离区段44仅延伸穿过公共硅外延层58且延伸到公共界面层60中,如图3B中所说明。本文中,公共界面层60保持连续,且个别界面层60I彼此连接。公共界面层60直接位于每个有源层24的顶表面上方,且直接位于每个隔离区段44的顶表面上方。硅处置衬底62保持在公共界面层60上方。另外,隔离区段44可延伸穿过公共硅外延层58,但不延伸到公共界面层60中。每个隔离区段44的顶表面和每个有源层24的顶表面可为共面的(未展示)。公共界面层60在每个隔离区段44和每个有源层24上方,且硅处置衬底62保持在公共界面层60上方。
接着,在每个BEOL部分22的底表面处形成第一凸块结构14,以提供装置晶片66,如图4中所描绘。每个BEOL部分22的底表面的组合形成装置晶片66的底表面。装置晶片66包含数个装置裸片68,与装置区12相比,每个装置裸片进一步包含第一凸块结构14。每个第一凸块结构14与对应连接层50的暴露部分接触。本文中,第一凸块结构14经由BEOL部分22的连接层50电耦合到FEOL部分20(在此说明中为源极触点36和漏极触点38)。第一凸块结构14可通过焊球凸起技术或铜柱封装技术形成。每个第一凸块结构14从BEOL部分22的底表面突出20μm与350μm之间。
接下来,如图5中所说明,可在一个BEOL部分22的一个或多个晶片标记(未展示)所位于的底表面处形成至少一个窗口组件70。本文中,晶片标记指示晶片的关键位置,将在随后的单分和/或组装过程中将其用于对准。在一个实施例中,至少一个窗口组件70位于装置晶片66的底表面的外围。至少一个窗口组件70可由透明材料(例如:透明聚硅氧材料)形成,使得可经由至少一个窗口组件70看到晶片标记。此外,至少一个窗口组件70可由易于移除的材料(例如:丙烯酸聚合物)形成,使得在容易地移除至少一个窗口组件70(更多详情见以下论述)之后将看到晶片标记。至少一个窗口组件70具有大于每个第一凸块结构14的高度的高度,且不连接到任何第一凸块结构14。注意,至少一个窗口组件70是可选的。在一些应用中,可省略在一个BEOL部分22的底表面处形成至少一个窗口组件70。
第一模制化合物16涂覆在装置晶片66的底表面上方,且囊封每个第一凸块结构14和至少一个窗口组件70,如图6中所说明。第一模制化合物16可通过各种程序涂覆,例如压缩模制、片材模制、包覆模制、传递模制、围坝填充囊封或丝网印刷囊封。第一模制化合物16可具有大于1W/m·K或大于10W/m·K的优良热导率,且可具有小于8或在3与5之间的介电常数。第一模制化合物16可具有在25μm与500μm之间的厚度。第一模制化合物16可抵抗例如KOH、NaOH和ACH的蚀刻化学物质。在一些应用中,第一模制化合物16可由透明材料形成。由此,由于可经由第一模制化合物16看到晶片的所有位置,因此不需要在BEOL部分22的底表面处形成至少一个窗口组件70。接着使用固化处理(未展示)来硬化第一模制化合物16。固化温度介于100℃与320℃之间,具体取决于哪种材料用作第一模制化合物16。
在形成第一模制化合物16之后,选择性地移除硅处置衬底62以提供经蚀刻晶片72,其中在每个界面层60I上停止选择性移除,如图7中所说明。如果隔离区段44在竖直上延伸超出界面层60I,则移除硅处置衬底62将在每个有源层24上方和隔离区段44内提供开口46。移除硅处置衬底62可通过化学机械研磨和利用湿式/干式蚀刻剂化学物质(其可为TMAH、KOH、NaOH、ACH或XeF2)的蚀刻过程来提供,或通过蚀刻过程本身提供。作为实例,可将硅处置衬底62研磨到较薄的厚度以减少随后的蚀刻时间。接着执行蚀刻过程以完全移除剩余的硅处置衬底62。由于硅处置衬底62与界面层60I具有不同的特性,所以其对于相同的蚀刻技术可能具有不同反应(例如:对于相同蚀刻剂的不同蚀刻速度)。因此,蚀刻系统能够识别界面层60I的存在,且能够指示何时停止蚀刻过程。
在移除过程期间,不移除隔离区段44,且因此保护每个FEOL部分20。第一模制化合物16保护每个BEOL部分22的底表面。本文中,在移除过程之后,暴露每个隔离区段44的顶表面和每个界面层60I的顶表面。如果隔离区段44延伸到公共界面层60中(如图3B所示),或每个隔离区段44的顶表面与每个有源层24的顶表面是共面的(未展示),则仅公共界面层60的顶表面将暴露(未展示)。
由于SiGe材料的窄间隙性质,界面层60I(或公共界面层60)可能导电。界面层60I可能在有源层24的源极28与漏极30之间引起明显的泄漏。因此,在例如FET应用的一些应用中,希望也移除界面层60I(或公共界面层60),如图8中所说明。界面层60I可通过与用于移除硅处置衬底62的蚀刻过程相同的蚀刻过程来移除,或可通过例如HCI干式蚀刻系统的另一蚀刻过程移除。如果界面层60I足够薄,则其可能完全耗尽,且可能不会在FEOL部分20的源极28与漏极30之间引起任何明显的泄漏。在此情况下,界面层60I可保持不变。
在一些应用中,可由二氧化硅、氮化硅或两者的组合形成的钝化层48可直接形成于每个FEOL部分20的有源层24上方,如图9中所说明。如果在每个有源层24上方且在隔离区段44内存在一个开口46,则钝化层48在开口46内。钝化层48经配置以终止有源层24的顶表面处的表面结合,这可能导致不希望的泄漏。钝化层48可通过CVD介电膜或钝化等离子体形成。
接着,将第二模制化合物18涂覆于经蚀刻晶片72上方,如图10中所说明。本文中,第二模制化合物18填充每个开口46,且与开口46内的钝化层48接触。此外,第二模制化合物18的部分可在隔离区段44上方延伸。如果在每个开口46中并未形成钝化层48,则第二模制化合物18与每个有源层24的顶表面(未展示)接触。如果界面层60I保持在每个有源层24的顶表面上方,则第二模制化合物18与界面层60I(未展示)接触。第二模制化合物18始终在每个有源层24上方。
第二模制化合物18可通过各种程序涂覆,例如压缩模制、片材模制、包覆模制、传递模制、围坝填充囊封或丝网印刷囊封。在第二模制化合物18的模制过程期间,第一模制化合物16为经蚀刻晶片72提供机械强度和刚度。随后进行固化处理(未展示)以硬化第二模制化合物18。固化温度介于100℃与320℃之间,具体取决于哪种材料用作第二模制化合物18。在固化处理之后,可使第二模制化合物18减薄和/或平坦化(未展示)。
接下来,减薄第一模制化合物16以提供模制装置晶片74,如图11中所说明。本文中,第一模制化合物囊封每个第一凸块结构14的侧面,且每个第一凸块结构14的底部部分暴露。此外,由于至少一个窗口组件70的高度大于每个第一凸块结构14的高度,因此至少一个窗口组件70的底部部分也经由第一模制化合物16暴露。减薄程序可利用机械研磨工艺进行。在一个实施例中,至少一个窗口组件70可由透明材料形成,使得指示晶片的关键位置的晶片标记将经由至少一个窗口组件70被看到。在另一实施例中,至少一个窗口组件70可由不透明材料形成,使得指示晶片的关键位置的晶片标记将不会经由至少一个窗口组件70被看到。需要移除至少一个窗口组件70的额外步骤来暴露指示晶片的关键位置(未展示)的晶片标记。
另外,在一些应用中,第二凸块结构54可在第一模制化合物16减薄之后形成,如图12中所说明。每个第二凸块结构54直接连接到对应的第一凸块结构14、电耦合到对应的FEOL部分20,且从第一模制化合物16的底表面突出。最后,将模制装置晶片74单分成个别RF装置10,如图13中所说明。单分步骤可通过在特定隔离区段44处的探测和切割过程来提供。个别RF装置10可使用数个裸片附接方法组装在PCB上。
所属领域的技术人员将认识到对本公开的优选实施例的改进和修改。所有此类改进和修改被视为在本文中公开的概念和所附的权利要求书的范围内。
Claims (15)
1.一种设备,其包括:
·装置区,其包含后段工艺BEOL部分和位于所述BEOL部分上方的前段工艺FEOL部分,其中:
·所述BEOL部分包括多个连接层;
·所述FEOL部分包括有源层、接触层和隔离区段;
·所述隔离区段包括二氧化硅;以及
·所述有源层和所述隔离区段位于所述接触层上方,其中所述隔离区段围绕所述有源层且在竖直上延伸超出所述有源层的顶表面以在所述隔离区段内且在所述有源层上方界定开口;
·多个第一凸块结构,其形成于所述BEOL部分的底表面处,其中所述多个第一凸块结构经由所述多个连接层电耦合到所述FEOL部分;
·第一模制化合物,其形成于所述BEOL部分的所述底表面上方且部分地囊封所述多个第一凸块结构中的每一个,其中所述多个第一凸块结构中的每一个的底部部分未被所述第一模制化合物覆盖;
·额外层,其直接在所述有源层的所述顶表面上方且在所述开口内,其中所述额外层是由二氧化硅和氮化硅中的至少一者形成的钝化层,或者是由硅锗SiGe形成的界面层;以及
·第二模制化合物,其位于所述额外层上方并且与所述额外层直接接触以填充所述开口,其中在所述第二模制化合物与所述有源层之间不存在没有锗含量的硅晶体。
2.根据权利要求1所述的设备,其中所述第二模制化合物的一部分位于所述隔离区段上方。
3.根据权利要求1所述的设备,其中:
·所述额外层是所述钝化层;且
·所述第二模制化合物与所述钝化层接触。
4.根据权利要求1所述的设备,其中:
·所述额外层是所述界面层;且
·所述第二模制化合物与所述界面层接触。
5.根据权利要求1所述的设备,其中所述第二模制化合物与所述有源层的所述顶表面接触。
6.根据权利要求1所述的设备,其进一步包括多个第二凸块结构,其中所述多个第二凸块结构中的每一个与所述多个第一凸块结构中的对应一个接触,且从所述第一模制化合物突出。
7.根据权利要求6所述的设备,其中所述多个第二凸块结构由焊膏、导电环氧树脂或可回流金属形成。
8.根据权利要求1所述的设备,其中所述多个第一凸块结构是焊球或铜柱。
9.根据权利要求1所述的设备,其中所述第一模制化合物由与所述第二模制化合物相同的材料形成。
10.根据权利要求9所述的设备,其中所述第一模制化合物和所述第二模制化合物的热导率大于1W/m·K。
11.根据权利要求9所述的设备,其中所述第一模制化合物和所述第二模制化合物的介电常数小于8。
12.根据权利要求9所述的设备,其中所述第一模制化合物和所述第二模制化合物的介电常数在3与5之间。
13.根据权利要求1所述的设备,其中所述第一模制化合物与所述第二模制化合物由不同的材料形成。
14.根据权利要求1所述的设备,其中所述第一模制化合物是透明的。
15.根据权利要求1所述的设备,其中所述FEOL部分经配置以提供开关场效应晶体管FET、二极管、电容器、电阻器和电感器中的至少一个。
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