TW202015193A - 具有增強之效能的rf裝置及其形成方法 - Google Patents
具有增強之效能的rf裝置及其形成方法 Download PDFInfo
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- TW202015193A TW202015193A TW108119536A TW108119536A TW202015193A TW 202015193 A TW202015193 A TW 202015193A TW 108119536 A TW108119536 A TW 108119536A TW 108119536 A TW108119536 A TW 108119536A TW 202015193 A TW202015193 A TW 202015193A
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Abstract
本揭示案係關於一種射頻裝置,該射頻裝置包括:一裝置區,該裝置區具有一後段產線(BEOL)部分及一前段產線(FEOL)部分;第一凸塊結構;一第一模塑料;及一第二模塑料。該FEOL部分包括一活化層、一接觸層及多個隔離區段。本文中,該活化層及該等隔離區段駐留於該接觸層上方,且該活化層被該等隔離區段環繞。該BEOL部分形成於該FEOL部分下面,且該等第一凸塊結構及該第一模塑料形成於該BEOL部分下面。每個第一凸塊結構部分地藉由該第一模塑料囊封,且經由該BEOL部分內之連接層電耦合至該FEOL部分。該第二模塑料駐留於該活化層上方,其間無一矽材料,該矽材料具有5歐姆-cm與30000歐姆-cm之間的一電阻率。
Description
本揭示案係關於一種射頻(RF)裝置及一種用於製造該RF裝置之方法,且更明確而言,係關於一種具有增強之熱效能及電效能之RF裝置,及一種用於提供具有增強之效能的RF裝置之晶圓級封裝方法。
蜂巢式裝置及無線裝置之廣泛利用驅動射頻(RF)技術之快速發展。上面製作了RF裝置之基板在RF技術中達成高水準效能過程中起到重要作用。RF裝置在習知矽處置基板上製作可得益於矽材料之低成本、晶圓生產之大規模能力、完善之半導體設計工具及成熟之半導體製造技術。
儘管使用習知矽處置基板進行RF裝置製作有益處,但在業界眾所周知的係,習知矽處置基板可能具有對於RF裝置為兩個不合意之性質:諧波畸變及低電阻率值。諧波畸變為在建置於矽處置基板上之RF裝置中達成高水準線性度之嚴重阻礙。另外,高速及高效能之電晶體更密集地整合於RF裝置中。因此,藉由RF裝置產生之熱量將歸因於整合於RF裝置中之大量電晶體、傳遞通過該等電晶體之大量電力及/或該等電晶體之高操作速度而顯著地增加。因此,希望按某組態來封裝該等RF裝置以實現更好之熱耗散。
為了適應RF裝置的增加之熱產生及減少RF裝置之有害諧波畸變,因此,本揭示案之目標為提供一種用於實現增強之熱效能及電效能的改良之封裝方法。另外,亦需要在不增加封裝尺寸之情況下增強RF裝置之性能。
本揭示案係關於一種具有增強之熱效能及電效能之射頻(RF)裝置及一種用於製造該RF裝置之方法。所揭示之RF裝置包括一裝置區、若干第一凸塊結構、一第一模塑料及一第二模塑料。該裝置區包括具有若干連接層之一後段產線(BEOL)部分及駐留於該BEOL部分上方之一前段產線(FEOL)部分。該FEOL部分包括一活化層、一接觸層及多個隔離區段。本文中,該活化層與該等隔離區段兩者皆駐留於該接觸層上方。該活化層被該等隔離層環繞且未垂直地延伸超過該等隔離區段。該等第一凸塊結構形成於該BEOL部分之一底部表面處,且經由該BEOL部分內之該等連接層電耦合至該FEOL部分。該第一模塑料形成於該BEOL部分之該底部表面上方且部分地囊封每個第一凸塊結構,使得每個第一凸塊結構之一底部部分未被該第一模塑料遮蓋。該第二模塑料駐留於該FEOL部分之該活化層上方,其間無一矽材料,該矽材料具有5歐姆-cm與30000歐姆-cm之間的一電阻率。
在該RF裝置之一個實施例中,該第二模塑料之一部分駐留於該等隔離區段上方。
在該RF裝置之一個實施例中,該等隔離區段垂直地延伸超過該活化層之一頂部表面以在該等隔離區段內且在該活化層上方界定一開口,其中該第二模塑料填充該開口。
根據另一個實施例,該RF裝置進一步包括直接在該活化層之該頂部表面上方且在該開口內之一鈍化層。本文中,該鈍化層由二氧化矽、氮化矽或該兩者之組合形成,且與該第二模塑料接觸。
根據另一個實施例,該RF裝置進一步包括直接在該活化層之該頂部表面上方且在該開口內之一界面層。本文中,該界面層由矽鍺(SiGe)形成且直接連接至該第二塑封。
在該RF裝置之一個實施例中,該第二模塑料與該活化層之該頂部表面接觸。
在該RF裝置之一個實施例中,每個隔離區段之一頂部表面與該活化層之一頂部表面為共面的。本文中,該第二模塑料駐留於該活化層與該等隔離區段兩者上方。
根據另一個實施例,該RF裝置進一步包括若干第二凸塊結構。每個第二凸塊結構與一對應之第一凸塊結構接觸,且自該第一模塑料突出。
在該RF裝置之一個實施例中,該等第二凸塊結構由焊錫膏、導電環氧樹脂或可回流焊金屬形成。
在該RF裝置之一個實施例中,該等第一凸塊結構為焊球或銅柱。
在該RF裝置之一個實施例中,該第一模塑料由與該第二模塑料相同之一材料形成。本文中,該第一模塑料及該第二模塑料具有大於1 W/m·K之一導熱率,及小於8之一介電常數及在3與5之間的一介電常數。
在該RF裝置之一個實施例中,該第一模塑料及該第二模塑料由不同材料形成。
在該RF裝置之一個實施例中,該第一模塑料為透明的。
在該RF裝置之一個實施例中,該FEOL部分經組態以提供一開關場效電晶體(FET)、一二極體、一電容器、一電阻器及一電感器中之至少一者。
根據一種例示性方法,首先提供具有若干裝置晶粒之一裝置晶圓。本文中,每個裝置晶粒包括第一凸塊結構及一裝置區,該裝置區具有一BEOL部分及在該BEOL部分上方之一FEOL部分。該FEOL部分包括一活化層、一接觸層及多個隔離區段。本文中,該活化層及該等隔離區段駐留於該接觸層上方,該等隔離區段環繞該活化層,且該活化層未垂直地延伸超過該等隔離區段。每個BEOL部分之一底部表面之一組合形成該裝置晶圓之一底部表面。該等第一凸塊結構形成於每個BEOL部分之該底部表面處。另外,由SiGe形成之一界面層直接在每個裝置晶粒之該活化層上方。一矽處置基板直接在每個界面層上方。接下來,將一第一模塑料施加於該裝置晶圓之該底部表面上方以囊封每個裝置晶粒之該等第一凸塊結構。隨後完全移除該矽處置基板。在每個裝置晶粒之該活化層上方形成一第二模塑料,該矽處置基板係自該活化層移除。無矽材料駐留於該第二模塑料與每個活化層之間。在形成該第二模塑料之後,使該第一模塑料薄化,直至暴露每個第一凸塊結構之一底部部分為止。
根據另一個實施例,該例示性方法進一步包括在施加該第二模塑料之前移除該界面層。本文中,在施加了該第二模塑料之後,每個裝置晶粒之該活化層與該第二模塑料接觸。
根據另一個實施例,該例示性方法進一步包括在施加該第二模塑料之前移除該界面層且直接在每個裝置晶粒之該活化層上方施加一鈍化層。本文中,該鈍化層由二氧化矽、氮化矽或該兩者之組合形成。在施加該第二模塑料之後,該鈍化層與該第二模塑料接觸。
根據另一個實施例,該例示性方法進一步包括在使該第一模塑料薄化之後形成若干第二凸塊結構。本文中,每個第二凸塊結構與一對應之第一凸塊結構之一暴露之底部部分接觸,且自該第一模塑料突出。
根據另一個實施例,該例示性方法進一步包括在施加該第一模塑料之前在該裝置晶圓之該底部表面的周界處形成至少一個窗組件。本文中,在施加該第一模塑料之後,該至少一個窗組件由該第一模塑料囊封。
在該例示性方法之一個實施例中,該至少一個窗組件比每個第一凸塊結構高,使得在該薄化製程期間,該至少一個窗組件在該等第一凸塊結構之前暴露。
在該例示性方法之一個實施例中,提供該裝置晶圓以提供一Si-SiGe-Si晶圓開始,該Si-SiGe-Si晶圓包括一共同矽磊晶層、在該共同矽磊晶層上方之一共同界面層及在該共同界面層上方之該矽處置基板。該共同界面層由SiGe形成。隨後執行一互補金屬氧化物半導體(CMOS)製程以提供包括若干裝置區之一前體晶圓。本文中,該等隔離區段延伸穿過該共同矽磊晶層及該共同界面層,且延伸至該矽處置基板中,使得該共同界面層分離為若干單獨之界面層,且該共同矽磊晶層分離為若干單獨之矽磊晶層。該等裝置區之每個活化層由一對應之單獨矽磊晶層形成。每個單獨界面層直接駐留於一對應活化層之一頂部表面上方,且該矽處置基板直接駐留於該等單獨界面層上方。接下來,在每個BEOL部分之該底部表面處形成該等第一凸塊結構以自該等裝置區完成該等裝置晶粒。
在該例示性方法之一個實施例中,提供該裝置晶圓以提供一Si-SiGe-Si晶圓開始,該Si-SiGe-Si晶圓包括一共同矽磊晶層、在該共同矽磊晶層上方之一共同界面層及在該共同界面層上方之該矽處置基板。該共同界面層包括SiGe,且具有相連接之若干界面層。隨後執行一CMOS製程以提供包括若干裝置區之一前體晶圓。本文中,該等隔離區段延伸穿過該共同矽磊晶層且延伸至該共同界面層中,使得該共同矽磊晶層分離為若干單獨之矽磊晶層,且該等界面層保持連接。該等裝置區之每個活化層由一對應之單獨矽磊晶層形成。每個界面層直接駐留於一對應活化層之一頂部表面上方,且該矽處置基板仍直接在該共同界面層上方。接下來,在每個BEOL部分之該底部表面處形成該等第一凸塊結構以自該等裝置區完成該等裝置晶粒。
熟習此項技術者在結合附圖閱讀了較佳實施例之以下詳細描述之後將瞭解本揭示案之範疇且認識到其額外態樣。
相關申請案
本申請案主張2018年7月2日提交之序列號為62/692,945之臨時專利申請案之利益,該申請案之揭示內容藉此以引用方式整體併入本文中。
本申請案係關於標題為「RF DEVICES WITH ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME」的同時提交之美國專利申請案第________號,該申請案之揭示內容藉此以引用方式整體併入本文中。
以下陳述之實施例表示用於使熟習此項技術者能夠實踐該等實施例之必需資訊且圖解說明了實踐該等實施例之最好模式。在依據附圖閱讀了以下描述之後,熟習此項技術者將理解本揭示案之概念且將認識到本文中未特別說明之此等概念的應用。將理解,此等概念及應用屬於本揭示案及所附申請專利範圍之範疇內。
將理解,雖然在本文中可使用術語第一、第二等來描述各種元件,但此等元件將不受此等術語限制。此等術語僅用於將一個元件與另一個元件區分開。舉例而言,在不脫離本揭示案之範疇的情況下,第一元件可被稱作第二元件,且類似地,第二元件可被稱作第一元件。如本文中使用,術語「及/或」包括相關聯之所列項中之一或多者的任何及所有組合。
應理解,當一個元件(諸如層、區或基板)被稱為「在另一個元件上」或「延伸至另一個元件上」時,該元件可直接在該另一個元件上或直接延伸至該另一個元件上,或亦可存在介入元件。相反地,當一個元件被稱為「直接在另一個元件上」或「直接延伸至另一個元件上」時,不存在介入元件。同樣地,將理解,當一個元件(諸如層、區或基板)被稱為「在另一個元件上方」或延伸「越過」另一個元件時,該元件可直接在該另一個元件上方或直接延伸越過該另一個元件,或亦可存在介入元件。相反地,當一個元件被稱為「直接在另一個元件上方」或「直接延伸越過另一個元件上」時,不存在介入元件。亦將理解,當一個元件被稱作「連接」或「耦合」至另一個元件時,該元件可直接地連接或耦合至該另一個元件,或可存在介入元件。相反地,當一個元件被稱為「直接連接」或「直接耦合」至另一個元件時,不存在介入元件。
在本文中可使用相對術語(諸如「下面」或「上面」或者「上」或「下」或者「水平」或「垂直」)來描述如各圖中所圖解說明之一個元件、層或區與另一個元件、層或區的關係。將理解,除了各圖中繪示之取向之外,此等術語及上文討論之彼等術語亦意欲涵蓋裝置之不同取向。
本文中使用之術語僅用於描述特定實施例且不意欲限制本揭示案。如本文中所使用,除非上下文另外清楚地指示,否則單數形式「一」、「一個」、及「該」亦意欲包括複數形式。亦將理解,術語「包含」及/或「包括」在本文中使用時指明了所述特徵、整數、步驟、操作、元件及/或組件之存在,但不排除一或多個其他特徵、整數、步驟、操作、元件、組件及/或其群組之存在或添加。
除非另外界定,否則本文中使用之所有術語(包括科技術語)具有與熟習此項技術者通常理解之含義相同的含義。亦將理解,本文中使用之術語應被解釋為具有與其在本說明書之上下文及相關領域中之含義一致的含義,並且除非本文中明確地界定,否則將不會以理想化或過於正式之意義來解釋。
由於習知射頻絕緣體上矽(RFSOI)晶圓在未來幾年預計會極其短缺,正在設想出替代技術以使用矽晶圓、圈閉富集層成形及智慧切割SOI晶圓製程來解決對高電阻率之需要。此等替代技術中之一者基於使用矽鍺(SiGe)界面層來替代矽基板與矽磊晶層之間的隱埋氧化層(BOX),然而,與RFSOI技術中觀察到之情況類似,矽鍺界面層亦將會遭受由矽基板所致之有害畸變效應。本揭示案係基於無來自矽基板之有害畸變效應的此Si-SiGe-Si結構,本揭示案係關於一種具有增強之熱效能及電效能的射頻(RF)裝置及一種用於製造該射頻裝置之晶圓級封裝方法。
圖1展示根據本揭示案之一個實施例的由Si-SiGe-Si晶圓形成之例示性RF裝置10 (在以下段落中描述加工細節)。為了進行此說明,例示性RF裝置10包括裝置區12、第一凸塊結構14、第一模塑料16及第二模塑料18。
詳言之,裝置區12包括前段產線(FEOL)部分20及在FEOL部分20下面之後段產線(BEOL)部分22。在一個實施例中,FEOL部分20經組態以提供開關場效電晶體(FET),且包括活化層24及接觸層26。本文中,活化層24具有源極28、汲極30及在源極28與汲極30之間的通道32。源極28、汲極30及通道32由同一矽磊晶層形成。接觸層26形成於活化層24下面且包括閘極結構34、源極接點36、汲極接點38及閘極接點40。閘極結構34可由二氧化矽形成,且在通道32下面水平地延伸(自源極28下面延伸至汲極30下面)。源極接點36連接至源極28且在該源極下面,該汲極接點38連接至汲極30且在該汲極下面,且閘極接點40連接至閘極結構34且在閘極結構34下面。絕緣材料42可環繞源極接點36、汲極接點38、閘極結構34及閘極接點40形成以將源極28、汲極30及閘極結構34電分離。在不同應用中,FEOL部分20可具有不同之FET組態或提供不同之裝置組件,諸如二極體、電容器、電阻器及/或電感器。
另外,FEOL部分20亦包括隔離區段44,該等隔離區段駐留於接觸層26之絕緣材料42上方且環繞活化層24。隔離區段44經組態以將RF裝置10,尤其係活化層24,與形成於共同晶圓(未展示)中之其他裝置電分離。本文中,隔離區段44可自接觸層26之頂部表面延伸且垂直地延伸超過活化層24之頂部表面以界定開口46,該開口在隔離區段44內且在活化層24上方。第二模塑料18填充開口46且可延伸越過隔離區段44。隔離區段44可由二氧化矽形成,二氧化矽可耐受蝕刻化學物,諸如氫氧化鉀(KOH)、氫氧化鈉(NaOH)及乙醯膽鹼(ACH)。
在一些應用中,RF裝置10可進一步包括鈍化層48,該鈍化層由二氧化矽、氮化矽或該兩者之組合形成,直接在活化層24之頂部表面上方且在開口46內。因而,第二模塑料18直接在鈍化層48上方。鈍化層48經組態以終止活化層24之表面黏結,該等表面黏結可能會引致不想要之洩漏。該鈍化層亦可用作障壁且經組態以保護活化層24使之免於受潮或離子污染。若省去鈍化層48,則第二模塑料18可與活化層24之頂部表面接觸。在一些應用中,RF裝置10可進一步包括界面層(在以下段落中描述且本文中未展示),該界面層由SiGe形成,直接在活化層24之頂部表面上方且在開口46內。因而,第二模塑料18可直接在該界面層上方。該界面層係來自Si-SiGe-Si晶圓(在以下段落中描述加工細節),該Si-SiGe-Si晶圓用於製造RF裝置10。若省去界面層,則第二模塑料18可與活化層24之頂部表面接觸。請注意,不管有無鈍化層48或界面層,矽晶體(其不含鍺)均不會存在於第二模塑料18與活化層24之頂部表面之間。鈍化層48與界面層為矽合金。
另外,在一些應用中,每個隔離區段44之頂部表面與活化層24之頂部表面為共面的(未展示),且省去開口46。第二模塑料18駐留於FEOL部分20之活化層24與隔離區段44上方。請注意,活化層24絕不會在垂直方向上超過隔離區段44。
BEOL部分22在FEOL部分20下面且包括形成於介電層52內之多個連接層50。第一凸塊結構14形成於BEOL部分22之底部表面處,且經由BEOL部分22之連接層50電耦合至FEOL部分20 (在此圖解說明中為源極接點36及汲極接點38)。第一模塑料16形成於BEOL部分22下面且囊封每個第一凸塊結構14之側,使得每個第一凸塊結構14之底部部分未被第一模塑料16覆蓋。
本文中,第一凸塊結構14不自第一模塑料16之底部表面突出。在一些應用中,將希望在RF裝置10之底部表面處具有突出結構以促進且提高晶粒附接(至印刷電路板)操作之可靠性。因此,RF裝置10可進一步包括若干第二凸塊結構54。每個第二凸塊結構54與對應之第一凸塊結構14接觸,且自第一模塑料16之底部表面突出。第一凸塊結構14可為焊球或銅柱。第二凸塊結構54可由焊錫膏、導電環氧樹脂或可回流焊金屬形成。
在裝置區12中產生之熱可向上傳播至第二模塑料18 (其在活化層24上方)之底部部分,且隨後將向上傳遞通過裝置區12及第一凸塊結構14,該等第一凸塊結構將會耗散熱。此外,在裝置區12中產生之熱亦可直接傳播通過第一模塑料16以被傳導。因此,非常希望第一模塑料16與第二模塑料18具有高之導熱率。第一模塑料16及第二模塑料18可具有大於1 W/m·K或大於10 W/m·K之導熱率。另外,第一模塑料16及第二模塑料18可具有小於8或在3與5之間的低介電常數以得到低RF耦合。第一模塑料16可由與第二模塑料18相同或不同之材料形成。在一個實施例中,第一模塑料16與第二模塑料18可由熱塑性或熱固性聚合物材料形成,諸如PPS (聚苯硫醚)、摻有氮化硼鋁、碳奈米管或類金剛石熱添加劑之包覆模製環氧樹脂或類似者。另外,第一模塑料16可為透明的,且可具有在約25 µm與500 µm之間的厚度(基於第一凸塊結構14之尺寸)。第二模塑料18之厚度係基於RF裝置10之所需熱效能、裝置佈局、距第一凸塊結構14之距離以及封裝及組裝之具體情況。第二模塑料18可具有在200 µm與500 µm之間的厚度。
圖2至圖13提供圖解說明用於製造圖1中所示之例示性RF裝置10之步驟的例示性晶圓級封裝方法。雖然該等例示性步驟連續地圖解說明,但該等例示性步驟未必係次序相關的。一些步驟可按與所呈現之次序不同的次序來進行。另外,在本揭示案之範疇內的方法可包括比圖2至圖13中所圖解說明之步驟少或多之步驟。
最初,如圖2中所圖解說明,提供一Si-SiGe-Si晶圓56。該Si-SiGe-Si晶圓56包括共同矽磊晶層58、在該共同矽磊晶層58上方之共同界面層60及在該共同界面層60上方之矽處置基板62。本文中,共同界面層60將共同矽磊晶層58與矽處置基板62分開,該共同界面層由SiGe形成。
本文中,共同矽磊晶層58由裝置級矽材料形成,該裝置級矽材料具有用於形成電子裝置之所要矽磊晶特性。共同界面層60由具有Si與Ge之任何莫耳比的合金形成。Ge濃度愈高,矽處置基板62與共同界面層60之間的蝕刻選擇性愈好,但共同矽磊晶層58之磊晶生長亦變得愈困難。在一個實施例中,共同界面層60可具有大於15%或大於25%之Ge濃度。Ge濃度在整個共同界面層60中可為均一的。在一些應用中,Ge濃度可在垂直方向上為分級的(在1%與50%之間)以便得到用於共同矽磊晶層58之生長的必需應變釋放。矽處置基板62可由習知之低成本、低電阻率及高介電常數之矽組成。共同矽磊晶層58具有比矽處置基板62高之電阻率,且共同矽磊晶層58具有比矽處置基板62低之諧波產生。共同矽磊晶層58之厚度可在700 nm與2000 nm之間,共同界面層60之厚度可在100 nm與1000 nm之間,且矽處置基板62之厚度可在200 µm與500 µm之間。
接下來,如圖3A中所圖解說明,對Si-SiGe-Si晶圓56執行互補金屬氧化物半導體(CMOS)製程以提供具有若干裝置區12之前體晶圓64。為了進行此說明,每個裝置區12之FEOL部分20經組態以提供開關FET。在不同應用中,FEOL部分20可具有不同之FET組態或提供不同之裝置組件,諸如二極體、電容器、電阻器及/或電感器。
在此實施例中,每個裝置區12之隔離區段44延伸穿過共同矽磊晶層58及共同界面層60,且延伸至矽處置基板62中。因而,共同界面層60分離為若干單獨之界面層60I,且共同矽磊晶層58分離為若干單獨之矽磊晶層58I,其中每一者用於形成一個裝置區12中之對應活化層24。
活化層24之頂部表面與對應之界面層60I接觸。矽處置基板62駐留於每個單獨之界面層60I上方,且矽處置基板62之部分可駐留於隔離區段44上方。裝置區12之BEOL部分22形成於FEOL部分20下面,該BEOL部分至少包括多個連接層50及介電層52。某些連接層50之底部部分經由BEOL部分22之底部表面處的介電層52暴露。
在另一個實施例中,隔離區段44不延伸至矽處置基板62中。而是,如圖3B中所圖解說明,隔離區段44僅延伸穿過共同矽磊晶層58且延伸至共同界面層60中。本文中,共同界面層60仍為連續的,且單獨之界面層60I彼此連接。共同界面層60直接駐留於每個活化層24之頂部表面上方,且直接駐留於每個隔離區段44之頂部表面上方。矽處置基板62仍在共同界面層60上方。另外,隔離區段44可延伸穿過共同矽磊晶層58,但不延伸至共同界面層60中。每個隔離區段44之頂部表面與每個活化層24之頂部表面可為共面的(未展示)。共同界面層60在每個隔離區段44及每個活化層24上方,且矽處置基板62仍在共同界面層60上方。
如圖4中所繪示,隨後在每個BEOL部分22之底部表面處形成第一凸塊結構14以提供裝置晶圓66。每個BEOL部分22之底部表面的組合形成裝置晶圓66之底部表面。裝置晶圓66包括若干裝置晶粒68,該等裝置晶粒中之每一者進一步包括比作裝置區12之第一凸塊結構14。每個第一凸塊結構14與對應連接層50之暴露部分接觸。本文中,第一凸塊結構14經由BEOL部分22之連接層50電耦合至FEOL部分20 (在此圖解說明中為源極接點36及汲極接點38)。第一凸塊結構14可藉由焊球凸塊技術或銅柱封裝技術形成。每個第一凸塊結構14自BEOL部分22之底部突出了20 µm至350 µm。
接下來,如圖5中所圖解說明,可在一個BEOL部分22之底部表面處形成至少一個窗組件70,晶圓標記(未展示)位於該底部表面處。本文中,該晶圓標記指示晶圓之關鍵位置,該等關鍵位置將在以下之單粒化及/或組裝製程中用於對準。在一個實施例中,至少一個窗組件70位於裝置晶圓66之底部表面的周界處。該至少一個窗組件70可由透明材料(例如,透明矽酮材料)形成,使得透過該至少一個窗組件70將看到晶圓標記。另外,至少一個窗組件70可由容易移除之材料(例如:丙烯酸聚合物)形成,使得在容易地移除該至少一個窗組件70之後將看到晶圓標記(在以下討論中有更多細節)。至少一個窗組件70具有比每個第一凸塊結構14大之高度且未連接至任何第一凸塊結構14。請注意,至少一個窗組件70為任選的。在一些應用中,在一個BEOL部分22之底部表面處形成至少一個窗組件70可被省去。
如圖6中所圖解說明,將第一模塑料16施加於裝置晶圓66之底部表面上方且囊封每個第一凸塊結構14及至少一個窗組件70。可藉由各種程序來施加第一模塑料16,諸如壓縮模製、片狀模製、包覆模製、轉移模製、壩填充囊封或絲網印刷囊封。第一模塑料16可具有大於1 W/m·K或大於10 W/m·K之導熱率,且可具有小於8或在3與5之間的介電常數。第一模塑料16可具有25 µm與500 µm之間的厚度。第一模塑料16可耐受蝕刻化學物,諸如KOH、NaOH及ACH。在一些應用中,第一模塑料16可由透明材料形成。因而,無需在BEOL部分22之底部表面處形成至少一個窗組件70,因為透過第一模塑料16可看到晶圓之所有位置。隨後使用固化製程(未展示)來使第一模塑料16硬化。固化溫度在100℃與320℃之間,此取決於使用哪種材料作為第一模塑料16。
如圖7中所圖解說明,在形成第一模塑料16之後,選擇性地移除矽處置基板62以提供經蝕刻晶圓72,其中該選擇性蝕刻停止於每個界面層60I。若隔離區段44垂直地延伸超過界面層60I,則矽處置基板62之移除將在每個活化層24上方且在隔離區段44內提供開口46。移除矽處置基板62可藉由化學機械研磨及使用濕式/乾式蝕刻劑化學物之蝕刻製程來提供,該等蝕刻劑化學物可為TMAH、KOH、NaOH、ACH或XeF2;或藉由蝕刻製程自身提供。作為一實例,可將矽處置基板62研磨至較薄厚度以減少接下來之蝕刻時間。隨後執行蝕刻製程以完全移除剩餘之矽處置基板62。由於矽處置基板62及界面層60I具有不同之特性,因此其對相同之蝕刻技術可具有不同之反應(例如:同種蝕刻劑,不同之蝕刻速度)。因此,蝕刻系統能夠識別界面層60I之存在,且能夠指示何時停止蝕刻製程。
在移除製程期間,不移除隔離區段44,且因此保護每個FEOL部分20。第一模塑料16保護每個BEOL部分22之底部表面。本文中,在移除製程之後,每個隔離區段44之頂部表面及每個界面層60I之頂部表面暴露。若隔離區段44延伸至共同界面層60中(如圖3B中所圖解說明),或每個隔離區段44之頂部表面與每個活化層24之頂部表面為共面的(未展示),僅共同界面層60之頂部表面將暴露(未展示)。
歸因於SiGe材料之窄間隙性質,可能的情況係界面層60I (或共同界面層60)可能為傳導的。界面層60I可導致活化層24之源極28與汲極30之間的明顯洩漏。因此,在一些應用(諸如FET應用)中,如圖8中所圖解說明,希望亦移除界面層60I (或共同界面層60)。界面層60I可藉由用於移除矽處置基板62之相同蝕刻製程來移除,或可藉由另一種蝕刻製程(諸如HCI乾式蝕刻系統)來移除。若界面層60I足夠薄,則其可能會完全耗盡且可能不會導致FEOL部分20之源極28與汲極30之間的任何明顯洩漏。在該種情況中,界面層60I可保持完整。
在一些應用中,如圖9中所圖解說明,可直接在每個FEOL部分20之活化層24上方形成鈍化層48,該鈍化層可由二氧化矽、氮化矽或兩者之組合形成。若有一個開口46在每個活化層24上方且在隔離區段44內,則鈍化層48在開口46內。鈍化層48經組態以終止活化層24之頂部表面處的表面黏結,該等表面黏結可能會引致不想要之洩漏。鈍化層48可藉由CVD介電質成膜或鈍化電漿來形成。
如圖10中所圖解說明,隨後在經蝕刻晶圓72上方施加第二模塑料18。本文中,第二模塑料18填充每個開口46且與開口46內之鈍化層48接觸。另外,第二模塑料18之部分可延伸越過隔離區段44。若無鈍化層48形成於每個開口46中,則第二模塑料18與每個活化層24之頂部表面接觸(未展示)。若界面層60I保持在每個活化層24之頂部表面上方,則第二模塑料18與界面層60I接觸(未展示)。第二模塑料18始終駐留於每個活化層24上方。
可藉由各種程序來施加第二模塑料18,諸如壓縮模製、片狀模製、包覆模製、轉移模製、壩填充囊封及絲網印刷囊封。在第二模塑料18之模製製程期間,第一模塑料16向經蝕刻之晶圓72提供機械強度及剛性。接下來進行固化製程(未展示)以使第二模塑料18硬化。固化溫度在100℃與320℃之間,此取決於使用哪種材料作為第二模塑料18。在固化製程之後,可使第二模塑料18薄化及/或平坦化(未展示)。
接下來,如圖11中所圖解說明,使第一模塑料16薄化以提供模製裝置晶圓74。本文中,第一模塑料囊封每個第一凸塊結構14之側,且每個第一凸塊結構14之底部部分暴露。另外,由於至少一個窗組件70具有比每個第一凸塊結構14大之高度,因此至少一個窗組件70之底部部分亦經由第一模塑料16暴露。可藉由機械研磨製程來完成該薄化程序。在一個實施例中,至少一個窗組件70可由透明材料形成,使得透過至少一個窗組件70將看到指示晶圓之關鍵位置的晶圓標記。在另一個實施例中,至少一個窗組件70可由不透明材料形成,使得將不能透過至少一個窗組件70看到指示晶圓之關鍵位置的晶圓標記。需要移除至少一個窗組件70之額外步驟以暴露指示晶圓之關鍵位置的晶圓標記(未展示)。
另外,在一些應用中,如圖12中所圖解說明,在使第一模塑料16薄化之後,可形成第二凸塊結構54。每個第二凸塊結構54直接連接至對應之第一凸塊結構14,電耦合至對應之FEOL部分20,且自第一模塑料16之底部表面突出。最後,如圖13中所圖解說明,將模製裝置晶圓74單粒化成單獨之RF裝置10。可在某些隔離區段44處藉由探測及切割製程來提供單粒化步驟。可使用若干晶粒附接方法將該等單獨之RF裝置10組裝在PCB上。
熟習此項技術者將認識到對本揭示案之較佳實施例的改良及修改。所有此類改良及修改被認為屬於本文中揭示之概念及以下申請專利範圍之範疇內。
10:RF裝置
12:裝置區
14:第一凸塊結構
16:第一模塑料
18:第二模塑料
20:前段產線(FEOL)部分
22:後段產線(BEOL)部分
24:活化層
26:接觸層
28:源極
30:汲極
32:通道
34:閘極結構
36:源極接點
38:汲極接點
40:閘極接點
42:絕緣材料
44:隔離區段
46:開口
48:鈍化層
50:連接層
52:介電層
54:第二凸塊結構
56:Si-SiGe-Si晶圓
58:共同矽磊晶層
58I:單獨之矽磊晶層
60:共同界面層
60I:單獨之界面層
62:矽處置基板
64:前體晶圓
70:窗組件
72:經蝕刻晶圓
74:模製裝置晶圓
併入本說明書中且形成本說明書之一部分的附圖圖解說明本揭示案之若干態樣,且與該描述一起用於闡釋本揭示案之原理。
圖1展示根據本揭示案之一個實施例的具有增強之熱效能及電效能的例示性射頻(RF)裝置。
圖2至圖13提供圖解說明用於製造圖1中所示之例示性RF裝置之步驟的例示性晶圓級封裝方法。
將理解,為了清楚說明,圖1至圖13可能未按比例繪製。
10:RF裝置
12:裝置區
14:第一凸塊結構
16:第一模塑料
18:第二模塑料
20:前段產線(FEOL)部分
22:後段產線(BEOL)部分
24:活化層
26:接觸層
28:源極
30:汲極
32:通道
34:閘極結構
36:源極接點
38:汲極接點
40:閘極接點
42:絕緣材料
44:隔離區段
46:開口
48:鈍化層
50:連接層
52:介電層
54:第二凸塊結構
Claims (25)
- 一種設備,該設備包括: ● 一裝置區,該裝置區包括一後段產線(BEOL)部分及駐留於該BEOL部分上方之一前段產線(FEOL)部分,其中: ● 該BEOL部分包括複數個連接層; ● 該FEOL部分包括一活化層、一接觸層及多個隔離區段; ● 該活化層及該等隔離區段駐留於該接觸層上方,且該等隔離區段環繞該活化層; ● 該活化層未垂直地延伸超過該等隔離區段; ● 複數個第一凸塊結構,該複數個第一凸塊結構形成於該BEOL部分之一底部表面處,其中該複數個第一凸塊結構經由該複數個連接層電耦合至該FEOL部分; ● 一第一模塑料,該第一模塑料形成於該BEOL部分之該底部表面上方且部分地囊封該複數個第一凸塊結構中之每一者,其中該複數個第一凸塊結構中之每一者的一底部部分未被該第一模塑料遮蓋;及 ● 一第二模塑料,該第二模塑料駐留於該FEOL部分之該活化層上方,其間無一矽材料,該矽材料具有5歐姆-cm與30000歐姆-cm之間的一電阻率。
- 如申請專利範圍第1項之設備,其中該第二模塑料之一部分駐留於該等隔離區段上方。
- 如申請專利範圍第1項之設備,其中該等隔離區段垂直地延伸超過該活化層之一頂部表面以在該等隔離區段內且在該活化層上方界定一開口,其中該第二模塑料填充該開口。
- 如申請專利範圍第3項之設備,該設備進一步包括直接在該活化層之該頂部表面上方且在該開口內之一鈍化層,其中: ● 該鈍化層由二氧化矽、氮化矽或該兩者之組合形成;且 ● 該第二模塑料與該鈍化層接觸。
- 如申請專利範圍第3項之設備,該設備進一步包括直接在該活化層之該頂部表面上方且在該開口內之一界面層,其中: ● 該界面層由矽鍺(SiGe)形成;且 ● 該第二模塑料與該界面層接觸。
- 如申請專利範圍第3項之設備,其中該第二模塑料與該活化層之該頂部表面接觸。
- 如申請專利範圍第1項之設備,其中每個隔離區段之一頂部表面與該活化層之一頂部表面為共面的,其中該第二模塑料駐留於該活化層與該等隔離區段兩者上方。
- 如申請專利範圍第1項之設備,該設備進一步包括複數個第二凸塊結構,其中該複數個第二凸塊結構中之每一者與該複數個第一凸塊結構中之一對應者接觸,且自該第一模塑料突出。
- 如申請專利範圍第8項之設備,其中該複數個第二凸塊結構由焊錫膏、導電環氧樹脂或可回流焊金屬形成。
- 如申請專利範圍第1項之設備,其中該複數個第一凸塊結構為焊球或銅柱。
- 如申請專利範圍第1項之設備,其中該第一模塑料由與該第二模塑料相同之一材料形成。
- 如申請專利範圍第11項之設備,其中該第一模塑料及該第二模塑料具有大於1 W/m·K之一導熱率。
- 如申請專利範圍第11項之設備,其中該第一模塑料及該第二模塑料具有小於8之一介電常數。
- 如申請專利範圍第11項之設備,其中該第一模塑料及該第二模塑料具有3與5之間的一介電常數。
- 如申請專利範圍第1項之設備,其中該第一模塑料及該第二模塑料由不同材料形成。
- 如申請專利範圍第1項之設備,其中該第一模塑料為透明的。
- 如申請專利範圍第1項之設備,其中該FEOL部分經組態以提供一開關場效電晶體(FET)、一二極體、一電容器、一電阻器及一電感器中之至少一者。
- 一種方法,該方法包括: ● 提供具有複數個裝置晶粒之一裝置晶圓,其中: ● 該複數個裝置晶粒中之每一者包括複數個第一凸塊結構及一裝置區,該裝置區具有一後段產線(BEOL)部分及在該BEOL部分上方之一前段產線(FEOL)部分; ● 該FEOL部分包括一活化層、一接觸層及多個隔離區段,其中該活化層及該等隔離區段駐留於該接觸層上方,該等隔離區段環繞該活化層,且該活化層未垂直地延伸超過該等隔離區段; ● 該複數個第一凸塊結構形成於該BEOL部分之一底部表面處,其中每個BEOL部分之該底部表面之一組合形成該裝置晶圓之一底部表面; ● 由矽鍺(SiGe)形成之一界面層直接在該複數個裝置晶粒中之每一者的該活化層上方;且 ● 一矽處置基板直接在每個界面層上方; ● 將一第一模塑料施加於該裝置晶圓之該底部表面上方以囊封該複數個裝置晶粒中之每一者的該複數個第一凸塊結構; ● 完全移除該矽處置基板; ● 將一第二模塑料施加於該複數個裝置晶粒中之每一者的該活化層上方,該矽處置基板係自該活化層移除,其中無矽材料駐留於該第二模塑料與每個活化層之間;及 ● 使該第一模塑料薄化,直至暴露該複數個第一凸塊結構中之每一者的一底部部分為止。
- 如申請專利範圍第18項之方法,該方法進一步包括在施加該第二模塑料之前移除該界面層,其中在施加了該第二模塑料之後,該複數個裝置晶粒中之每一者的該活化層與該第二模塑料接觸。
- 如申請專利範圍第18項之方法,該方法進一步包括在施加該第二模塑料之前移除該界面層且直接在該複數個裝置晶粒中之每一者的該活化層上方施加一鈍化層,其中: ● 該鈍化層由二氧化矽、氮化矽或該兩者之組合形成;且 ● 在施加該第二模塑料之後,該鈍化層與該第二模塑料接觸。
- 如申請專利範圍第18項之方法,該方法進一步包括在使該第一模塑料薄化之後形成複數個第二凸塊結構,其中該複數個第二凸塊結構中之每一者與一對應之第一凸塊結構之該暴露之底部部分接觸,且自該第一模塑料突出。
- 如申請專利範圍第18項之方法,該方法進一步包括在施加該第一模塑料之前在該裝置晶圓之該底部表面的周界處形成至少一個窗組件,其中在施加該第一模塑料之後,該至少一個窗組件由該第一模塑料囊封。
- 如申請專利範圍第22項之方法,其中該至少一個窗組件比該複數個第一凸塊結構中之每一者高,使得在該薄化製程期間,該至少一個窗組件在該複數個第一凸塊結構之前暴露。
- 如申請專利範圍第18項之方法,其中提供該裝置晶圓包括: ● 提供一Si-SiGe-Si晶圓,該Si-SiGe-Si晶圓包括一共同矽磊晶層、在該共同矽磊晶層上方之一共同界面層及在該共同界面層上方之該矽處置基板,其中該共同界面層由SiGe形成; ● 執行一互補金屬氧化物半導體(CMOS)製程以提供包括複數個裝置區之一前體晶圓,其中: ● 該等隔離區段延伸穿過該共同矽磊晶層及該共同界面層,且延伸至該矽處置基板中,使得該共同界面層分離為複數個單獨之界面層,且該共同矽磊晶層分離為複數個單獨之矽磊晶層; ● 該複數個裝置區之每個活化層由一對應之單獨矽磊晶層形成;且 ● 該複數個單獨之界面層中之每一者直接駐留於一對應活化層之一頂部表面上方,且該矽處置基板直接駐留於該複數個單獨界面層上方;及 ● 在每個BEOL部分之該底部表面處形成該複數個第一凸塊結構以自該複數個裝置區完成該複數個裝置晶粒。
- 如申請專利範圍第18項之方法,其中提供該裝置晶圓包括: ● 提供一Si-SiGe-Si晶圓,該Si-SiGe-Si晶圓包括一共同矽磊晶層、在該共同矽磊晶層上方之一共同界面層及在該共同界面層上方之該矽處置基板,其中: ● 該共同界面層包括SiGe;且 ● 該共同界面層具有相連接之複數個界面層; ● 執行一CMOS製程以提供一前體晶圓,該前體晶圓包括複數個裝置區,其中: ● 該等隔離區段延伸穿過該共同矽磊晶層且延伸至該共同界面層中,使得該共同矽磊晶層分離為複數個單獨之矽磊晶層,且該複數個界面層保持連接; ● 該複數個裝置區之每個活化層由一對應之單獨矽磊晶層形成;且 ● 該複數個界面層中之每一者直接駐留於一對應活化層之一頂部表面上方,且該矽處置基板仍直接在該共同界面層上方;及 ● 在每個BEOL部分之該底部表面處形成該複數個第一凸塊結構以自該複數個裝置區完成該複數個裝置晶粒。
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US10964554B2 (en) | 2018-10-10 | 2021-03-30 | Qorvo Us, Inc. | Wafer-level fan-out package with enhanced performance |
US11069590B2 (en) | 2018-10-10 | 2021-07-20 | Qorvo Us, Inc. | Wafer-level fan-out package with enhanced performance |
US11646242B2 (en) | 2018-11-29 | 2023-05-09 | Qorvo Us, Inc. | Thermally enhanced semiconductor package with at least one heat extractor and process for making the same |
US20200235040A1 (en) | 2019-01-23 | 2020-07-23 | Qorvo Us, Inc. | Rf devices with enhanced performance and methods of forming the same |
US11387157B2 (en) | 2019-01-23 | 2022-07-12 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
US11923313B2 (en) | 2019-01-23 | 2024-03-05 | Qorvo Us, Inc. | RF device without silicon handle substrate for enhanced thermal and electrical performance and methods of forming the same |
US20200235066A1 (en) | 2019-01-23 | 2020-07-23 | Qorvo Us, Inc. | Rf devices with enhanced performance and methods of forming the same |
US11646289B2 (en) | 2019-12-02 | 2023-05-09 | Qorvo Us, Inc. | RF devices with enhanced performance and methods of forming the same |
US11923238B2 (en) | 2019-12-12 | 2024-03-05 | Qorvo Us, Inc. | Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive |
US20220285205A1 (en) * | 2021-03-05 | 2022-09-08 | Qorvo Us, Inc. | SELECTIVE ETCHING PROCESS FOR SiGe AND DOPED EPITAXIAL SILICON |
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US8525335B2 (en) * | 2009-07-03 | 2013-09-03 | Teramikros, Inc. | Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof |
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