JP5703105B2 - 半導体装置及びその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 118
- 238000004519 manufacturing process Methods 0.000 title claims description 45
- 239000010410 layer Substances 0.000 claims description 144
- 229910052751 metal Inorganic materials 0.000 claims description 136
- 239000002184 metal Substances 0.000 claims description 136
- 239000011229 interlayer Substances 0.000 claims description 65
- 239000000758 substrate Substances 0.000 claims description 24
- 238000009792 diffusion process Methods 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- 238000009751 slip forming Methods 0.000 claims 3
- 230000002265 prevention Effects 0.000 claims 1
- 238000000034 method Methods 0.000 description 21
- 229920002120 photoresistant polymer Polymers 0.000 description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 230000000052 comparative effect Effects 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 10
- 239000010949 copper Substances 0.000 description 10
- 239000012535 impurity Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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Description
(半導体装置の構成)
まず、図1を参照して、比較例に係る半導体装置の積層構造を説明する。その後、図2を参照して、第1の実施の形態に係る半導体装置の構造について説明する。
このような観点から、第1の実施の形態では以下に示す構成を採用する。以下、本実施の形態に係る半導体装置の構成を、図2を参照して説明する。
本実施の形態に係る半導体装置では、領域Bにおける金属層114を2つの配線層に亘る膜厚となるように形成している。図1に示す比較例では、金属層107と金属層117との間に層間絶縁膜110が存在していたが、図2に示す本実施の形態の半導体装置では、金属層114内には層間絶縁膜が含まれない。本実施の形態の半導体装置は、層間絶縁膜110が存在していた領域が金属層114となることにより配線の断面積が増加し、配線抵抗の低減を図ることができる。また、領域Bの金属層114による配線幅W3を領域Aの配線幅W1よりも大きくすることで、より配線の断面積が増加し、配線抵抗の低減を図ることができるようになると共に、配線の厚さが厚くなっても埋め込み性よく金属層を形成することが可能となる。
次に、第2の実施の形態の半導体装置を、図15を参照して説明する。本実施の形態の半導体装置の全体構成は、第1の実施の形態と同様であり、その詳細な説明は省略する。また、第2の実施の形態における半導体基板201、層間絶縁膜202、コンタクト203、層間絶縁膜205は、第1の実施の形態の半導体基板101、層間絶縁膜102、コンタクト103、層間絶縁膜105とそれぞれ対応しており、同様の構成を有する。
本実施の形態に係る半導体装置では、領域Bに形成される配線は、2つの配線層に亘る膜厚となる第1金属部207、第2金属部214により構成されている。図15に示す本実施の形態の半導体装置でも、第1金属部207、第2金属部214内には層間絶縁膜が含まれることがなく、配線の断面積が増加し、配線抵抗の低減を図ることができる。
次に、第2の実施の形態の半導体装置の製造方法の他の例を、図20〜図22を参照して説明する。図15に示す第2の実施の形態では、ストッパ膜208は、第1配線層上の全面に設けられていた。このストッパ膜208は、必ずしも全面に設ける必要はなく、金属層207の上に設けられていればよい。
以上、本発明のいくつかの実施の形態を説明したが、これらの実施の形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施の形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施の形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
Claims (7)
- 半導体基板と、
前記半導体基板上にそれぞれ設けられた第1の領域及び第2の領域とを備え、
前記第1の領域は、
前記半導体基板上の第1配線層に形成され、所定の第1の幅を有する第1の金属配線と、
前記第1配線層の上層の第2配線層に形成され前記第1の幅を有する第2の金属配線と、
前記第1の金属配線と第2の金属配線とを接続し、前記第1の幅以下の第2の幅を有する第1のコンタクトとを有し、
前記第2の領域は、
前記第1配線層から前記第2配線層へと亘る膜厚を有し、所定の第3の幅を有する第3の金属配線を有し、
前記第3の金属配線は、金属膜及びバリアメタル膜を含み、
前記金属膜は、前記第1配線層の下側表面から前記第2配線層の上側表面に至る膜厚で形成され、
前記バリアメタル膜は、前記金属膜の側面表面から前記金属膜の下側表面まで連続的に形成されている
ことを特徴とする半導体装置。 - 前記第1の領域は、
前記半導体基板上の前記第1の領域に形成された第1の素子と、
前記第1の素子及び前記第1の金属配線に接続される第2のコンタクトを有し、
前記第2の領域は、
前記半導体基板上の前記第2の領域に形成された第2の素子と、
前記第2の素子及び前記第3の金属配線に接続される第3のコンタクトを有する
ことを特徴とする請求項1記載の半導体装置。 - 前記第3の幅は、前記第1の幅よりも大きいことを特徴とする請求項1又は2記載の半導体装置。
- 前記第3の金属配線は、前記第1配線層に形成された第1金属部と、前記第2配線層から前記第1配線層の上面へと亘る膜厚を有する第2金属部とにより構成される
ことを特徴とする請求項1乃至3のいずれか1項記載の半導体装置。 - 前記第1配線層上に形成され、前記第1の金属配線及び前記第1金属部に用いられる金属が層間絶縁膜中に拡散することを防止する機能を有する拡散防止膜を更に備え、
前記第1のコンタクト及び前記第2金属部は、それぞれ前記拡散防止膜を貫通して前記第1の金属配線及び前記第1金属部に接続されている
ことを特徴とする請求項4記載の半導体装置。 - 半導体基板上に設けられた第1の領域において、第1配線層に所定の第1の幅を有する第1の金属配線を形成する工程と、
前記第1の領域において、前記第1配線層の上層の第2配線層に形成され前記第1の幅を有し、第2の金属配線材料からなる第2の金属配線と、前記第1の金属配線及び前記第2の金属配線を接続し前記第1の幅以下の第2の幅を有する第1のコンタクトとを形成するとともに、前記半導体基板上に設けられた第2の領域において、前記第1配線層から前記第2配線層へと亘る膜厚を有し、前記第2の金属配線材料からなる第3の金属配線を形成する工程とを備え、
前記第3の金属配線は、前記第1配線層の下側表面から前記第2配線層の上側表面に至る膜厚で連続的に形成されるようにする
ことを特徴とする半導体装置の製造方法。 - 半導体基板上に設けられた第1の領域に形成された第1の素子に接続される第2のコンタクトを形成する工程と、
前記半導体基板上に設けられた第2の領域に形成された第2の素子に接続される第3のコンタクトを形成する工程と、
前記第1の領域において、前記半導体基板上の第1配線層に、前記第2のコンタクトに接続され且つ所定の第1の幅を有する第1の金属配線を形成する工程と、
前記第1の領域において、前記第1配線層の上層の第2配線層に形成され前記第1の幅を有し、第2の金属配線材料からなる第2の金属配線と、前記第1の金属配線及び前記第2の金属配線を接続し前記第1の幅以下の第2の幅を有する第1のコンタクトとを形成するとともに、前記第2の領域において、前記第3のコンタクトに接続され前記第1配線層から前記第2配線層へと亘る膜厚を有し、第2の金属配線材料からなる第3の金属配線を形成する工程とを備え、
前記第3の金属配線は、前記第1配線層の下側表面から前記第2配線層の上側表面に至る膜厚で連続的に形成されるようにする
ことを特徴とする半導体装置の製造方法。
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US10002826B2 (en) * | 2014-10-27 | 2018-06-19 | Taiwan Semiconductor Manufacturing Company | Semiconductor device structure with conductive pillar and conductive line and method for forming the same |
JP2016174021A (ja) * | 2015-03-16 | 2016-09-29 | 株式会社東芝 | 半導体装置 |
US10672708B2 (en) | 2015-11-30 | 2020-06-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Standard-cell layout structure with horn power and smart metal cut |
US9837353B2 (en) | 2016-03-01 | 2017-12-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Middle end-of-line strap for standard cell |
TWI597847B (zh) * | 2016-09-05 | 2017-09-01 | 新唐科技股份有限公司 | 高壓半導體裝置 |
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CN1171304C (zh) | 1995-11-20 | 2004-10-13 | 株式会社日立制作所 | 半导体存储器及其制造方法 |
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2011
- 2011-04-15 JP JP2011090988A patent/JP5703105B2/ja active Active
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