CN112420654A - 半导体管芯、其制造方法、及半导体封装 - Google Patents
半导体管芯、其制造方法、及半导体封装 Download PDFInfo
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- CN112420654A CN112420654A CN201911394423.5A CN201911394423A CN112420654A CN 112420654 A CN112420654 A CN 112420654A CN 201911394423 A CN201911394423 A CN 201911394423A CN 112420654 A CN112420654 A CN 112420654A
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- passivation layer
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Abstract
提供一种半导体管芯。所述半导体管芯包括半导体衬底、内连结构、多个导电接垫、第一钝化层及第二钝化层。内连结构设置在半导体衬底上。导电接垫设置在内连结构之上且电连接到内连结构。第一钝化层及第二钝化层依序堆叠在导电接垫上。第一钝化层及第二钝化层填充所述导电接垫中的两个相邻的导电接垫之间的间隙。第一钝化层包括第一区段及第二区段。第一区段实质上平行于内连结构的顶表面延伸。第二区段面对导电接垫中的一者的侧表面。第一区段的厚度与第二区段的厚度不同。
Description
技术领域
本发明实施例涉及半导体管芯、其制造方法、及半导体封装。
背景技术
用于各种电子装置(例如手机及其他移动电子设备)中的半导体器件及集成电路通常是在单个半导体晶片上制造。可在晶片级上对晶片的管芯进行处理并与其他半导体器件或管芯封装在一起,且已经开发出用于晶片级封装的各种技术及应用。多个半导体器件的集成已成为此领域中的挑战。
发明内容
根据本公开的一些实施例,一种半导体管芯包括半导体衬底、内连结构、多个导电接垫、第一钝化层及第二钝化层。所述内连结构设置在所述半导体衬底上。所述导电接垫设置在所述内连结构之上且电连接到所述内连结构。所述第一钝化层及所述第二钝化层依序堆叠在所述导电接垫上。所述第一钝化层及所述第二钝化层填充所述导电接垫中的两个相邻的导电接垫之间的间隙。所述第一钝化层包括第一区段及第二区段。所述第一区段实质上平行于所述内连结构的顶表面延伸。所述第二区段面对所述导电接垫中的一者的侧表面。所述第一区段的厚度与所述第二区段的厚度不同。
附图说明
结合附图阅读以下详细说明,会最好地理解本公开的各个方面。应注意,根据本行业中的标准惯例,各种特征并非按比例绘制。事实上,为使论述清晰起见,可任意增大或减小各种特征的尺寸。
图1A到图1G是示出根据本公开一些实施例的半导体管芯的制造工艺的示意性剖视图。
图2是图1G中的半导体管芯的一区的示意性放大图。
图3A到图3E是示出根据本公开一些实施例的半导体封装的制造工艺的示意性剖视图。
图3F是示出根据本公开一些实施例的电子器件的示意性剖视图。
图4A到图4C是示出根据本公开一些替代实施例的半导体管芯的示意性剖视图。
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开。当然,这些仅为实例而非旨在进行限制。举例来说,以下说明中将第一特征形成在第二特征之上或第二特征上可包括其中第一特征与第二特征被形成为直接接触的实施例,且也可包括其中第一特征与第二特征之间可形成有附加特征从而使得所述第一特征与所述第二特征可不直接接触的实施例。另外,本公开可能在各种实例中重复使用参考编号和/或字母。这种重复使用是出于简明及清晰的目的,而不是自身指示所论述的各种实施例和/或配置之间的关系。
此外,为易于说明,本文中可能使用例如“在...之下”、“在...下方”、“下部的”、“在...上方”、“上部的”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括器件在使用或操作中的不同取向。装置可具有其他取向(旋转90度或处于其他取向),且本文中所使用的空间相对性描述语可同样相应地进行解释。
还可包括其他特征及工艺。举例来说,可包括测试结构以帮助对三维(three-dimensional,3D)封装或三维集成电路(three-dimensional integrated circuit,3DIC)器件进行验证测试。所述测试结构可包括例如在重布线层中或衬底上形成的测试接垫(test pad),以便能够对3D封装或3DIC进行测试、使用探针和/或探针卡(probe card)等。可对中间结构以及最终结构执行验证测试。另外,本文中所公开的结构及方法可与包含对已知良好管芯(known good die)进行中间验证的测试方法结合使用以提高良率并降低成本。
图1A到图1G是示出根据本公开一些实施例的半导体管芯100的制造工艺的示意性剖视图。参照图1A,提供半导体晶片W。在一些实施例中,半导体晶片W包括多个管芯单元DU。在一些实施例中,每一管芯单元DU对应于半导体晶片W的一部分。在图1A中,为简明起见,示出单个管芯单元DU。然而,本公开并非仅限于此。可将多个管芯单元DU在半导体晶片W中排列成阵列。
在一些实施例中,每一管芯单元DU包括半导体衬底110及形成在半导体衬底110上的内连结构120。在一些实施例中,半导体衬底110可由以下材料制成:元素半导体材料,例如晶体硅、金刚石或锗;化合物半导体材料,例如碳化硅、砷化镓、砷化铟或磷化铟;或者合金半导体材料,例如硅锗、碳化硅锗、磷化镓砷或磷化镓铟。在一些实施例中,半导体衬底110包括形成在半导体衬底110中的有源组件(例如,晶体管等)和/或无源组件(例如,电阻器、电容器、电感器等)。半导体衬底110还可包括穿透过半导体衬底110的多个半导体穿孔(through semiconductor via,TSV)112,以进行双面连接(dual-side connection)。然而,TSV 112是可选的且在一些替代实施例中可被省略。
如图1A中所示,在半导体衬底110上设置内连结构120。在一些实施例中,内连结构120包括介电间层(inter-dielectric layer)122及图案化导电层124。在一些实施例中,图案化导电层124嵌在介电间层122中。在一些实施例中,图案化导电层124与介电间层122交替堆叠。在一些实施例中,图案化导电层124的一部分可延伸穿过下伏介电间层122,以建立与下伏图案化导电层124的电连接。在一些实施例中,图案化导电层124也可建立与TSV 112的电连接。
在一些实施例中,介电间层122的材料包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(benzocyclobutene,BCB)、聚苯并恶唑(polybenzoxazole,PBO)、其组合或其他合适的介电材料。可通过合适的制作技术(例如旋转涂布(spin-on coating)、叠层(lamination)、化学气相沉积(chemical vapor deposition,CVD)等)形成介电间层122。在一些实施例中,图案化导电层124的材料包括铝、钛、铜、镍、钨和/或其合金。可通过例如电镀(electroplating)、沉积和/或光刻及蚀刻来形成图案化导电层124。在一些实施例中,通过顺序性CVD(sequential CVD)工艺与双镶嵌工艺(dual damascene process)形成内连结构120。应注意,图1A中所示的图案化导电层124及介电间层122的数目仅为例示,且本公开并非仅限于此。在一些替代实施例中,可依据布线要求对图案化导电层124的数目及第一介电间层122的数目进行调整。
在一些实施例中,在内连结构120之上形成保护层130。在一些实施例中,保护层130可全面覆盖内连结构120。保护层130还可包括开口O1,开口O1暴露出最顶部图案化导电层124的一些部分。在一些实施例中,保护层130的材料包括氧化物(例如氧化硅)、氮化物(例如氮化硅)等。在一些实施例中,保护层130可包含聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(BCB)、聚苯并恶唑(PBO)或任何其他合适的介电材料。举例来说,可通过合适的制作技术(例如旋转涂布、CVD等)形成保护层130。在一些实施例中,内连结构120夹置在保护层130与半导体衬底110之间。
在一些实施例中,在保护层130之上设置导电接垫140。在一些实施例中,导电接垫140填充保护层130的开口O1且到达最顶部图案化导电层124,以建立电连接。在一些实施例中,保护层130的一些部分设置在导电接垫140的一些部分与内连结构120之间,同时导电接垫140的一些部分穿透过保护层130以与最顶部图案化导电层124连接。在一些实施例中,导电接垫140用于建立与随后形成或提供的其他组件(未示出)或管芯(未示出)的电连接。在一些替代实施例中,导电接垫140可为测试接垫,以用于探测其中包括导电接垫140的管芯单元DU。
参照图1B,在导电接垫140及保护层130之上形成第一钝化层152。在一些实施例中,第一钝化层152共形地设置在导电接垫140及保护层130之上。在一些实施例中,第一钝化层152可覆盖导电接垫140及保护层130。在一些实施例中,第一钝化层152的厚度介于0.1微米到1微米之间的范围内。在一些实施例中,第一钝化层152的材料包括氧化物。在一些实施例中,第一钝化层152的材料包括氧化硅。在一些实施例中,通过除高密度等离子体化学气相沉积(high-density plasma chemical vapor deposition,HDP-CVD)以外的化学气相沉积形成第一钝化层152。在一些实施例中,在形成第一钝化层152期间使用300℃到450℃范围内的温度。
参照图1C,在第一钝化层152之上形成第二钝化层154,以覆盖第一钝化层152。在一些实施例中,第二钝化层154的厚度可介于0.1微米到2微米的范围内。在一些实施例中,第二钝化层154包括彼此连接的区段1541到1543。在一些实施例中,第二钝化层154的区段1541到1543可具有不同的厚度。举例来说,平行于内连结构120的顶表面120t延伸但不在导电接垫140之上延伸的钝化层154的区段1541可比面对导电接垫140的侧表面140s(覆盖导电接垫140的侧表面140s)的区段1542薄。此外,区段1541的厚度T1541及区段1542的厚度T1542可不同于在导电接垫140的顶表面140t之上延伸的区段1543的厚度T1543。在一些实施例中,区段1541到1543的厚度T1541到T1543被作为第二钝化层154的和第一钝化层152接触的表面与直接相对的表面之间的距离进行测量。在一些实施例中,覆盖侧表面140s的区段1542可相对于导电接垫140的侧表面140s倾斜。在一些实施例中,钝化层154的区段1542及区段1541可在两个相邻的导电接垫140之间界定凹陷区(concave region)CR。在一些实施例中,凹陷区CR可具有截锥体(truncated cone)或截棱锥体(truncated pyramid)的轮廓,所述截锥体或截棱锥体具有规则或不规则的底部(base)。也就是说,随着进一步远离钝化层130,凹陷区CR的宽度可增大(凹陷区CR变得越来越宽)。对于任何水平高度(距内连结构120的垂直距离),凹陷区CR的宽度可被认为是形成凹陷区CR的区段1542的外表面之间的水平距离。为便于例示,在图1C中示出凹陷区CR在两个不同水平高度处的两个宽度WCR1及WCR2。在一些实施例中,形成同一凹陷区CR的两个区段1542的延伸方向可朝内连结构120的顶表面120t聚集(converge)。在一些实施例中,第二钝化层154的材料可相同于第一钝化层152的材料。在一些实施例中,第一钝化层152及第二钝化层154可由氧化硅制成。在一些实施例中,可通过高密度等离子体化学气相沉积(HDP-CVD)形成第二钝化层154。在HDP-CVD工艺期间,新材料的沉积可与先前松散沉积的材料的蚀刻发生竞争。在一些实施例中,松散沉积的材料可能被在HDP-CVD工艺期间形成的反应离子或自由基(radical)溅射掉。在一些实施例中,如上所述,新材料的沉积与松散沉积的材料的蚀刻之间的竞争可使第二钝化层154的不同区段1541到1543具有不同的厚度。在一些实施例中,如图1C中所示,也可移除第一钝化层152的一些部分。举例来说,可移除第一钝化层152的一些部分,使得在形成第二钝化层154期间第一钝化层152的边缘可平滑。在一些实施例中,HDP-CVD工艺可在300℃到450℃范围内的温度下进行。
参照图1D,在第二钝化层154之上可形成第三钝化前驱体层156a。在一些实施例中,第三钝化前驱体层156a的材料可相同于第二钝化层154的材料。在一些实施例中,第三钝化前驱体层156a覆盖第二钝化层154。在一些实施例中,第三钝化前驱体层156a在导电接垫140之上延伸且填充凹陷区CR。在一些实施例中,由于存在第二钝化层154,在形成第三钝化前驱体层156a期间在凹陷区CR中不形成间隙(真空袋(vacuum sack))。也就是说,凹陷区CR完全被第三钝化前驱体层156a填充。在一些实施例中,第三钝化前驱体层156a的材料可不同于第一钝化层152的材料。在一些替代实施例中,第三钝化前驱体层156a的材料可相同于第一钝化层152的材料。在一些实施例中,第三钝化前驱体层156a的材料包括氧化硅。在一些实施例中,可通过CVD等形成第三钝化前驱体层156a。在一些实施例中,第三钝化前驱体层156a被形成为具有厚度T1。
参照图1D及图1E,从第三钝化前驱体层156a形成第三钝化层156。在一些实施例中,通过例如平坦化工艺将第三钝化前驱体层156a的厚度T1减小到第三钝化层156的厚度T2。在一些实施例中,平坦化工艺包括机械研磨工艺(mechanical grinding process)、化学机械抛光(chemical mechanical polishing,CMP)工艺等。在一些实施例中,第三钝化层156的厚度T2为第三钝化前驱体层156a的厚度T1的约一半。如以上工艺中所示,通过将高密度等离子体化学气相沉积工艺(例如,用于形成第二钝化层154的工艺)与除高密度等离子体化学气相沉积工艺以外的化学气相沉积工艺(例如,用于形成第一钝化层152及第三钝化层156的工艺)交替进行来形成堆叠的钝化层152、154、156。在一些实施例中,可包括比图1E中所示的钝化层多的钝化层或比图1E中所示的钝化层少的钝化层。在一些实施例中,利用HDP-CVD形成的钝化层与利用除HDP-CVD以外的其他沉积技术(例如,除HDP-CVD之外的其他CVD技术)形成的钝化层交替堆叠。
参照图1F,形成结合通孔160及结合层170。结合通孔160穿透过钝化层152、154及156,以建立与内连结构120的图案化导电层124的电连接。在一些实施例中,尽管在图1F中未示出,然而结合通孔160中的一些结合通孔160可设置在导电接垫140上。结合层170设置在第三钝化层156及结合通孔160上。在一些实施例中,结合层170包括介电结合层172及散布在介电结合层172中的结合接垫174。在一些实施例中,结合接垫174中的至少一些结合接垫174设置在结合通孔160之上且通过结合通孔160电连接到内连结构120。
制成结合通孔160及结合层170的方法不受特别限制。在一些实施例中,可通过双镶嵌工艺形成结合通孔160及结合接垫174。举例来说,可在第三钝化层156上形成介电结合层172,可通过移除介电结合层172的一些部分、钝化层152、154、156的一些部分及保护层130的一些部分来开制(未必按此处所述次序开制)沟槽及通孔孔洞(未示出),且可在沟槽及通孔孔洞中设置导电材料(未示出)以分别形成结合接垫174及结合通孔160。在一些实施例中,通过同时填充通孔孔洞及与通孔孔洞连接的上覆沟槽(未示出)来形成结合通孔160及结合接垫174。在一些替代实施例中,可在介电结合层172之前形成结合通孔160。在一些实施例中,结合接垫174的宽度可大于下伏结合通孔160的宽度。在一些实施例中,结合通孔160及结合接垫174包含相同的材料。用于结合通孔160及结合接垫174的材料为例如铝、钛、铜、镍、钨或其合金。
参照图1F及图1G,例如通过沿着排列在各别管芯单元DU之间的切分线C-C切穿半导体晶片W来执行单体化步骤,以将各别半导体管芯100分开。在一些实施例中,单体化工艺通常涉及使用旋转刀片(rotating blade)和/或激光束执行晶片划切工艺(wafer dicingprocess)。在单体化之后,可从半导体晶片W制成各别半导体管芯100。
如图1G中所示,半导体管芯100包括半导体衬底110、内连结构120、一个或多个导电接垫140、钝化层152、154、156及结合层170。在一些实施例中,在半导体衬底110内形成TSV 112。在内连结构120之上设置保护层130,且在保护层130之上设置导电接垫140。导电接垫140直接接触内连结构120,以建立电连接。结合层170设置在第三钝化层156之上且包括介电结合层172及结合接垫174。结合接垫174中的至少一些结合接垫174通过结合通孔160电连接到内连结构120或导电接垫140。从结合层170延伸到导电接垫140或内连结构120的结合通孔160穿透过钝化层152、154、156,且可能穿透过保护层130。在一些实施例中,结合层170的距第三钝化层156较远的表面170a可被称为半导体管芯100的有源表面AS1。如图1G中所示,结合接垫174的顶表面与介电结合层172的顶表面实质上位于同一水平高度处,以提供用于混合结合的适当的有源表面AS1。在一些实施例中,半导体衬底110的与内连结构120相对的表面110b可被称为半导体晶片W的背侧表面BS1。
第一钝化层152共形地设置在保护层130之上,以覆盖导电接垫140。由于第二钝化层154的形成,第一钝化层152的转角(corners)可变得平滑。第二钝化层154设置在第一钝化层152之上。第二钝化层154包括具有不同厚度的区段1541、1542、1543。区段1542及对这两个面对的区段1542进行接合的中间区段1541在两个导电接垫140之间形成凹陷区CR。在一些实施例中,区段1542中的每一者可相对于区段1541的延伸方向以角度α倾斜。也就是说,倾斜角度α可被认为是区段1541与接合到第一区段1541的区段1542中的一者之间的夹角。在一些实施例中,倾斜角度α可在区段1542的外表面与第一区段1541的外表面之间测量且可被称为夹角。在一些实施例中,区段1542的外表面(背对导电接垫140的表面)可为实质上直的(具有实质上恒定的斜率,直到区段1542到达在导电接垫140的顶表面140t上延伸的区段1543的水平高度为止)。在区段1542的外表面是实质上直的实施例中,倾斜角度α可沿着区段1542在任何地方测量。然而,本公开并非仅限于此。在一些替代实施例中,区段1542的外表面的斜率可变化,其中倾斜角度α是在与区段1541的接合处与区段1542的外表面的切线之间测量。在一些实施例中,区段1542的倾斜角度α可独立地介于100°到120°的范围内。此外,形成同一凹陷区CR的所述两个区段1542的倾斜角度α可相同,但本公开并非仅限于此。在一些替代实施例中,形成同一凹陷区CR的两个区段1542的倾斜角度α不同。在一些实施例中,每一凹陷区CR在远离内连结构120的同时变宽。也就是说,形成给定凹陷区CR的两个区段1542的外表面朝内连结构120聚集且朝结合层170发散。在一些实施例中,当进行HDP-CVD工艺以形成第二钝化层154时,第二钝化层154的形状、厚度及总体轮廓可由工艺参数确定。
第三钝化层156设置在第二钝化层154、内连结构120及导电接垫140之上。在一些实施例中,第三钝化层156填充凹陷区CR。在一些实施例中,凹陷区CR的轮廓有利于第三钝化层156的无间隙形成(gapless formation)。也就是说,由于在HDP-CVD工艺期间第二钝化层154所获得的轮廓,第三钝化层156的后续沉积可不具有缺陷。举例来说,相对于不包括第二钝化层154或者在一些实施例中第二钝化层154不利用HDP-CVD工艺形成的情形,可减少或消除在第三钝化层156中形成的多个真空间隙。即使当将两个相邻的导电接垫的相对的侧表面140s分开的距离D对位于保护层130上方的导电接垫140的高度H140的高宽比D/H140小于3时,也可实现令人满意的间隙填充能力。在一些实施例中,导电接垫140的高度H140被作为导电接垫140的顶表面140t与保护层130的顶表面之间的距离进行测量。在一些实施例中,两个相邻的导电接垫140可具有不同的高度。在这种情景中,将这两个所测量高度中的较大者作为高度H140来确定中间凹陷区CR的高宽比。在一些实施例中,对于低至0.65的高宽比D/H140,可实现良好的填充能力。换句话说,由于存在第二钝化层154,第三钝化层156的顶表面可为实质上平的表面。因此,结合层170可形成在平的表面上,从而消除结合层170中迹线/接垫断裂的可能性。这样一来,由于包括利用HDP-CVD工艺形成的第二钝化层154,半导体管芯100的可靠性提高且故障率降低,从而提高制造工艺的良率并降低整体生产成本。在一些实施例中,堆叠的钝化层152、154、156可被统称为复合钝化结构150。
图2是图1G中的半导体管芯100的区A的示意性放大图。应注意,在图2中,为易于参照,对相似的元件使用不同的参考编号(例如,导电接垫1401及1402),而未必表示所指部件之间存在区别。如图2中所示,导电接垫1401及1402可被第一钝化层152涂覆。第一钝化层152以实质上共形的方式设置在导电接垫1401及1402之上。第二钝化层154覆盖第一钝化层152。在相邻的导电接垫1401与1402之间形成有凹陷区CR。如图2中所示,在一些实施例中,第二钝化层154的区段1542A及1542B的斜率可改变。也就是说,区段1542A及1542B可具有弯曲的轮廓,而不是直的轮廓。因此,第二钝化层154的区段1542A及1542B与形成在第二钝化层154上的第三钝化层156之间的界面可为弯曲的。如图2中所示,区段1542A在导电接垫1401之上延伸,区段1542B在导电接垫1402之上延伸,且区段1542A与1542B可通过第二钝化层1542的区段1541连接。
第三钝化层156设置在第二钝化层154上。在一些实施例中,如图2中所示,第三钝化层156可包括多个部分1561、1562、1563。举例来说,第一部分1561沉积在第二钝化层154的区段1542A之上,第二部分1562沉积在第二钝化层154的区段1542B之上,且第三部分1563沉积在第二钝化层154的区段1541之上。部分1561及1562中的每一者可从对应的下伏区段1542A或1542B的表面生长。部分1561与部分1562可在界面IN1处交会(encounter)。部分1561与1562可交会以形成较浅的凹陷区CR’,较浅的凹陷区CR’可被一个或多个附加钝化层或其部分(例如,图2中的部分156’)填充。
在一些实施例中,第三部分1563可具有指向远离内连结构120的方向的实质上三角形形状,其中三角形的底部设置在区段1541上。在一些实施例中,第三部分1563具有与第一部分1561的界面IN2及与第二部分1562的界面IN3。在一些实施例中,所述三个界面IN1、IN2及IN3在同一点P处交会。在一些实施例中,部分1561、1562、1563的形状由第二钝化层154的轮廓及用于形成第三钝化层156的条件确定。应注意,图2中所示的配置仅为例示。在一些替代实施例中,界面IN1、IN2及IN3可能不可见。
图3A到图3E是示出根据本公开一些实施例的半导体封装10的制造工艺的示意性剖视图。参照图3A,提供半导体晶片W2。半导体晶片W2可包括形成在半导体晶片W2中的与半导体晶片W2的不同部分对应的一个或多个半导体管芯200。半导体晶片W2及半导体管芯200可分别相似于上述半导体晶片W及半导体管芯100,因此本文中不再对其予以赘述。在一些实施例中,每一半导体管芯200包括半导体衬底210、内连结构220、导电接垫240、钝化层250、结合通孔260及结合层270。结合层270包括介电结合层272及结合接垫274。在一些实施例中,钝化层250可为与半导体管芯100的复合钝化结构150相似的复合钝化结构。如图3A中所示,介电结合层272的顶表面及结合接垫274的顶表面可被统称为半导体管芯200的有源表面AS2。如图3A中所示,介电结合层272的顶表面与结合接垫274的顶表面实质上位于同一水平高度处,以提供用于混合结合的适当的有源表面AS2。
参照图3A,在半导体管芯200的有源表面AS2上提供半导体管芯(上部管芯)100。在一些实施例中,在单个半导体管芯200上设置多个半导体管芯100。设置在同一半导体管芯200上的半导体管芯100可为相同类型或执行相同的功能,但本公开并非仅限于此。在一些替代实施例中,设置在同一半导体管芯200上的半导体管芯100可彼此不同或执行不同的功能。
在一些实施例中,半导体管芯100可为能够执行存储功能的管芯。举例来说,半导体管芯100中的每一者可独立地为动态随机存取存储器(Dynamic Random Access Memory,DRAM)、电阻式随机存取存储器(Resistive Random Access Memory,RRAM)、静态随机存取存储器(Static Random Access Memory,SRAM)等。然而,本公开并非仅限于此。在一些替代实施例中,半导体管芯100中的一者或多者可独立地为中央处理器(Central ProcessUnit,CPU)管芯、图形处理单元(Graphic Process Unit,GPU)管芯、现场可编程门阵列(Field-Programmable Gate Array,FPGA)等。
如图3A中所示,将半导体管芯100结合到半导体管芯200。在一些实施例中,可通过混合结合工艺将半导体管芯100结合到半导体管芯200。在一些实施例中,混合结合工艺的温度介于约200℃到约300℃的范围内。在一些实施例中,可将半导体管芯100拾取并放置到半导体管芯200的有源表面AS2上,使得半导体管芯100电连接到半导体管芯200。在一些实施例中,半导体管芯100被放置成使得半导体管芯100的有源表面AS1接触半导体管芯200的有源表面AS2。此外,半导体管芯100的结合接垫174实质上对准且直接接触半导体管芯200的对应的结合接垫274。举例来说,介电结合层172直接接触介电结合层272,且结合接垫174直接接触结合接垫274。在一些实施例中,半导体管芯100仅覆盖结合接垫274中的一些结合接垫274。也就是说,即使在放置半导体管芯100之后,一些结合接垫274仍可保持被暴露出。在一些实施例中,为有利于半导体管芯100与半导体管芯200之间的混合结合,可执行对半导体管芯100及半导体晶片W2的结合表面(即,有源表面AS1及有源表面AS2)的表面准备。表面准备可包括例如表面清洁及活化。可对有源表面AS1、AS2执行表面清洁,以移除结合接垫174及274的结合表面以及介电结合层172及272的结合表面上的颗粒。在一些实施例中,可通过例如湿式清洁来清洁有源表面AS1、AS2。
在清洁有源表面AS1及AS2之后,可执行介电结合层172及272的结合表面的活化以形成高的结合强度。举例来说,可执行等离子体活化来处理介电结合层172及272的结合表面。当介电结合层172及272的经活化的结合表面彼此接触时,对介电结合层172及272进行预结合。在将半导体管芯100预结合到半导体管芯200上之后,执行混合结合步骤。混合结合步骤可包括用于介电结合的热处理及用于导体结合的热退火(thermal annealing)。在一些实施例中,执行用于介电结合的热处理以强化介电结合层172与介电结合层272之间的结合。在执行用于介电结合的热处理之后,执行用于导体结合的热退火,以有利于结合接垫174与274之间的结合。在一些实施例中,用于导体结合的热退火的工艺温度高于用于介电结合的热处理的工艺温度。在执行用于导体结合的热退火之后,将介电结合层172结合到介电结合层272,且将结合接垫174结合到下伏结合接垫274。这样一来,上部管芯(例如,半导体管芯100)便混合结合到半导体管芯200。
参照图3B,执行填充工艺以在半导体晶片W2之上形成前驱体包封体400a来包封半导体管芯100。在一些实施例中,前驱体包封体400a可被形成为填充位于半导体晶片W2之上的半导体管芯100之间的间隙。在一些实施例中,前驱体包封体400a可被形成为与半导体管芯100的背侧表面100b实质上齐平。也就是说,包封体的顶表面400t可与背侧表面100b处于实质上相同的水平高度处。然而,本公开并非仅限于此。在一些替代实施例中,前驱体包封体400a可覆盖半导体管芯100的背侧表面110b。在一些实施例中,前驱体包封体400a的材料包括无机材料,例如氧化硅、氮化硅等。在一些替代实施例中,前驱体包封体400a的材料包括模制化合物、聚合材料(例如聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、BCB、PBO、其组合或其他合适的聚合物系介电材料)。在一些实施例中,可通过合适的工艺(例如CVD、等离子体增强型化学气相沉积(plasma-enhanced chemical vapor deposition,PECVD)、原子层沉积(atomic layer deposition,ALD)等)形成前驱体包封体400a。
参照图3B及图3C,在一些实施例中,在前驱体包封体400a中在半导体管芯100旁边形成多个导通孔300。在一些实施例中,导通孔300被形成为环绕半导体管芯100且被贴合到未被半导体管芯100覆盖的结合接垫274。在一些实施例中,可在前驱体包封体400a中形成多个开口(未示出),以暴露出结合接垫274中的一些结合接垫274。随后,将导电材料填充到所述开口中。在一些实施例中,在将导电材料填充到所述开口中之后,可执行平坦化工艺以将前驱体包封体400a及导电材料平坦化,从而形成包封体400及导通孔300。在一些实施例中,包封体400的平坦化包括执行机械研磨工艺和/或化学机械抛光(CMP)工艺。如图3C中所示,导通孔300直接接触结合接垫274。在一些实施例中,导通孔300通过设置在上面形成有导通孔300的结合接垫274下方的结合通孔260电连接到内连结构220。在一些实施例中,在前驱体包封体400a及导电材料的平坦化工艺期间,半导体管芯100的半导体衬底110从原始厚度T3(在图3B中示出)薄化到最终厚度T4(在图3C中示出),直到暴露出TSV 112。在一些实施例中,通过对背侧表面BS1执行平坦化工艺来实现半导体衬底110的薄化。在一些实施例中,导通孔300的一些部分及TSV 112的一些部分也可在薄化或平坦化工艺期间被移除。在一些实施例中,在平坦化工艺及薄化工艺(如果执行的话)之后,半导体衬底110的底表面110b与包封体400的顶表面400t可实质上处于相同的水平高度处(实质上共面)。在一些实施例中,导通孔300、TSV 112、半导体衬底110及包封体400可实质上到达相同的水平高度。在一些实施例中,导通孔300及TSV 112可相对于半导体衬底110的底表面110b及包封体400的顶表面400t而略微突出。如图3C中所示,包封体400在横向上包封半导体管芯100及导通孔300。在一些实施例中,导通孔300穿透过包封体400。在一些实施例中,半导体管芯100的介电结合层172及半导体管芯200的介电结合层272直接接触包封体400。在一些实施例中,介电结合层172被包封体400环绕。随着包封体400的形成,便获得了重构晶片(reconstructed wafer)RW。在一些实施例中,重构晶片RW包括多个封装单元PU。换句话说,可在重构晶片级上执行工艺,以使多个封装单元PU以重构晶片RW的形式得到处理。在图3C中,为简明起见,示出单个封装单元PU。然而,本公开并非仅限于此。可将多个封装单元PU以阵列的形式排列在重构晶片RW中。
参照图3D,在半导体管芯100及导通孔300之上形成重布线结构500。在一些实施例中,重布线结构500设置在包封体400之上。在一些实施例中,重布线结构500包括介电层502及内连的重布线导电层504。重布线导电层504可包括多个重布线导电图案。为简明起见,在图式中将介电层502示出为一个单个介电层,且将重布线导电层504示出为嵌在介电层502中。然而,从制造工艺的角度来看,介电层502可包括多个介电层,且每一重布线导电层504可夹置在两个相邻的介电层之间。重布线导电层504的一些部分可在介电层502内在垂直方向上延伸,以建立与其他上覆或下伏重布线导电层504的电连接。在一些实施例中,重布线导电层504的材料包括铝、钛、铜、镍、钨、其组合或其他合适的导电材料。可通过例如电镀、沉积和/或光刻及蚀刻来形成重布线导电层504。在一些实施例中,介电层502的材料包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(BCB)、聚苯并恶唑(PBO)或任何其他合适的聚合物系介电材料。举例来说,可通过合适的制作技术(例如旋转涂布、化学气相沉积(CVD)、等离子体增强型化学气相沉积(PECVD)等)形成介电层502。应注意,图3D中所示的重布线导电层504的数目及介电层502的数目仅出于例示目的,且本公开并非仅限于此。在一些替代实施例中,重布线导电层504的数目及介电层502的数目可依据电路设计而变化。在一些实施例中,重布线导电层504实体接触TSV 112及导通孔300,以建立与半导体管芯100及200的电连接。
如图3D中所示,在重布线结构500上依序形成多个凸块下金属(under-bumpmetallurgy,UBM)图案506及多个导电端子600。在一些实施例中,可通过以下步骤形成UBM图案506。首先,在重布线结构500的最顶部介电层502中形成多个接触开口O2。接触开口O2至少暴露出最顶部重布线导电层504的一些部分。接着,在最顶部介电层502之上及在接触开口O2中形成晶种材料层(未示出)。晶种材料层延伸到接触开口O2中,以直接接触最顶部重布线导电层504的被暴露出的部分。在一些实施例中,晶种材料层包括钛/铜复合层且通过溅射工艺形成。接着,在晶种材料层上形成具有开口的掩模图案(未示出)。掩模图案的开口暴露出将随后形成的UBM图案506的预期位置。举例来说,掩模图案的开口可暴露出位于接触开口O2内部的晶种材料层及位于接触开口O2附近的晶种材料层。之后,执行镀覆工艺,以在被掩模图案的开口暴露出的晶种材料层上形成导电材料层。在一些实施例中,导电材料层的材料包括铝、钛、铜、镍、钨和/或其合金。接着通过剥除工艺(stripping process)及蚀刻工艺移除掩模图案及下伏晶种材料层。接着剩余的晶种材料层及导电材料层构成UBM图案506。在一些实施例中,UBM图案506通过重布线导电层504电连接到TSV 112及导通孔300。这样一来,UBM图案506可电连接到半导体管芯100及200。
在一些实施例中,导电端子600设置在UBM图案506上。在一些实施例中,导电端子600通过焊剂(solder flux)贴合到UBM图案506。在一些实施例中,导电端子600是例如焊料球、球栅阵列(ball grid array,BGA)球或受控塌陷芯片连接(controlled collapse chipconnection,C4)凸块。在一些实施例中,导电端子600包含具有低电阻率的导电材料(例如Sn、Pb、Ag、Cu、Ni、Bi或其合金)。
参照图3D及图3E,执行单体化工艺以形成多个半导体封装10。例如通过沿着排列在各别封装单元PU之间的切割道SC切穿重构晶片RW来执行单体化步骤以将各别半导体封装10分开。在一些实施例中,划切工艺或单体化工艺通常涉及使用旋转刀片或激光束进行划切。换句话说,划切工艺或单体化工艺是例如激光切分工艺、机械切分工艺或其他合适的工艺。
应注意,尽管半导体管芯100及200在图3A到图3E中被示出为混合结合,然而本公开并非仅限于此。在一些替代实施例中,半导体管芯100及200可通过不同的内连方案(例如,倒装芯片结合到重布线结构等)进行内连。在这些实施例中,可针对其他合适的结合结构来改变半导体管芯100中的结合层170及半导体管芯200中的结合层270的配置。
在一些实施例中,图3A到图3E中所示的步骤可被称为“晶片上芯片(chip onwafer,CoW)级封装”。如图3E中所示,半导体管芯100堆叠在半导体管芯200上。换句话说,多个半导体管芯100、200被集成到单个半导体封装10中。这样一来,半导体封装10可被称为“集成电路上系统(system on integrated circuit,SOIC)封装”。在一些实施例中,通过对图3A到图3E中所呈现的步骤进行修改,可将异质半导体组件或同质半导体组件以较低的成本有效地集成到单个半导体封装中。举例来说,可将已知良好管芯以低成本有效地与半导体晶片或另一半导体管芯集成在一起。此外,由于导电端子600分别通过TSV 112及导通孔300电连接到半导体管芯100及半导体管芯200,因此可修改为较短的电路径。也就是说,可有效地增强半导体封装10的信号传输性能。
图3F是示出根据本公开一些实施例的电子器件的示意性剖视图。参照图3F,在一些实施例中,半导体封装10可堆叠在电路衬底700上,以形成电子器件20。在一些实施例中,电路衬底700可为主机板(motherboard)、印刷电路板(printed circuit board)等。在一些实施例中,半导体封装10通过导电端子600连接到电路衬底700。
图4A到图4C是示出根据本公开一些替代实施例的半导体管芯101到103的示意性剖视图。参照图4A,图4A所示半导体管芯101可含有与图1G所示半导体管芯100的组件相似的组件,因此使用相同或相似的参考编号来指示类似的组件。半导体管芯101与半导体管芯100之间的区别在于,在半导体管芯101的测试期间,在导电接垫140中的至少一者上形成探测标记142。也就是说,在形成复合钝化结构150B之前,执行晶片测试操作(有时被称为晶片最终测试或电路探测),例如以识别已知良好管芯。测试过程使得在用于测试的导电接垫140之上形成探测标记142。探测标记142的高度H142可介于0.5微米与1微米之间的范围内。
在一些实施例中,形成在导电接垫140之上的第一钝化层152B及第二钝化层154B的轮廓可能会受到探测标记142的存在的影响。也就是说,第一钝化层152B及第二钝化层154B可呈现与探测标记142的位置对应的垂直突起。也就是说,第一钝化层152B及第二钝化层154B分别具有与探测标记142同形且位于探测标记142之上的峰。在一些实施例中,为确保结合层170的平面性,第三钝化层156B在第二钝化层154顶上对应于探测标记142具有至少厚度H156。厚度H156可被作为探测标记142顶上的第三钝化层156B的相对的外表面之间的距离进行测量。探测标记142的高度H142可为探测标记142相对于导电接垫140的顶表面140t的突出高度。厚度H156对高度H142的比率可介于1.5到6的范围内。在一些实施例中,当探测标记142顶上的第三钝化层156B的厚度H156等于或大于0.3微米时,可实现结合层170的令人满意的平面性,且实现与探测标记142的形成位置相邻的凹陷区CR中的良好间隙填充能力。
参照图4B,图4B所示半导体管芯102可含有与图1G所示半导体管芯100的组件相似的组件,因此使用相同或相似的参考编号指示类似的组件。半导体管芯102与半导体管芯100之间的区别在于,在半导体管芯102中的保护层130之上形成有保护层132。在一些实施例中,保护层132在导电接垫140之上延伸。也就是说,导电接垫140夹置在保护层132的一些部分与保护层130的一些部分之间。当保护层132在导电接垫140上方延伸时,保护层132包括暴露出每一导电接垫140的至少一部分的开口O3。也就是说,保护层132覆盖导电接垫140的侧表面140s且覆盖顶表面140t的一部分。在一些实施例中,形成在保护层132之上的第一钝化层152C及第二钝化层154C的轮廓可对应于开口O3而呈现出凹陷(depression)。也就是说,保护层132之上的第一钝化层152C的顶表面位于比开口O3之上的第一钝化层152C的顶表面高的水平高度处。在一些实施例中,开口O3的宽度WO3对保护层132的厚度T132的比率等于或大于20。举例来说,开口O3的宽度WO3可大于30微米,而保护层132的厚度T132可介于0.7微米与1.5微米之间的范围内。当比率WO3/T132处于所述范围内时,可为随后形成的钝化层152C、154C、156C确保最佳间隙填充能力。在一些实施例中,堆叠的钝化层152C、154C、156C可被统称为复合钝化结构150C。厚度T132被视为导电接垫140顶上的第二保护层132的相对的表面之间(在垂直方向上)的距离。宽度WO3被视为导电接垫140顶上的保护层132的两个面对的表面之间(在水平方向上)的距离。在一些实施例中,开口O3上方的第三钝化层156C的厚度H156C对导电接垫顶上的保护层132的厚度T132的比率介于0.2到4.3的范围内,以确保结合层170的平面性。举例来说,厚度H156C可介于0.3微米与3微米之间的范围内,而厚度T132可介于0.7微米与1.5微米之间的范围内。在一些实施例中,厚度H156C被作为在给定开口O3上方延伸的第三钝化层156C的相对的表面之间的距离进行测量。
在一些实施例中,可利用与针对保护层130阐述的材料及工艺相似的材料及工艺形成保护层132。在一些实施例中,保护层130及保护层132二者均可呈多层式结构,其中由不同材料形成的层堆叠在彼此顶上。举例来说,保护层130及保护层132均可包括由第一材料及第二材料形成的堆叠的层(未示出)。在这些实施例中,保护层130及保护层132的接触层可由相同的材料制成。举例来说,如果保护层130及保护层132中的每一者均包括一个由第一材料形成的层及一个由第二材料形成的层,则可按第一材料-第二材料-第二材料-第一材料的顺序使由第二材料形成的这两个层彼此相邻地设置。举例来说,如果第一材料是氧化硅且第二材料是氮化硅,则保护层130可包括直接设置在内连结构120顶上的一个第一氧化硅层以及设置在第一氧化硅层顶上的一个第一氮化硅层。另一方面,保护层132将包括设置在第一氮化硅层上的一个第二氮化硅层以及设置在第二氮化硅层上的一个第二氧化硅层。
参照图4C,图4C所示半导体管芯103可含有与图1G所示半导体管芯100的组件相似的组件,因此使用相同或相似的参考编号指示类似的组件。半导体管芯103与半导体管芯100之间的区别在于,第一钝化层152D包括第一子层152D1及第二子层152D2,且第二钝化层154D包括第一子层154D1及第二子层154D2。在一些实施例中,子层交替堆叠。举例来说,第一子层152D1、第一子层154D1、第二子层152D1及第二子层152D2依序彼此堆叠。在一些实施例中,半导体管芯103具有与钝化层154D1及154D2(其通过HDP-CVD形成)交替堆叠的钝化层152D1及152D2(其通过例如CVD形成)。在一些实施例中,附加钝化层的存在可增强制作工艺的间隙填充能力、减少缺陷的发生并提高总体良率。在一些实施例中,堆叠的钝化层152D、154D、156D可被统称为复合钝化结构150D。在一些实施例中,半导体管芯103还包括将导电接垫140电连接到结合接垫174中的一些结合接垫174的附加结合通孔162。也就是说,在一些实施例中,导电接垫104用于增强半导体管芯103的电连接。
根据本公开的一些实施例,一种半导体管芯包括半导体衬底、内连结构、多个导电接垫、第一钝化层及第二钝化层。所述内连结构设置在所述半导体衬底上。所述导电接垫设置在所述内连结构之上且电连接到所述内连结构。所述第一钝化层及所述第二钝化层依序堆叠在所述导电接垫上。所述第一钝化层及所述第二钝化层填充所述导电接垫中的两个相邻的导电接垫之间的间隙。所述第一钝化层包括第一区段及第二区段。所述第一区段实质上平行于所述内连结构的顶表面延伸。所述第二区段面对所述导电接垫中的一者的侧表面。所述第一区段的厚度与所述第二区段的厚度不同。
在一些实施例中,还包括设置在所述内连结构与所述第一钝化层之间以及所述导电接垫的一些部分与所述第一钝化层之间的保护层,其中所述保护层具有开口,所述开口局部地暴露出所述导电接垫的所述顶表面。
在一些实施例中,在所述保护层之上的所述第一钝化层的顶表面位于比在所述开口之上的所述第一钝化层的所述顶表面高的水平高度处。
在一些实施例中,位于所述开口中的一者上方的所述第二钝化层的厚度对所述保护层的厚度的比率介于0.2与4.3之间的范围内。
在一些实施例中,所述第一钝化层与所述第二钝化层由相同的材料制成。
在一些实施例中,所述第一区段比所述第二区段薄。
在一些实施例中,所述导电接垫中的两个相邻的导电接垫之间的距离对所述导电接垫的高度的比率小于3。
根据本公开的一些实施例,一种半导体封装包括第一半导体管芯及第二半导体管芯。所述第一半导体管芯包括半导体衬底、内连结构、多个导电接垫及复合钝化结构。所述内连结构设置在所述半导体衬底上。所述导电接垫在所述内连结构上设置在彼此旁边。所述复合钝化结构覆盖所述导电接垫。所述复合钝化结构包括第一钝化层、第二钝化层及第三钝化层。所述第一钝化层共形地设置在所述导电接垫之上。所述第二钝化层设置在所述第一钝化层上。所述第二钝化层具有第一区段及连接到所述第一区段的多个第二区段。所述第一区段及所述第二区段位于所述导电接垫中的两个相邻的导电接垫之间。所述第一区段的延伸方向实质上平行于所述内连结构的顶表面。所述第二区段的延伸方向朝所述内连结构的所述顶表面聚集。所述第三钝化层覆盖所述第二钝化层。所述第二半导体管芯设置在所述第一半导体管芯上且电连接到所述第一半导体管芯。
在一些实施例中,所述导电接垫中的至少一者具有从所述导电接垫中的所述至少一者的顶表面突出的探测标记,且所述第一钝化层及所述第二钝化层分别具有与所述探测标记同形且位于所述探测标记之上的峰。
在一些实施例中,位于所述探测标记之上的所述第三钝化层的厚度对所述探测标记的突出高度的比率介于1.5与6之间的范围内。
在一些实施例中,所述第一区段与所述第二区段中的一者之间的夹角介于100°与120°之间的范围内。
在一些实施例中,所述第三钝化层包括设置在所述第二钝化层的所述第一区段之上的第一部分及分别设置在所述第二钝化层的对应的所述第二区段之上的多个第二部分,且所述第三钝化层的所述第一部分具有指向远离所述内连结构的方向的三角形形状。
在一些实施例中,所述第二区段中的一者的背对所述导电接垫的外表面是实质上直的。
在一些实施例中,所述第一半导体管芯具有包括第一结合接垫的第一结合层,所述第二半导体管芯具有包括第二结合接垫的第二结合层,所述第一结合层结合到所述第二结合层,且所述第一结合接垫对准对应的所述第二结合接垫。
根据本公开的一些实施例,一种半导体管芯的制造方法包括至少以下步骤。提供半导体晶片。所述半导体晶片具有内连结构及导电接垫。在所述半导体晶片上形成复合钝化结构,以填充所述导电接垫中的两个相邻的导电接垫之间的间隙。所述复合钝化结构是通过将高密度等离子体化学气相沉积工艺与化学气相沉积工艺交替进行来形成的。在所述复合钝化结构之上形成结合层。
在一些实施例中,形成所述复合钝化结构包括:执行第一化学气相沉积工艺,以在所述半导体晶片上形成第一钝化层;执行高密度等离子体化学气相沉积工艺,以在所述第一钝化层上形成第二钝化层;以及执行第二化学气相沉积工艺,以在所述第二钝化层上形成第三钝化层。
在一些实施例中,在所述高密度等离子体化学气相沉积工艺期间,所述第一钝化层的至少一部分被移除。
在一些实施例中,在所述高密度等离子体化学气相沉积工艺期间,所述第二钝化层的至少一部分被移除。
在一些实施例中,还包括:形成延伸穿过所述复合钝化结构的结合通孔,以对所述内连结构与所述结合层进行电连接。
在一些实施例中,还包括:在形成所述复合钝化结构之前,在所述内连结构及所述导电接垫之上形成保护层。
以上概述了若干实施例的特征,以使所属领域中的技术人员可更好地理解本公开的各个方面。所属领域中的技术人员应理解,他们可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到,这种等效构造并不背离本公开的精神及范围,而且他们可在不背离本公开的精神及范围的条件下在本文中作出各种改变、代替及变更。
Claims (1)
1.一种半导体管芯,包括:
半导体衬底;
内连结构,设置在所述半导体衬底上;
多个导电接垫,设置在所述内连结构之上且电连接到所述内连结构;以及
第一钝化层及第二钝化层,依序堆叠在所述导电接垫上,其中所述第一钝化层及所述第二钝化层填充所述导电接垫中的两个相邻的导电接垫之间的间隙,且所述第一钝化层包括:
第一区段,实质上平行于所述内连结构的顶表面延伸;以及
第二区段,面对所述导电接垫中的一者的侧表面,且所述第一区段的厚度与所述第二区段的厚度不同。
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