TWI462247B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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Description
本發明是關於半導體封裝,特別是關於一種具有兩個導電墊之半導體裝置及其製造方法。
當封裝一已形成電路的半導體晶片時,可使用覆晶封裝技術來內連接晶片上電路與一封裝基板上的輸入\輸出接腳。覆晶封裝組件包括直接電性連接一封裝基板與一面朝下放置在該封裝基板上的半導體晶片。其中,該封裝基板可為陶瓷基板、電路板、或在半導體晶片上放置導電凸塊而成的載體。覆晶技術正快速取代舊式打線技術。
在覆晶封裝時,需將半導體晶片翻轉並放置在一封裝基板上。導電凸塊通過回焊後形成半導體晶片與封裝基板間的電連接,並提供晶片與基板有限的結構支撐。在回焊的過程中,助焊劑被用來促進導電凸塊、半導體晶片上接合墊、及封裝基板上焊墊的結合。接著,移除多餘的助焊劑,並用例如環氧樹脂的底部填充劑去填入半導體晶片和封裝基板之間未被助焊劑填滿的空間,以達到半導體晶片和封裝基板之間更好的結構連結。此舉也增加了封裝結構連結的可靠度與疲勞強度,及把應力分布不平均降到最低。其中,應力不平均來自半導體晶片與封裝基板不同的熱膨脹係數所造成的溫度誘導應變。
如先前提到,在覆晶封裝技術裡,需把半導體晶片翻面且放置在封裝基板之上,然後加熱被翻面的半導體晶片。這些操作讓半導體晶片承受很大的應力與應變。隨著如低介電常數材質等結構強度較弱的材質日益普及,比起使用非低介電常數材質,半導體晶片在承受應力與應片時越來越脆弱。此外,當半導體晶片的尺寸增加,封裝過程中所造成的應力與應變也會增加。
本發明提供一種半導體裝置,包括:一基板;至少兩個導電墊,形成於該基板上,其中一個導電墊形成於另一個之上,且一重分佈層延伸至其中至少一個導電墊;一凸塊結構,形成於該些導電墊之上,並且與該些導電墊電性連接。
在另一實施例中,本發明之半導體裝置包括:一基板;三個導電墊,以一導電墊形成於另一導電墊之上的形式形成於該基板上,其中一重分佈層延伸至該至少一個導電墊;及一凸塊結構,形成於該些導電墊之上,並與該些導電墊電性連接。
在又一實施例中,本發明之半導體裝置包括:一基板;一第一導電墊,包括鋁銅合金且形成於基板之上;一第二導電墊,包括銅且形成於該第一導電墊之上,其中一重分佈層延伸至該第二導電墊;一第三導電墊,包括銅且形成於該第二導電墊之上;及一凸塊結構,形成於該第三導電墊之上,且與該第三導電墊電性連接。
本發明亦提供一種半導體裝置的製造方法,包括:形成一第一導電墊在一基板之上;形成一第二導電墊在該第一導電墊之上;當形成該第一導電墊或第二導電墊時,形成一重分佈層做為該第一導電墊或第二導電墊的一延伸部分;及形成一凸塊結構在該第二導電墊之上為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:
以下詳細說明實施例的使用以及製造方法。此實施例提供了許多可在廣泛的特定背景下被具體實現的應用概念。在此討論的特定具體實現方式僅供說明,並不限制其他可能性。一個技藝成熟的人應能理解其他替代方案。
第1圖是實施例中半導體裝置100的剖面圖。半導體裝置100具有一個已具有電路的基板110,其中,該基板包括許多在上形成的電子裝置與元件。兩個含金屬層120a及120b形成在基板110上,且其上形成一頂部含金屬層130。導電結構132在頂部含金屬層130上形成,並通過含金屬層120a及120b與在基板110上至少一部分的電路作電性連接。兩個導電墊142及144在兩含金屬層120a及120b與半導體基板110上形成,並且與導電結構132電性連接。凸塊結構150在導電墊142及144上形成,並與導電墊142及144互相電性連接。
在一些實施例中,凸塊結構150包括:在導電墊142及144上形成的一凸塊下金屬層152,在凸塊下金屬層上形成的一金屬柱154,在金屬柱154上形成的一金屬膜156,及一覆蓋在金屬柱上的蓋層158。在一實施例中,金屬柱154為銅或銅合金材質,金屬膜156為鎳、金或含鎳材質而蓋層158為金屬、焊劑或無鉛焊劑材質。
另外,一鈍化層160形成於頂部含金屬層130及導電結構132之上。開口162(第2B圖)及一系列重分佈導孔164(第2B圖顯示了三個示範性的重分佈導孔)穿過鈍化層160形成。導電墊142及144通過開口162形成連接。在一實施例中,導電墊142及導電結構132形成在頂部含金屬層130。以導電材質填入上述的重分佈導孔,形成一系列的重分佈導孔插塞166。導電重分佈結構172形成於鈍化層160之上且與導電墊144及導電結構132經由一系列的重分佈導孔插塞166連接。另一個鈍化層180形成於鈍化層160,導電重分佈結構172,及導電墊144之上。最後,保護層190,例如聚亞醯胺層,形成於鈍化層180之上。
在一些實施例中,導電重分佈結構172也被稱為重分佈層(RDL),並且也是導電墊144的一延伸部分。導電重分佈結構172及導電墊144可在同一製程中以相同材質形成。在一實施例中,導電結構132與導電重分佈結構172為金屬材質,如銅或含銅合金;用來填充重分佈導孔插塞166的材質與形成導電重分佈結構172的材質相同;而導電墊142是以形成導電結構132的導電材質形成。在一些實施例中,導電墊144的形成是填入穿過鈍化層160的開口以建立與導電墊142的電性連接,並使鈍化層160得以延伸進入導電墊142與導電墊144之間隙。在一實施例中,導電墊142為銅材質,而導電墊144為鋁銅合金。舉例來說,導電墊144為含0.5%銅的鋁銅合金。在其他實施例中,導電墊142及導電墊144可為相同或不同導電材質。另外,導電墊142及導電墊144具有能夠在結構上支撐凸塊下金屬組件150的尺寸與形狀。舉例來說,在一些實施例中,導電墊142及144為寬度80-85微米之間的八角形。
導電結構132,導電重分佈結構172,含金屬層120a及120b,及導電墊142及144的形成是為了讓基板110上一部份的電路及凸塊結構150之間可以電性連接。雖然第1圖中只顯示兩個含金屬層120a及120b,及一頂部含金屬層130,一些實施例包括了少於或多於兩個的含金屬層及一個頂部含金屬層。舉例來說,一些特定實施例包括八個含金屬層及一個頂部含金屬層;其他的實施例包括六個含金屬層及兩個頂部含金屬層。在一些實施例中,鈍化層160及180包括氮化矽,並可更包括少量的氧化物及/或碳化物。除此之外,在其他實施例中,鈍化層160及180可為相同或不同介電材質。
第2A~2F圖顯示了第1圖之半導體裝置100的製程剖面圖。第2A圖中,一導電墊142及由該導電墊142延伸出的導電結構形成於一頂部含金屬層130之中,且位於基板110與兩個含金屬層120a及120b之上。基板110上已形成電路。在第2B圖中,一介電層160形成於頂部含金屬層130之上,及導電墊142及導電結構132之上。介電層160是用來當作鈍化層,以保護其下結構。然後移除介電層160一部分以形成穿過該介電層160的開口162及重分佈導孔164。為簡化起見,圖裡只有顯示三個重分佈導孔164。在一些實施例中,重分佈導孔164有可能多或少於三個。
在第2C圖中,形成複數個填入重分佈導孔164的重分佈導孔插塞166,並且形成一導電重分佈結構172於介電層160之上。導電重分佈結構172透過重分佈導孔插塞166與導電結構132連接。另外,填入開口162,形成一導電墊144於導電墊142之上方,且導電墊144透過開口162與導電墊142連接。在一實施例中,導電重分佈結構172是導電墊144的一延伸部分。在第2D圖中,另一個被當作鈍化層的介電層180形成於介電層160、導電墊144,及導電重分佈結構172之上。在第2E圖中,接著在介電層180上形成一保護層190,然後形成一開口以暴露導電墊144的一部分。最後,在第2F圖中,在導電墊144上形成一凸塊下金屬組件150。
第3圖為一實施例中的半導體裝置300的剖面圖。半導體裝置300與第1圖中的實施例相似,具有一已形成電路的基板310。兩個含金屬層320a及320b形成於基板310之上,而一頂部含金屬層330形成於含金屬層320a及320b之上。一導電結構332形成於頂部含金屬層330之中,且透過含金屬層320a及320b與基板310上至少一部分的電路作電性連接。兩個導電墊342與344形成在含金屬層320a及320b與半導體基板310上,並與導電墊332電性連接。在一些實施例中,導電結構332是導電墊342的一延伸部分,且被當作重分佈層。一凸塊結構350形成於導電墊342及344之上,且與導電墊342及344電性連接。
另外,一鈍化層360形成於頂部含金屬層330、導電墊342,及導電結構332之上。一開口362(第4B圖)穿過鈍化層360形成。導電墊344形成於開口362之中及鈍化層350之上。導電墊342及導電墊344通過開口362連接(第4C圖)。在一實施例中,導電結構332為頂部含金屬層330之中的導電墊342的一延伸部分。最後,一保護層390,例如一聚亞醯胺層,形成於鈍化層360及導電墊344之上(第4D圖)。
一實施例與第1圖中的實施例相似,其中導電結構332為金屬材質,例如為銅或含銅合金。在一些實施例中,導電墊344的形成是填入穿過鈍化層360的開口362以建立與導電墊342的電性連接,並使讓鈍化層360得以延伸進入導電墊342與導電墊344之間隙。在一實施例中,導電墊342為銅材質,而導電層344為摻有0.5%銅的鋁銅合金。在其他實施例中,導電墊342及導電墊344可為同樣或不同材質。另外,導電墊342及導電墊344具有能夠在結構上支撐凸塊下金屬組件350的尺寸與形狀。舉例,在一些實施例中,導電墊342及344為寬度80-85微米之間的八角形。
導電結構332、含金屬層320a及320b,及導電墊342及344的形成是為了讓在基板310上的一部分的電路與凸塊結構350作電性連接。含金屬層320a及320b與頂部含金屬層330只是示範說明用,在一些實施例中,有可能有多或少於兩個含金屬層及一頂部含金屬層。另外,在一些實施例中,鈍化層360包括氮化矽,也可能更包括少量的氧化物及/或碳化物。
第4A~4E圖為第3圖之半導體裝置300的製程剖面圖。在第4A圖中,一導電墊342及從導電墊342所延伸出來的一導電結構332形成於一頂部含金屬層330之中,且位於基板310及兩個含金屬層320a及320b之上。導電墊342及導電結構332可同時形成。基板310上已形成電路。參照第4B圖,一介電層360形成於頂部含金屬層330、導電墊342及導電結構332之上。介電層360為一鈍化層,以保護其下結構。接著移除一部分的介電層360以形成穿過介電層360的一開口362。
參照第4C圖,導電墊344形成於導電墊342之上並通過開口362與導電墊342連接。參照第4D圖,在介電層360及一部分的導電墊344上形成一保護層390,此外,形成一開口以暴露導電墊344的一部分。最後,在第4E圖中,在導電墊344上形成一凸塊下金屬組件350。
第5圖為一實施例中一半導體裝置500的剖面圖。半導體裝置500與第1圖中的實施例相似,具有一已形成電路的基板510。兩個示範性的含金屬層520a及520b形成於基板510之上,而一示範性的頂部含金屬層530形成於含金屬層520a及520b之上。一導電結構532在含金屬層530之中形成,並透過含金屬層520a及520b與基板510上至少一部分的電路作電性連接。兩個導電墊542及544形成於含金屬層520a及520b,及半導體基板510之上,並與導電結構532電性連接。在一些實施例中,導電結構532為導電墊542的一延伸部分,並且用來當作重分佈層。一凸塊結構550形成於導電墊542及544之上,並與導電墊542及544電性連接。
另外,一鈍化層560形成於頂部含金屬層530及導電結構532之上。一開口562(第6B圖)穿過鈍化層560形成。導電墊542及導電墊544透過開口562而連接。在一實施例中,導電結構532為頂部含金屬層530中導電墊542的一延伸部分。最後,另一鈍化層580形成於鈍化層560及導電墊544之上,且一保護層590,如一聚亞醯胺層,形成於鈍化層580之上。
在一實施例中,導電結構532為金屬材質,例如銅或含銅合金;而形成導電墊542的導電材質與形成導電結構532的導電材質相同。在一些實施例中,導電墊544的形成是填入穿過鈍化層560的開口以建立與導電墊542的電性連接,並使鈍化層560得以延伸進入導電墊542與導電墊544之間隙。在一實施例中,導電墊542為銅材質,而導電墊544為含0.5%銅的鋁銅合金。在其他實施例中,導電墊542及導電墊544可為相同或不同的導電材質。除此之外,導電墊542與導電墊544具有能夠在結構上支撐凸塊下金屬組件550的尺寸與形狀。舉例來說,在一些實施例中,導電墊542及544為寬度80-85微米之間的八角形。
導電結構532、含金屬層520a及520b,及導電墊542及544的形成是為了讓在基板510上的一部分的電路與凸塊結構550作電性連接。含金屬層520a及520b與頂部含金屬層530只是示範說明用,在一些實施例中,可具有多於或少於兩個含金屬層及一頂部含金屬層。另外,在一些實施例中,鈍化層560及580可為相同或不同介電材質。舉例來說,鈍化層560及580可包括氮化矽,也可能更包括少量的氧化物及/或碳化物。
第6A~6E圖為第5圖之半導體裝置500的一製程剖面圖。在第6A圖中,一導電墊542及另一從導電墊542所延伸出來的導電墊532形成於頂部含金屬層530之中,且位於基板510與兩個含金屬層520a及520b之上。導電墊542及導電結構532可同時形成。基板510上已形成電路。參照第6B圖,一介電層560形成於頂部含金屬層530、導電墊542及導電結構532之上。介電層560為一鈍化層,以保護其下結構。接著移除一部分的介電層560以形成穿過介電層560的一開口562。
參照第6C圖,導電墊544形成於導電墊542之上並通過開口562與導電墊542連接。參照第6D圖,另一用來當作鈍化層的介電層580形成於介電層560及導電墊544之上。在第6E圖中,移除一部分的介電層580,接著,在介電層580之上形成一保護層590。最後,在第6F圖中,在導電墊544之上形成一凸塊下金屬組件550。
第7圖為一實施例中一半導體裝置700的剖面圖。該半導體裝置700與第1圖中的實施例相似,具有一已形成電路的基板710。兩個含金屬層720a及720b形成於基板710之上,而兩個頂部含金屬層730a及730b形成於含金屬層720a及720b之上。兩個導電結構732及734分別形成於頂部含金屬層730a及頂部含金屬層730b之中。導電結構732及734是透過形成於一頂部介電層738的一系列導孔插塞連接。其中,導孔插塞是由利用導電材質填入頂部導孔736所形成。兩個導電墊742及744形成於含金屬層720a及720b,及半導體基板710之上,並與導電結構732及734的其中至少一者電性連接。一凸塊結構750形成於導電墊742及744之上,並與導電墊742及744電性連接。
除此之外,頂部介電層738形成於導電結構732及導電墊742之上,及導電結構734及導電墊744之下。複數個開口746穿過頂部介電層738形成,此外,導電墊742及導電墊744透過複數個開口746連接。在一實施例中,只具有一個開口746;在其他實施例中,開口746形成一系列的導孔。導電結構734形成於頂部介電層738之上,及一鈍化層760之下,其中該鈍化層形成於頂部含金屬層730a及730b,及導電結構734及導電墊744之上。最後,形成一保護層790,例如一聚亞醯胺層,於鈍化層760及導電墊744之上。
導電結構732及導電墊742形成於頂部含金屬層730a之中,而導電結構734及導電墊744形成於頂部金屬層730b之中。導電結構732與導電墊742在頂部含金屬層730a連接,而導電結構734與導電墊744在頂部含金屬層730b連接。在其他實施例中,只有導電結構732及734的其中一個結構連接到相對應的導電墊742及744。在一些實施例中,導電結構732或734其中至少有一個分別是導電墊742或744的一延伸部分,且為一重分佈層。在一特定的實施例中,導電結構732是導電墊742的一延伸部分,且被用來當作一重分佈層,而導電結構734是導電墊744的一延伸部分,並且被用來當作另一重分佈層。
在相似於第1圖裡所呈現實施例的一實施例中,導電結構732及734為同樣材質,例如銅或含銅合金。在一些實施例中,導電墊744的形成是先由填入穿過頂部介電層738形成的開口746以建立與導電墊742的電性連接,接著導電墊744與導電結構734同時形成。在一實施例中,導電墊742及744為銅材質。在其他實施例中,導電墊742及導電墊744可為相同或不同材質。除此之外,導電墊742和導電墊744具有能夠在結構上支撐凸塊下金屬組件750的尺寸與形狀。
導電結構732及734,含金屬層720a及720b,及導電墊742及744的形成讓基板710上的一部分電路可以跟凸塊結構750電性連接。含金屬層720a及720b及頂部含金屬層730a及730b只是示範說明用,在一些實施例中,可以包括多於或少於兩個的含金屬層及兩個頂部含金屬層。另外,在一些實施例中,鈍化層760包括氮化矽,也可更包括少量的氧化物及/或碳化物。
第8A~8D圖為第7圖之半導體裝置700的製程剖面圖。在第8A圖中,一導電墊742及從導電墊742所延伸出來的一導電結構732形成於頂部含金屬層730a之中,且位於基板710及兩個含金屬層720a及720b之上。導電墊742及導電結構732可同時形成。基板710上已形成電路。接著,形成一介電層738於頂部含金屬層730a及導電墊及導電結構732之上。在此,介電層738是用來當作一頂部介電層,以分離頂部含金屬層730a及另外的頂部含金屬層730b。一部分的介電層738被移除以形成穿過介電層738的複數個開口(導孔)746及頂部導孔736。以一導電材質填入頂部導孔736,且形成一導電結構734於導電結構732之上,其中導電結構734透過頂部導孔736與導電結構732連接,以一導電材質填入複數個開口746,且形成導電墊744於導電墊742之上,其中導電墊744透過複數個開口746與導電墊742連接。除此之外,導電墊744及從導電墊744延伸的導電結構734形成於頂部含金屬層730b之中,且位於介電層738之上。
參照第8B圖,形成另一介電層760在導電墊744及導電結構734之上。介電層760是用來當作一鈍化層以保護其下結構。接著,移除一部分的介電層760,且進一步在介電層760之上形成一保護層790,除此之外,形成一開口以暴露導電墊744的一部分。最後,在第8D圖中,在導電墊744上形成一凸塊下金屬組件750。
第9圖是在一實施例中半導體裝置900的剖面圖。與第1圖中描繪的實施例相似的是,該半導體裝置900具有一已形成電路的基板910。兩個含金屬層920a及920b形成於基板910之上,而兩個頂部含金屬層930形成於含金屬層920a及920b之上。一導電結構932形成於頂部含金屬層930之中,且透過含金屬層920a及920b與基板910上至少一部分的電路形成電性連接。三個導電墊942、944及946,形成於含金屬層920a及920b及半導體基板950之上,且與導電結構932電性連接。一凸塊結構950形成於導電墊942、944及946之上,且與導電墊942、944及946電性連接。
除此之外,一鈍化層960形成於頂部含金屬層930及導電結構932之上,一開口962(第10B圖)及一系列的重分佈導孔964(第10B圖,三個示範說明用的重分佈導孔如圖示)穿過鈍化層960形成。導電墊942(較下層墊)及導電墊944(中層墊)通過開口962連接。在一實施例中,導電墊942及從導電墊942所延伸出來的導電結構932形成於頂部含金屬層930之中。以一導電材質填入一系列的重分佈導孔,形成一系列的重分佈導孔插塞966。一導電重分佈結構972形成於鈍化層960之上,與導電墊944連接,並透過一系列的重分佈導孔插塞966與導電結構932連接。
除此之外,另一個鈍化層980形成於鈍化層960、導電重分佈結構972,及導電墊944之上。另一導電墊946(較上方墊)接著形成於凸塊結構950之下及導電墊944之上,且透過一穿過於鈍化層980的開口與導電墊944連接。最後,一保護層990,例如一聚亞醯胺層,形成於該鈍化層980之上。
在一些實施例中,導電重分佈結構972也被稱作重分佈層,並且是導電墊944的一延伸部分。在一實施例中,導電結構932及導電重分佈結構972為金屬材質,例如銅或含銅合金;用來填入重分佈導孔插塞966的導電材質與用來填入導電重分佈結構972的材質相同;形成導電墊942的材質與形成導電結構932的導電材質相同。在一些實施例中,導電墊944的形成是填入穿過鈍化層960的開口以建立與導電墊942的電性連接,並使鈍化層960得以延伸進入導電墊942與導電墊944之間隙。導電墊946的形成與導電墊944的形成相似,是為了使鈍化層980可延伸進入導電墊944及導電墊946之間隙。在一實施例中,導電墊942為銅材質,且導電墊944及946為含0.5%銅的鋁銅合金。在其他的實施例中,導電墊942、944,及946可為相同或不同的導電材質。除此之外,導電墊942、944及946具有能夠在結構上支撐凸塊下金屬組件950的尺寸與形狀。舉例來說,在一些實施例中,導電墊942、944,及946為寬度80-85微米之間的八角形。
導電結構932及972,含金屬層920a及920b,及導電墊942、944及946的形成,是為了讓基板910上一部分的電路與凸塊結構950作電性連接。
第10A-10F圖顯示第9圖之半導體裝置900的一製程剖面圖。在第10A圖中,導電墊942及導電結構932同時於頂部含金屬層930之中形成,且位於基板910及兩個含金屬層920a及920b之上。在一些實施例中,導電結構932是導電墊942的一延伸部分,且被當作是一重分佈層。基板910上已形成電路。參照第10B圖,一介電層960形成於頂部含金屬層930、導電墊942,及導電結構932之上。該介電層960被用來當作一鈍化層以保護其下結構。接著,移除介電層960的一部分以形成穿過介電層960的一開口962及三個重分佈導孔964。在一些實施例中,有可能具有多或少於三個重分佈導孔964。
參照第10C圖,形成複數個填入重分佈導孔964的重分佈導孔插塞966,並且形成導電重分佈結構972於介電層960之上。導電重分佈結構972透過重分佈導孔插塞966連接到導電結構932。除此之外,填入開口962,形成一導電墊944於導電墊942之上,且透過開口964與導電墊942連接。在一實施例中,導電重分佈結構972為導電墊944的一延伸部分。參照第10D圖,被當作鈍化層的另一介電層980形成於介電層960、導電墊944,及導電重分佈結構972之上。除此之外,一第三導電墊946形成於介電層980之上。導電墊946透過一穿過介電層980的開口連接到導電墊944。在第10E圖中,接著在介電層980及導電墊946之上形成一保護層990,且形成一開口以暴露導電墊946的一部分。最後,在第10F圖中,在導電墊946上形成一凸塊下金屬組件950。
第11圖為一實施例中一半導體裝置1100的剖面圖。與第7圖中描繪的實施例相似的是,該半導體裝置1100有一已形成電路的基板1110。兩個含金屬層1120a及1120b形成於基板1110之上,而兩個頂部含金屬層1130a及1130b形成於含金屬層1120a及1120b之上。兩個導電結構1132及1134分別形成於頂部含金屬層1130a及1130b之中。導電結構1132及1134透過在一頂部介電層1138之中一系列的頂部導孔插塞相互連接,其中頂部導孔插塞是由以一導電材質填補一系列頂部導孔1136形成。三個導電墊1142、1144及1146形成於含金屬層1120a及1120b,及半導體基板1110之上,並與導電結構1132及1134的其中至少一者電性連接。一凸塊結構1150形成於導電墊1142、1144及1146之上,並與導電墊1142、1144及1146電性連接。
再者,頂部介電層1138形成於導電結構1132及導電墊1142之上,且位於導電結構1134及導電墊1144之下。複數個開口1148穿過頂部介電層1138形成,而導電墊1142(底層墊)透過開口1148與導電墊1144(中間墊)連接。在一實施例中,只具有一開口1148;在其他實施例中,複數個開口1148形成為導孔。導電結構1134形成於頂部介電層1138之上,及一鈍化層1160之下。其中該鈍化層形成於頂部含金屬層1130a及1130b,及導電結構1132及1134上方。
一鈍化層1160形成於頂部含金屬層1130b及導電結構1134之上。一開口1162(第12B圖)穿過鈍化層1160形成。導電墊1146(頂部墊)及導電墊1144透過開口1162連接。最後,一保護層1190,例如一聚亞醯胺層,形成於鈍化層1160及導電墊1146之上。在一些實施例中,鈍化層1160延伸進入導電墊1144及導電墊1146之間隙。
導電結構1132及導電墊1142形成於頂部含金屬層1130a之中,而導電結構1134及導電墊1144形成於頂部含金屬層1130b之中。導電結構1132與導電墊1142在頂部含金屬層1130a之中連接,而導電結構1134與導電墊1144在頂部含金屬層1130b之中連接。在其他實施例中,在導電結構1132及1134中只有一個與對應的導電墊1142及1144連接。在一些實施例中,導電結構1132或1134之中至少有一個是分別對應的導電墊1142或1144的一延伸部分,且被用來當作一重分佈層。在一特定實施例中,導電結構1132是導電墊1142的一延伸部分,且被當成一重分佈層,而導電結構1134為導電墊1144的一延伸部分,且被當成另一重分佈層。
一實施例與第7圖中的實施例相似,其中導電結構1132及1134為金屬材質,例如為銅或含銅合金。在一些實施例中,導電墊1144的形成是先由填入穿過頂部介電層1138的開口1146以建立與導電墊1142的電性連接,接著導電墊1144與導電結構1134同時形成。在一實施例中,導電墊1142及1144為銅材質,而導電墊1146為含0.5%的鋁銅合金。在一些實施例中,導電墊1142、1144,及1146可為相同或不同導電材質,除此之外,導電墊1142、1144,及1146具有能夠在結構上支撐凸塊下金屬組件1150的尺寸與形狀。
導電結構1132及1134、含金屬層1120a及1120b,及導電墊1142、1144及1146的形成是為了讓在基板1110上的一部分的電路與凸塊結構1150作電性連接。含金屬層1120a及1120b,及頂部含金屬層1130a及1130b僅供示範說明用,在一些實施例中,可具有多於或少於兩個含金屬層及兩個頂部含金屬層。除此之外,在一些實施例中,鈍化層1160包括氮化矽,也可更包括少量的氧化物及/或碳化物。
第12A-12E圖顯示第11圖之半導體裝置1100的一製程剖面圖。在第12A圖中,一導電墊1142及從導電墊1142延伸出的一導電結構1132形成於一頂部含金屬層1130之中,且位於基板1110及兩個含金屬層1120a及1120b之上。導電墊1142及一導電結構1132可同時形成。基板1110上已形成電路。接著一介電層1138形成於頂部含金屬層1130a之上,且位於導電墊1142及導電結構1132之上。介電層1138是用來當作一頂部介電層以分離頂部含金屬層1130a與另一頂部含金屬層1130b。一部分的介電層1138被移除以形成穿過介電層1138的複數個開口1148及複數個頂部導孔1136。以一導電材質填入複數個頂部導孔1136,且在其上形成一導電結構1134,導電結構1134透過頂部導孔1136連接到導電結構1132,以一導電材質填入複數個開口1148,且在導電墊1142上形成一導電墊1144,導電墊1144透過開口1148與導電墊1142連接。除此之外,在一些實施例中,導電墊1144及從導電墊1132延伸出的導電結構1134同時形成於介電層1138之中及頂部含金屬層1130b之上。
參照第12B圖,另一介電層1160形成於導電墊1144及導電結構1134之上。介電層1160被用來當作一鈍化層,以保護其下結構。接著,移除介電層1160的一部分以形成一另外開口1162。參照第12C圖,填入開口1162,而一導電墊1146形成於導電墊1144之上,且導電墊1146透過開口1162與導電墊1144連接。在第12D圖中,進一步在介電層1160及導電墊1146上形成一保護層1190,形成一開口以暴露導電墊1146的一部分。最後,在第12E圖中,在導電墊1146之上形成一凸塊下金屬組件。
此處揭露了半導體裝置各種不同的實施例。具有兩個或以上導電墊的半導體裝置可保護避免金屬間介電層產生接合面剝離,或其他因凸塊結構應力與應變或封裝過程引起的缺陷。所揭露的特定實施例與圖示並不是最詳盡的。雖然此揭露只描述了三個導電墊,但可以使用更多的導電墊,以進一步增強凸塊結構在結構上的支撐以及封裝過程。因此可在更多導電墊所帶來的好處,與更多晶圓處理步驟及晶片翹曲所引起的更高內應力所帶來的壞處之中取捨,並找到一個恰當的平衡點。
此關於示範說明用的實施例敘述應與相對應的伴隨圖示一起閱讀,因這些圖示被視為是整個敘述的一部分。在敘述裡相關的術語,例如較下方、較上方、水平、垂直、之上、之下、上、下、頂部、最下方、以及其他衍生詞(例:水平地、向下地、向上地等等)應可被理解成有關當時描述或正在討論的圖示的方向。這些相關詞是為了描述的便利,並不需要裝置在一特定方向被建構或被使用。有關相連或相接,以及其他同類詞,例如連接,內連接,除非特別敘述,皆是指結構之間彼此直接或透過中間結構間接被穩固或附著的關係,並可包括固定式或可動式的結合或關係。
雖然本發明已以數個較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作任意之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100、300、500、700、900、1100...半導體裝置
110、310、510、710、910、1110...基板
120a、120b、320a、320b、520a、520b、720a、720b、920a、920b、1120a、1120b...含金屬層
130、330、530、730a、730b、930、1130a、1130b‧‧‧頂部含金屬層
132、332、532、732、734、932、1132、1134‧‧‧導電結構
142、144、342、344、542、544、742、744、942、944、946、1142、1144、1146‧‧‧導電墊
150、350、550、750、950、1150‧‧‧凸塊下金屬組件
152‧‧‧凸塊下金屬層
154‧‧‧金屬柱
156‧‧‧金屬膜
158‧‧‧蓋層
160、180、360、560、580、760、960、980、1160‧‧‧鈍化層
162、362、562、746、962、1148、1162‧‧‧開口
164、964‧‧‧重分佈導孔
166、966‧‧‧重分佈導孔插塞
172、972‧‧‧導電重分佈結構
190、390、590、790、990、1190‧‧‧保護層
736、1136‧‧‧頂部導孔
738、1138‧‧‧頂部介電層
第1圖為一實施例中一半導體裝置的剖面圖;
第2A~2F圖為第1圖中所示之半導體裝置的製程剖面圖;
第3圖為一實施例中一半導體裝置的剖面圖;
第4A~4E圖為第3圖中所示之半導體裝置的製程剖面圖;
第5圖為一實施例中一半導體裝置的剖面圖;
第6A~6F圖為第5圖中所示之半導體裝置的製程剖面圖;
第7圖為一實施例中一半導體裝置的剖面圖;
第8A~8D圖為第7圖中所示之半導體裝置的製程剖面圖;
第9圖為一實施例中一半導體裝置的剖面圖;
第10A~10F圖為第9圖中所示之半導體裝置的製程剖面圖;
第11圖為一實施例中一半導體裝置的剖面圖;及
第12A~12E圖為第11圖中所示之半導體裝置的一製程剖面圖。
100...半導體裝置
110...基板
120a、120b...含金屬層
130...頂部含金屬層
132...導電結構
142、144...導電墊
150...凸塊下金屬組件
152...凸塊下金屬層
154...金屬柱
156...金屬膜
158...蓋層
160...鈍化層
166...重分佈導孔插塞
172...導電重分佈結構
180...鈍化層
190...保護層
Claims (10)
- 一種半導體裝置,包括:一基板;至少兩個導電墊,形成於該基板上,其中一個導電墊形成於另一個之上,而至少有兩個導電墊為直接接觸,且一重分佈層延伸至其中至少一個導電墊;及一凸塊結構,形成於該些導電墊之上,並且與該些導電墊電性連接。
- 如申請專利範圍第1項所述之半導體裝置,更包括一介電層,延伸進入該至少兩個導電墊之一第一導電墊與一第二導電墊之間隙。
- 如申請專利範圍第1項所述之半導體裝置,其中該凸塊結構包括:一金屬柱,形成於該些導電墊之上;一金屬膜,形成於該金屬柱之上;及一蓋層,形成於該金屬膜之上。
- 如申請專利範圍第1項所述之半導體裝置,其中該至少兩個導電墊包括一第一導電墊及一第二導電墊,而該第二導電墊形成於該第一導電墊之上,並且該第一導電墊與該第二導電墊其中之一具有該重分佈層。
- 一種半導體裝置,包括:一基板;三個導電墊,以一導電墊形成於另一導電墊之上的形式形成於該基板上,而至少有兩個導電墊為直接接觸,且其中一重分佈層延伸至該至少一個導電墊;及 一凸塊結構,形成於該些導電墊之上,並與該些導電墊電性連接。
- 如申請專利範圍第5項所述之半導體裝置,其中該重分佈層延伸至一中間導電墊。
- 如申請專利範圍第5項所述之半導體裝置,其中一中間導電墊包括銅,一頂部導電墊包括銅,而一最下方導電墊包括一鋁銅合金。
- 一種半導體裝置的製造方法,包括:以一導電墊形成於另一導電墊之上的形式,形成至少兩個導電墊於該基板上,且至少有兩個導電墊為直接接觸;當形成該些導電墊時,形成一重分佈層做為該些導電墊中至少一導電墊的一延伸部分;及形成一凸塊結構在該些導電墊之上。
- 如申請專利範圍第8項所述之半導體裝置的製造方法,其中該重分佈層在形成一第一導電墊時形成,並且更包括另一重分佈層在形成一第二導電墊時形成。
- 如申請專利範圍第8項所述之半導體裝置的製造方法,其中形成該些導電墊包括形成一第二導電墊於一第一導電墊之上及形成一第三導電墊於該第二導電墊之上,且該重分佈層在形成該第二導電墊時形成。
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Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8227916B2 (en) * | 2009-07-22 | 2012-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method for reducing dielectric layer delamination |
US20110121438A1 (en) | 2009-11-23 | 2011-05-26 | Xilinx, Inc. | Extended under-bump metal layer for blocking alpha particles in a semiconductor device |
US8294264B2 (en) * | 2010-03-30 | 2012-10-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Radiate under-bump metallization structure for semiconductor devices |
US8193639B2 (en) * | 2010-03-30 | 2012-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy metal design for packaging structures |
US9105588B2 (en) * | 2010-10-21 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor component having a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer |
US8492892B2 (en) * | 2010-12-08 | 2013-07-23 | International Business Machines Corporation | Solder bump connections |
US9099396B2 (en) | 2011-11-08 | 2015-08-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post-passivation interconnect structure and method of forming the same |
DE102013105721B4 (de) | 2013-03-15 | 2024-01-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Halbleitervorrichtung mit einer Nach-Passivierung-Verbindungs-Struktur und Verfahren zu dessen Herstellung |
KR102154112B1 (ko) * | 2013-08-01 | 2020-09-09 | 삼성전자주식회사 | 금속 배선들을 포함하는 반도체 장치 및 그 제조 방법 |
CN105336848B (zh) * | 2014-06-12 | 2018-01-09 | 中芯国际集成电路制造(上海)有限公司 | Mram器件的形成方法 |
KR102387541B1 (ko) * | 2015-03-25 | 2022-04-18 | 삼성전자주식회사 | 반도체 칩, 및 이를 포함하는 플립 칩 패키지와 웨이퍼 레벨 패키지 |
US9916999B2 (en) * | 2015-06-04 | 2018-03-13 | Micron Technology, Inc. | Methods of fabricating a semiconductor package structure including at least one redistribution layer |
TWI651819B (zh) * | 2016-11-28 | 2019-02-21 | 矽品精密工業股份有限公司 | 基板結構及其製法 |
CN108666287B (zh) * | 2017-04-01 | 2020-07-28 | 中芯国际集成电路制造(北京)有限公司 | 一种焊盘结构 |
US10249583B1 (en) * | 2017-09-19 | 2019-04-02 | Infineon Technologies Ag | Semiconductor die bond pad with insulating separator |
CN109920787B (zh) * | 2017-12-12 | 2021-05-25 | 中芯国际集成电路制造(北京)有限公司 | 互连结构的设计方法、装置及制造方法 |
JP7319808B2 (ja) * | 2019-03-29 | 2023-08-02 | ローム株式会社 | 半導体装置および半導体パッケージ |
US10923421B2 (en) * | 2019-04-23 | 2021-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of manufacturing the same |
US11670608B2 (en) * | 2019-09-27 | 2023-06-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Prevention of metal pad corrosion due to exposure to halogen |
US11069562B1 (en) | 2020-01-15 | 2021-07-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Passivation layer for integrated circuit structure and forming the same |
US11973050B2 (en) | 2021-02-02 | 2024-04-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming an upper conductive structure having multilayer stack to decrease fabrication costs and increase performance |
US11978713B2 (en) * | 2022-05-20 | 2024-05-07 | Western Digital Technologies, Inc. | Flip chip bump with multi-PI opening |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5470787A (en) * | 1994-05-02 | 1995-11-28 | Motorola, Inc. | Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same |
US6297563B1 (en) * | 1998-10-01 | 2001-10-02 | Yamaha Corporation | Bonding pad structure of semiconductor device |
TW200512857A (en) * | 2003-09-26 | 2005-04-01 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for fabricating the same |
Family Cites Families (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4985925A (en) * | 1988-06-24 | 1991-01-15 | Sensor Electronics, Inc. | Active noise reduction system |
US5027410A (en) * | 1988-11-10 | 1991-06-25 | Wisconsin Alumni Research Foundation | Adaptive, programmable signal processing and filtering for hearing aids |
NO169689C (no) * | 1989-11-30 | 1992-07-22 | Nha As | Programmerbart hybrid hoereapparat med digital signalbehandling samt fremgangsmaate ved deteksjon og signalbehandlingi samme. |
US5402496A (en) * | 1992-07-13 | 1995-03-28 | Minnesota Mining And Manufacturing Company | Auditory prosthesis, noise suppression apparatus and feedback suppression apparatus having focused adaptive filtering |
US6563931B1 (en) * | 1992-07-29 | 2003-05-13 | K/S Himpp | Auditory prosthesis for adaptively filtering selected auditory component by user activation and method for doing same |
JPH08293523A (ja) * | 1995-02-21 | 1996-11-05 | Seiko Epson Corp | 半導体装置およびその製造方法 |
US6434246B1 (en) * | 1995-10-10 | 2002-08-13 | Gn Resound As | Apparatus and methods for combining audio compression and feedback cancellation in a hearing aid |
JPH113984A (ja) * | 1997-06-13 | 1999-01-06 | Hitachi Ltd | 半導体集積回路装置 |
TW444252B (en) * | 1999-03-19 | 2001-07-01 | Toshiba Corp | Semiconductor apparatus and its fabricating method |
US6258705B1 (en) * | 2000-08-21 | 2001-07-10 | Siliconeware Precision Industries Co., Ltd. | Method of forming circuit probing contact points on fine pitch peripheral bond pads on flip chip |
US6754356B1 (en) * | 2000-10-06 | 2004-06-22 | Gn Resound As | Two-stage adaptive feedback cancellation scheme for hearing instruments |
US6831986B2 (en) * | 2000-12-21 | 2004-12-14 | Gn Resound A/S | Feedback cancellation in a hearing aid with reduced sensitivity to low-frequency tonal inputs |
US6674174B2 (en) * | 2001-11-13 | 2004-01-06 | Skyworks Solutions, Inc. | Controlled impedance transmission lines in a redistribution layer |
US6743660B2 (en) * | 2002-01-12 | 2004-06-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method of making a wafer level chip scale package |
JP3829325B2 (ja) | 2002-02-07 | 2006-10-04 | 日本電気株式会社 | 半導体素子およびその製造方法並びに半導体装置の製造方法 |
US6650010B2 (en) | 2002-02-15 | 2003-11-18 | International Business Machines Corporation | Unique feature design enabling structural integrity for advanced low K semiconductor chips |
US7092529B2 (en) * | 2002-11-01 | 2006-08-15 | Nanyang Technological University | Adaptive control system for noise cancellation |
US7470997B2 (en) * | 2003-07-23 | 2008-12-30 | Megica Corporation | Wirebond pad for semiconductor chip or wafer |
TWI227557B (en) * | 2003-07-25 | 2005-02-01 | Advanced Semiconductor Eng | Bumping process |
TWI220308B (en) * | 2003-08-07 | 2004-08-11 | Advanced Semiconductor Eng | Under bump metallurgic layer |
US7208758B2 (en) * | 2003-09-16 | 2007-04-24 | Micron Technology, Inc. | Dynamic integrated circuit clusters, modules including same and methods of fabricating |
WO2005081584A2 (en) * | 2004-02-20 | 2005-09-01 | Gn Resound A/S | Hearing aid with feedback cancellation |
JP2005243907A (ja) * | 2004-02-26 | 2005-09-08 | Renesas Technology Corp | 半導体装置 |
US7425767B2 (en) * | 2004-07-14 | 2008-09-16 | Megica Corporation | Chip structure with redistribution traces |
US7468545B2 (en) * | 2005-05-06 | 2008-12-23 | Megica Corporation | Post passivation structure for a semiconductor device and packaging process for same |
JP2006332533A (ja) * | 2005-05-30 | 2006-12-07 | Fujitsu Ltd | 半導体素子及びその製造方法 |
TWI281699B (en) * | 2005-07-26 | 2007-05-21 | Siliconware Precision Industries Co Ltd | Semiconductor device and fabrication method thereof |
US7566650B2 (en) | 2005-09-23 | 2009-07-28 | Stats Chippac Ltd. | Integrated circuit solder bumping system |
TW200733270A (en) * | 2005-10-19 | 2007-09-01 | Koninkl Philips Electronics Nv | Redistribution layer for wafer-level chip scale package and method therefor |
US7397121B2 (en) * | 2005-10-28 | 2008-07-08 | Megica Corporation | Semiconductor chip with post-passivation scheme formed over passivation layer |
JP4611943B2 (ja) * | 2006-07-13 | 2011-01-12 | Okiセミコンダクタ株式会社 | 半導体装置 |
WO2008051569A2 (en) * | 2006-10-23 | 2008-05-02 | Starkey Laboratories, Inc. | Entrainment avoidance with pole stabilization |
JP2008258258A (ja) | 2007-04-02 | 2008-10-23 | Sanyo Electric Co Ltd | 半導体装置 |
KR101479512B1 (ko) * | 2008-01-22 | 2015-01-08 | 삼성전자주식회사 | 반도체 패키지의 제조방법 |
CN101599445B (zh) * | 2008-06-03 | 2012-05-16 | 中芯国际集成电路制造(北京)有限公司 | 焊垫结构的形成方法 |
JP5102726B2 (ja) * | 2008-09-08 | 2012-12-19 | ラピスセミコンダクタ株式会社 | 半導体装置の製造方法 |
US8916464B2 (en) * | 2008-12-29 | 2014-12-23 | International Business Machines Corporation | Structures and methods for improving solder bump connections in semiconductor devices |
US7977783B1 (en) * | 2009-08-27 | 2011-07-12 | Amkor Technology, Inc. | Wafer level chip size package having redistribution layers |
-
2010
- 2010-10-15 US US12/905,276 patent/US8659170B2/en active Active
-
2011
- 2011-01-20 CN CN2011100250516A patent/CN102157479A/zh active Pending
- 2011-01-20 TW TW100102072A patent/TWI462247B/zh active
-
2014
- 2014-01-16 US US14/156,564 patent/US9129818B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5470787A (en) * | 1994-05-02 | 1995-11-28 | Motorola, Inc. | Semiconductor device solder bump having intrinsic potential for forming an extended eutectic region and method for making and using the same |
US6297563B1 (en) * | 1998-10-01 | 2001-10-02 | Yamaha Corporation | Bonding pad structure of semiconductor device |
TW200512857A (en) * | 2003-09-26 | 2005-04-01 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for fabricating the same |
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