CN102157479A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN102157479A CN102157479A CN2011100250516A CN201110025051A CN102157479A CN 102157479 A CN102157479 A CN 102157479A CN 2011100250516 A CN2011100250516 A CN 2011100250516A CN 201110025051 A CN201110025051 A CN 201110025051A CN 102157479 A CN102157479 A CN 102157479A
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Abstract
本发明公开了一种半导体装置及其制造方法,该半导体装置,包含至少两个导电垫,其中,一导电垫形成于至少两个导电垫之中的另一个导电垫上,及从至少一个导电垫延伸出来的一重分布层。该半导体装置也包含了一形成于导电垫之上且与导电垫电性连接的凸块结构。本发明具有两个或以上导电垫的半导体装置可保护避免金属间介电层产生接合面剥离,或其他因凸块结构应力与应变或封装过程引起的缺陷。
Description
技术领域
本发明涉及一种半导体封装,特别是涉及一种具有两个导电垫的半导体装置及其制造方法。
背景技术
当封装一已形成电路的半导体芯片时,可使用倒装芯片封装技术来内连接芯片上电路与一封装基板上的输入\输出接脚。倒装芯片封装组件包括直接电性连接一封装基板与一面朝下放置在该封装基板上的半导体芯片。其中,该封装基板可为陶瓷基板、电路板、或在半导体芯片上放置导电凸块而成的载体。倒装芯片技术正快速取代旧式打线技术。
在倒装芯片封装时,需将半导体芯片翻转并放置在一封装基板上。导电凸块通过回焊后形成半导体芯片与封装基板间的电连接,并提供芯片与基板有限的结构支撑。在回焊的过程中,助焊剂被用来促进导电凸块、半导体芯片上接合垫、及封装基板上焊垫的结合。接着,移除多余的助焊剂,并用例如环氧树脂的底部填充剂去填入半导体芯片和封装基板之间未被助焊剂填满的空间,以达到半导体芯片和封装基板之间更好的结构连结。此举也增加了封装结构连结的可靠度与疲劳强度,及把应力分布不平均降到最低。其中,应力不平均来自半导体芯片与封装基板不同的热膨胀系数所造成的温度诱导应变。
如先前提到,在倒装芯片封装技术里,需把半导体芯片翻面且放置在封装基板之上,然后加热被翻面的半导体芯片。这些操作让半导体芯片承受很大的应力与应变。随着如低介电常数材质等结构强度较弱的材质日益普及,比起使用非低介电常数材质,半导体芯片在承受应力与应片时越来越脆弱。此外,当半导体芯片的尺寸增加,封装过程中所造成的应力与应变也会增加。
发明内容
为克服现有技术的缺陷,本发明提供一种半导体装置,包括:一基板;至少两个导电垫,形成于该基板上,其中一个导电垫形成于另一个之上,且一重分布层延伸至其中至少一个导电垫;一凸块结构,形成于所述多个导电垫之上,并且与所述多个导电垫电性连接。
在另一实施例中,本发明的半导体装置包括:一基板;三个导电垫,以一导电垫形成于另一导电垫之上的形式形成于该基板上,其中一重分布层延伸至该至少一个导电垫;及一凸块结构,形成于所述多个导电垫之上,并与所述多个导电垫电性连接。
在又一实施例中,本发明的半导体装置包括:一基板;一第一导电垫,包括铝铜合金且形成于基板之上;一第二导电垫,包括铜且形成于该第一导电垫之上,其中一重分布层延伸至该第二导电垫;一第三导电垫,包括铜且形成于该第二导电垫之上;及一凸块结构,形成于该第三导电垫之上,且与该第三导电垫电性连接。
本发明也提供一种半导体装置的制造方法,包括:形成一第一导电垫在一基板之上;形成一第二导电垫在该第一导电垫之上;当形成该第一导电垫或第二导电垫时,形成一重分布层做为该第一导电垫或第二导电垫的一延伸部分;及形成一凸块结构在该第二导电垫之上。
本发明具有两个或以上导电垫的半导体装置可保护避免金属间介电层产生接合面剥离,或其他因凸块结构应力与应变或封装过程引起的缺陷。
为让本发明的上述和其他目的、特征、和优点能更明显易懂,下文特举出较佳实施例,并配合附图,作详细说明如下。
附图说明
图1为一实施例中一半导体装置的剖面图;
图2A~图2F为图1中所示的半导体装置的工艺剖面图;
图3为一实施例中一半导体装置的剖面图;
图4A~图4E为图3中所示的半导体装置的工艺剖面图;
图5为一实施例中一半导体装置的剖面图;
图6A~图6F为图5中所示的半导体装置的工艺剖面图;
图7为一实施例中一半导体装置的剖面图;
图8A~图8D为图7中所示的半导体装置的工艺剖面图;
图9为一实施例中一半导体装置的剖面图;
图10A~图10F为图9中所示的半导体装置的工艺剖面图;
图11为一实施例中一半导体装置的剖面图;及
图12A~图12E为图11中所示的半导体装置的一工艺剖面图。
【主要元件符号说明】
100、300、500、700、900、1100~半导体装置
110、310、510、710、910、1110~基板
120a、120b、320a、320b、520a、520b、720a、720b、920a、920b、1120a、1120b~含金属层
130、330、530、730a、730b、930、1130a、1130b~顶部含金属层
132、332、532、732、734、932、1132、1134~导电结构
142、144、342、344、542、544、742、744、942、944、946、1142、1144、1146~导电垫
150、350、550、750、950、1150~凸块下金属组件
152~凸块下金属层
154~金属柱
156~金属膜
158~盖层
160、180、360、560、580、760、960、980、1160~钝化层
162、362、562、746、962、1148、1162~开口
164、964~重分布导孔
166、966~重分布导孔插塞
172、972~导电重分布结构
190、390、590、790、990、1190~保护层
736、1136~顶部导孔
738、1138~顶部介电层
具体实施方式
以下详细说明实施例的使用以及制造方法。此实施例提供了许多可在广泛的特定背景下被具体实现的应用概念。在此讨论的特定具体实现方式仅供说明,并不限制其他可能性。本领域普通技术人员应能理解其他替代方案。
图1是实施例中半导体装置100的剖面图。半导体装置100具有一个已具有电路的基板110,其中,该基板包括许多在上形成的电子装置与元件。两个含金属层120a及120b形成在基板110上,且其上形成一顶部含金属层130。导电结构132在顶部含金属层130上形成,并通过含金属层120a及120b与在基板110上至少一部分的电路作电性连接。两个导电垫142及144在两含金属层120a及120b与半导体基板110上形成,并且与导电结构132电性连接。凸块结构150在导电垫142及144上形成,并与导电垫142及144互相电性连接。
在一些实施例中,凸块结构150包括:在导电垫142及144上形成的一凸块下金属层152,在凸块下金属层上形成的一金属柱154,在金属柱154上形成的一金属膜156,及一覆盖在金属柱上的盖层158。在一实施例中,金属柱154为铜或铜合金材质,金属膜156为镍、金或含镍材质而盖层158为金属、焊剂或无铅焊剂材质。
另外,一钝化层160形成于顶部含金属层130及导电结构132之上。开口162(图2B)及一系列重分布导孔164(图2B显示了三个示范性的重分布导孔)穿过钝化层160形成。导电垫142及144通过开口162形成连接。在一实施例中,导电垫142及导电结构132形成在顶部含金属层130。以导电材质填入上述的重分布导孔,形成一系列的重分布导孔插塞166。导电重分布结构172形成于钝化层160之上且与导电垫144及导电结构132经由一系列的重分布导孔插塞166连接。另一个钝化层180形成于钝化层160,导电重分布结构172,及导电垫144之上。最后,保护层190,例如聚酰亚胺层,形成于钝化层180之上。
在一些实施例中,导电重分布结构172也被称为重分布层(RDL),并且也是导电垫144的一延伸部分。导电重分布结构172及导电垫144可在同一工艺中以相同材质形成。在一实施例中,导电结构132与导电重分布结构172为金属材质,如铜或含铜合金;用来填充重分布导孔插塞166的材质与形成导电重分布结构172的材质相同;而导电垫142是以形成导电结构132的导电材质形成。在一些实施例中,导电垫144的形成是填入穿过钝化层160的开口以建立与导电垫142的电性连接,并使钝化层160得以延伸进入导电垫142与导电垫144的间隙。在一实施例中,导电垫142为铜材质,而导电垫144为铝铜合金。举例来说,导电垫144为含0.5%铜的铝铜合金。在其他实施例中,导电垫142及导电垫144可为相同或不同导电材质。另外,导电垫142及导电垫144具有能够在结构上支撑凸块下金属组件150的尺寸与形状。举例来说,在一些实施例中,导电垫142及144为宽度80-85微米之间的八角形。
导电结构132,导电重分布结构172,含金属层120a及120b,及导电垫142及144的形成是为了让基板110上一部分的电路及凸块结构150之间可以电性连接。虽然图1中只显示两个含金属层120a及120b,及一顶部含金属层130,一些实施例包括了少于或多于两个的含金属层及一个顶部含金属层。举例来说,一些特定实施例包括八个含金属层及一个顶部含金属层;其他的实施例包括六个含金属层及两个顶部含金属层。在一些实施例中,钝化层160及180包括氮化硅,并还可包括少量的氧化物及/或碳化物。除此之外,在其他实施例中,钝化层160及180可为相同或不同介电材质。
图2A~图2F显示了图1的半导体装置100的工艺剖面图。图2A中,一导电垫142及由该导电垫142延伸出的导电结构形成于一顶部含金属层130之中,且位于基板110与两个含金属层120a及120b之上。基板110上已形成电路。在图2B中,一介电层160形成于顶部含金属层130之上,及导电垫142及导电结构132之上。介电层160是用来当作钝化层,以保护其下结构。然后移除介电层160一部分以形成穿过该介电层160的开口162及重分布导孔164。为简化起见,图里只有显示三个重分布导孔164。在一些实施例中,重分布导孔164有可能多或少于三个。
在图2C中,形成多个填入重分布导孔164的重分布导孔插塞166,并且形成一导电重分布结构172于介电层160之上。导电重分布结构172通过重分布导孔插塞166与导电结构132连接。另外,填入开口162,形成一导电垫144于导电垫142的上方,且导电垫144通过开口162与导电垫142连接。在一实施例中,导电重分布结构172是导电垫144的一延伸部分。在图2D中,另一个被当作钝化层的介电层180形成于介电层160、导电垫144,及导电重分布结构172之上。在图2E中,接着在介电层180上形成一保护层190,然后形成一开口以暴露导电垫144的一部分。最后,在图2F中,在导电垫144上形成一凸块下金属组件150。
图3为一实施例中的半导体装置300的剖面图。半导体装置300与图1中的实施例相似,具有一已形成电路的基板310。两个含金属层320a及320b形成于基板310之上,而一顶部含金属层330形成于含金属层320a及320b之上。一导电结构332形成于顶部含金属层330之中,且通过含金属层320a及320b与基板310上至少一部分的电路作电性连接。两个导电垫342与344形成在含金属层320a及320b与半导体基板310上,并与导电垫332电性连接。在一些实施例中,导电结构332是导电垫342的一延伸部分,且被当作重分布层。一凸块结构350形成于导电垫342及344之上,且与导电垫342及344电性连接。
另外,一钝化层360形成于顶部含金属层330、导电垫342,及导电结构332之上。一开口362(图4B)穿过钝化层360形成。导电垫344形成于开口362之中及钝化层350之上。导电垫342及导电垫344通过开口362连接(图4C)。在一实施例中,导电结构332为顶部含金属层330之中的导电垫342的一延伸部分。最后,一保护层390,例如一聚酰亚胺层,形成于钝化层360及导电垫344之上(图4D)。
一实施例与图1中的实施例相似,其中导电结构332为金属材质,例如为铜或含铜合金。在一些实施例中,导电垫344的形成是填入穿过钝化层360的开口362以建立与导电垫342的电性连接,并使让钝化层360得以延伸进入导电垫342与导电垫344的间隙。在一实施例中,导电垫342为铜材质,而导电层344为掺有0.5%铜的铝铜合金。在其他实施例中,导电垫342及导电垫344可为同样或不同材质。另外,导电垫342及导电垫344具有能够在结构上支撑凸块下金属组件350的尺寸与形状。举例,在一些实施例中,导电垫342及344为宽度80-85微米之间的八角形。
导电结构332、含金属层320a及320b,及导电垫342及344的形成是为了让在基板310上的一部分的电路与凸块结构350作电性连接。含金属层320a及320b与顶部含金属层330只是示范说明用,在一些实施例中,有可能有多或少于两个含金属层及一顶部含金属层。另外,在一些实施例中,钝化层360包括氮化硅,也可能还包括少量的氧化物及/或碳化物。
图4A~图4E为图3的半导体装置300的工艺剖面图。在图4A中,一导电垫342及从导电垫342所延伸出来的一导电结构332形成于一顶部含金属层330之中,且位于基板310及两个含金属层320a及320b之上。导电垫342及导电结构332可同时形成。基板310上已形成电路。参照图4B,一介电层360形成于顶部含金属层330、导电垫342及导电结构332之上。介电层360为一钝化层,以保护其下结构。接着移除一部分的介电层360以形成穿过介电层360的一开口362。
参照图4C,导电垫344形成于导电垫342之上并通过开口362与导电垫342连接。参照图4D,在介电层360及一部分的导电垫344上形成一保护层390,此外,形成一开口以暴露导电垫344的一部分。最后,在图4E中,在导电垫344上形成一凸块下金属组件350。
图5为一实施例中一半导体装置500的剖面图。半导体装置500与图1中的实施例相似,具有一已形成电路的基板510。两个示范性的含金属层520a及520b形成于基板510之上,而一示范性的顶部含金属层530形成于含金属层520a及520b之上。一导电结构532在含金属层530之中形成,并通过含金属层520a及520b与基板510上至少一部分的电路作电性连接。两个导电垫542及544形成于含金属层520a及520b,及半导体基板510之上,并与导电结构532电性连接。在一些实施例中,导电结构532为导电垫542的一延伸部分,并且用来当作重分布层。一凸块结构550形成于导电垫542及544之上,并与导电垫542及544电性连接。
另外,一钝化层560形成于顶部含金属层530及导电结构532之上。一开口562(图6B)穿过钝化层560形成。导电垫542及导电垫544通过开口562而连接。在一实施例中,导电结构532为顶部含金属层530中导电垫542的一延伸部分。最后,另一钝化层580形成于钝化层560及导电垫544之上,且一保护层590,如一聚酰亚胺层,形成于钝化层580之上。
在一实施例中,导电结构532为金属材质,例如铜或含铜合金;而形成导电垫542的导电材质与形成导电结构532的导电材质相同。在一些实施例中,导电垫544的形成是填入穿过钝化层560的开口以建立与导电垫542的电性连接,并使钝化层560得以延伸进入导电垫542与导电垫544的间隙。在一实施例中,导电垫542为铜材质,而导电垫544为含0.5%铜的铝铜合金。在其他实施例中,导电垫542及导电垫544可为相同或不同的导电材质。除此之外,导电垫542与导电垫544具有能够在结构上支撑凸块下金属组件550的尺寸与形状。举例来说,在一些实施例中,导电垫542及544为宽度80-85微米之间的八角形。
导电结构532、含金属层520a及520b,及导电垫542及544的形成是为了让在基板510上的一部分的电路与凸块结构550作电性连接。含金属层520a及520b与顶部含金属层530只是示范说明用,在一些实施例中,可具有多于或少于两个含金属层及一顶部含金属层。另外,在一些实施例中,钝化层560及580可为相同或不同介电材质。举例来说,钝化层560及580可包括氮化硅,也可能还包括少量的氧化物及/或碳化物。
图6A~图6E为图5的半导体装置500的一工艺剖面图。在图6A中,一导电垫542及另一从导电垫542所延伸出来的导电垫532形成于顶部含金属层530之中,且位于基板510与两个含金属层520a及520b之上。导电垫542及导电结构532可同时形成。基板510上已形成电路。参照图6B,一介电层560形成于顶部含金属层530、导电垫542及导电结构532之上。介电层560为一钝化层,以保护其下结构。接着移除一部分的介电层560以形成穿过介电层560的一开口562。
参照图6C,导电垫544形成于导电垫542之上并通过开口562与导电垫542连接。参照图6D,另一用来当作钝化层的介电层580形成于介电层560及导电垫544之上。在图6E中,移除一部分的介电层580,接着,在介电层580之上形成一保护层590。最后,在图6F中,在导电垫544之上形成一凸块下金属组件550。
图7为一实施例中一半导体装置700的剖面图。该半导体装置700与图1中的实施例相似,具有一已形成电路的基板710。两个含金属层720a及720b形成于基板710之上,而两个顶部含金属层730a及730b形成于含金属层720a及720b之上。两个导电结构732及734分别形成于顶部含金属层730a及顶部含金属层730b之中。导电结构732及734是通过形成于一顶部介电层738的一系列导孔插塞连接。其中,导孔插塞是由利用导电材质填入顶部导孔736所形成。两个导电垫742及744形成于含金属层720a及720b,及半导体基板710之上,并与导电结构732及734的其中至少一个电性连接。一凸块结构750形成于导电垫742及744之上,并与导电垫742及744电性连接。
除此之外,顶部介电层738形成于导电结构732及导电垫742之上,及导电结构734及导电垫744之下。多个开口746穿过顶部介电层738形成,此外,导电垫742及导电垫744通过多个开口746连接。在一实施例中,只具有一个开口746;在其他实施例中,开口746形成一系列的导孔。导电结构734形成于顶部介电层738之上,及一钝化层760之下,其中该钝化层形成于顶部含金属层730a及730b,及导电结构734及导电垫744之上。最后,形成一保护层790,例如一聚酰亚胺层,于钝化层760及导电垫744之上。
导电结构732及导电垫742形成于顶部含金属层730a之中,而导电结构734及导电垫744形成于顶部金属层730b之中。导电结构732与导电垫742在顶部含金属层730a连接,而导电结构734与导电垫744在顶部含金属层730b连接。在其他实施例中,只有导电结构732及734的其中一个结构连接到相对应的导电垫742及744。在一些实施例中,导电结构732或734其中至少有一个分别是导电垫742或744的一延伸部分,且为一重分布层。在一特定的实施例中,导电结构732是导电垫742的一延伸部分,且被用来当作一重分布层,而导电结构734是导电垫744的一延伸部分,并且被用来当作另一重分布层。
在相似于图1里所呈现实施例的一实施例中,导电结构732及734为同样材质,例如铜或含铜合金。在一些实施例中,导电垫744的形成是先由填入穿过顶部介电层738形成的开口746以建立与导电垫742的电性连接,接着导电垫744与导电结构734同时形成。在一实施例中,导电垫742及744为铜材质。在其他实施例中,导电垫742及导电垫744可为相同或不同材质。除此之外,导电垫742和导电垫744具有能够在结构上支撑凸块下金属组件750的尺寸与形状。
导电结构732及734,含金属层720a及720b,及导电垫742及744的形成让基板710上的一部分电路可以跟凸块结构750电性连接。含金属层720a及720b及顶部含金属层730a及730b只是示范说明用,在一些实施例中,可以包括多于或少于两个的含金属层及两个顶部含金属层。另外,在一些实施例中,钝化层760包括氮化硅,也还可包括少量的氧化物及/或碳化物。
图8A~图8D为图7的半导体装置700的工艺剖面图。在图8A中,一导电垫742及从导电垫742所延伸出来的一导电结构732形成于顶部含金属层730a之中,且位于基板710及两个含金属层720a及720b之上。导电垫742及导电结构732可同时形成。基板710上已形成电路。接着,形成一介电层738于顶部含金属层730a及导电垫及导电结构732之上。在此,介电层738是用来当作一顶部介电层,以分离顶部含金属层730a及另外的顶部含金属层730b。一部分的介电层738被移除以形成穿过介电层738的多个开口(导孔)746及顶部导孔736。以一导电材质填入顶部导孔736,且形成一导电结构734于导电结构732之上,其中导电结构734通过顶部导孔736与导电结构732连接,以一导电材质填入多个开口746,且形成导电垫744于导电垫742之上,其中导电垫744通过多个开口746与导电垫742连接。除此之外,导电垫744及从导电垫744延伸的导电结构734形成于顶部含金属层730b之中,且位于介电层738之上。
参照图8B,形成另一介电层760在导电垫744及导电结构734之上。介电层760是用来当作一钝化层以保护其下结构。接着,移除一部分的介电层760,且进一步在介电层760之上形成一保护层790,除此之外,形成一开口以暴露导电垫744的一部分。最后,在图8D中,在导电垫744上形成一凸块下金属组件750。
图9是在一实施例中半导体装置900的剖面图。与图1中描绘的实施例相似的是,该半导体装置900具有一已形成电路的基板910。两个含金属层920a及920b形成于基板910之上,而两个顶部含金属层930形成于含金属层920a及920b之上。一导电结构932形成于顶部含金属层930之中,且通过含金属层920a及920b与基板910上至少一部分的电路形成电性连接。三个导电垫942、944及946,形成于含金属层920a及920b及半导体基板950之上,且与导电结构932电性连接。一凸块结构950形成于导电垫942、944及946之上,且与导电垫942、944及946电性连接。
除此之外,一钝化层960形成于顶部含金属层930及导电结构932之上,一开口962(图10B)及一系列的重分布导孔964(图10B,三个示范说明用的重分布导孔如附图)穿过钝化层960形成。导电垫942(较下层垫)及导电垫944(中层垫)通过开口962连接。在一实施例中,导电垫942及从导电垫942所延伸出来的导电结构932形成于顶部含金属层930之中。以一导电材质填入一系列的重分布导孔,形成一系列的重分布导孔插塞966。一导电重分布结构972形成于钝化层960之上,与导电垫944连接,并通过一系列的重分布导孔插塞966与导电结构932连接。
除此之外,另一个钝化层980形成于钝化层960、导电重分布结构972,及导电垫944之上。另一导电垫946(较上方垫)接着形成于凸块结构950之下及导电垫944之上,且通过一穿过于钝化层980的开口与导电垫944连接。最后,一保护层990,例如一聚酰亚胺层,形成于该钝化层980之上。
在一些实施例中,导电重分布结构972也被称作重分布层,并且是导电垫944的一延伸部分。在一实施例中,导电结构932及导电重分布结构972为金属材质,例如铜或含铜合金;用来填入重分布导孔插塞966的导电材质与用来填入导电重分布结构972的材质相同;形成导电垫942的材质与形成导电结构932的导电材质相同。在一些实施例中,导电垫944的形成是填入穿过钝化层960的开口以建立与导电垫942的电性连接,并使钝化层960得以延伸进入导电垫942与导电垫944的间隙。导电垫946的形成与导电垫944的形成相似,是为了使钝化层980可延伸进入导电垫944及导电垫946的间隙。在一实施例中,导电垫942为铜材质,且导电垫944及946为含0.5%铜的铝铜合金。在其他的实施例中,导电垫942、944,及946可为相同或不同的导电材质。除此之外,导电垫942、944及946具有能够在结构上支撑凸块下金属组件950的尺寸与形状。举例来说,在一些实施例中,导电垫942、944,及946为宽度80-85微米之间的八角形。
导电结构932及972,含金属层920a及920b,及导电垫942、944及946的形成,是为了让基板910上一部分的电路与凸块结构950作电性连接。
图10A-图10F显示图9的半导体装置900的一工艺剖面图。在图10A中,导电垫942及导电结构932同时于顶部含金属层930之中形成,且位于基板910及两个含金属层920a及920b之上。在一些实施例中,导电结构932是导电垫942的一延伸部分,且被当作是一重分布层。基板910上已形成电路。参照图10B,一介电层960形成于顶部含金属层930、导电垫942,及导电结构932之上。该介电层960被用来当作一钝化层以保护其下结构。接着,移除介电层960的一部分以形成穿过介电层960的一开口962及三个重分布导孔964。在一些实施例中,有可能具有多或少于三个重分布导孔964。
参照图10C,形成多个填入重分布导孔964的重分布导孔插塞966,并且形成导电重分布结构972于介电层960之上。导电重分布结构972通过重分布导孔插塞966连接到导电结构932。除此之外,填入开口962,形成一导电垫944于导电垫942之上,且通过开口964与导电垫942连接。在一实施例中,导电重分布结构972为导电垫944的一延伸部分。参照图10D,被当作钝化层的另一介电层980形成于介电层960、导电垫944,及导电重分布结构972之上。除此之外,一第三导电垫946形成于介电层980之上。导电垫946通过一穿过介电层980的开口连接到导电垫944。在图10E中,接着在介电层980及导电垫946之上形成一保护层990,且形成一开口以暴露导电垫946的一部分。最后,在图10F中,在导电垫946上形成一凸块下金属组件950。
图11为一实施例中一半导体装置1100的剖面图。与图7中描绘的实施例相似的是,该半导体装置1100有一已形成电路的基板1110。两个含金属层1120a及1120b形成于基板1110之上,而两个顶部含金属层1130a及1130b形成于含金属层1120a及1120b之上。两个导电结构1132及1134分别形成于顶部含金属层1130a及1130b之中。导电结构1132及1134通过在一顶部介电层1138之中一系列的顶部导孔插塞相互连接,其中顶部导孔插塞是由以一导电材质填补一系列顶部导孔1136形成。三个导电垫1142、1144及1146形成于含金属层1120a及1120b,及半导体基板1110之上,并与导电结构1132及1134的其中至少一个电性连接。一凸块结构1150形成于导电垫1142、1144及1146之上,并与导电垫1142、1144及1146电性连接。
再者,顶部介电层1138形成于导电结构1132及导电垫1142之上,且位于导电结构1134及导电垫1144之下。多个开口1148穿过顶部介电层1138形成,而导电垫1142(底层垫)通过开口1148与导电垫1144(中间垫)连接。在一实施例中,只具有一开口1148;在其他实施例中,多个开口1148形成为导孔。导电结构1134形成于顶部介电层1138之上,及一钝化层1160之下。其中该钝化层形成于顶部含金属层1130a及1130b,及导电结构1132及1134上方。
一钝化层1160形成于顶部含金属层1130b及导电结构1134之上。一开口1162(图12B)穿过钝化层1160形成。导电垫1146(顶部垫)及导电垫1144通过开1162连接。最后,一保护层1190,例如一聚酰亚胺层,形成于钝化层1160及导电垫1146之上。在一些实施例中,钝化层1160延伸进入导电垫1144及导电垫1146的间隙。
导电结构1132及导电垫1142形成于顶部含金属层1130a之中,而导电结构1134及导电垫1144形成于顶部含金属层1130b之中。导电结构1132与导电垫1142在顶部含金属层1130a之中连接,而导电结构1134与导电垫1144在顶部含金属层1130b之中连接。在其他实施例中,在导电结构1132及1134中只有一个与对应的导电垫1142及1144连接。在一些实施例中,导电结构1132或1134之中至少有一个是分别对应的导电垫1142或1144的一延伸部分,且被用来当作一重分布层。在一特定实施例中,导电结构1132是导电垫1142的一延伸部分,且被当成一重分布层,而导电结构1134为导电垫1144的一延伸部分,且被当成另一重分布层。
一实施例与图7中的实施例相似,其中导电结构1132及1134为金属材质,例如为铜或含铜合金。在一些实施例中,导电垫1144的形成是先由填入穿过顶部介电层1138的开1146以建立与导电垫1142的电性连接,接着导电垫1144与导电结构1134同时形成。在一实施例中,导电垫1142及1144为铜材质,而导电垫1146为含0.5%的铝铜合金。在一些实施例中,导电垫1142、1144,及1146可为相同或不同导电材质,除此之外,导电垫1142、1144,及1146具有能够在结构上支撑凸块下金属组件1150的尺寸与形状。
导电结构1132及1134、含金属层1120a及1120b,及导电垫1142、1144及1146的形成是为了让在基板1110上的一部分的电路与凸块结构1150作电性连接。含金属层1120a及1120b,及顶部含金属层1130a及1130b仅供示范说明用,在一些实施例中,可具有多于或少于两个含金属层及两个顶部含金属层。除此之外,在一些实施例中,钝化层1160包括氮化硅,也还可包括少量的氧化物及/或碳化物。
图12A-图12E显示图11的半导体装置1100的一工艺剖面图。在图12A中,一导电垫1142及从导电垫1142延伸出的一导电结构1132形成于一顶部含金属层1130之中,且位于基板1110及两个含金属层1120a及1120b之上。导电垫1142及一导电结构1132可同时形成。基板1110上已形成电路。接着一介电层1138形成于顶部含金属层1130a之上,且位于导电垫1142及导电结构1132之上。介电层1138是用来当作一顶部介电层以分离顶部含金属层1130a与另一顶部含金属层1130b。一部分的介电层1138被移除以形成穿过介电层1138的多个开口1148及多个顶部导孔1136。以一导电材质填入多个顶部导孔1136,且在其上形成一导电结构1134,导电结构1134通过顶部导孔1136连接到导电结构1132,以一导电材质填入多个开口1148,且在导电垫1142上形成一导电垫1144,导电垫1144通过开口1148与导电垫1142连接。除此之外,在一些实施例中,导电垫1144及从导电垫1132延伸出的导电结构1134同时形成于介电层1138之中及顶部含金属层1130b之上。
参照图12B,另一介电层1160形成于导电垫1144及导电结构1134之上。介电层1160被用来当作一钝化层,以保护其下结构。接着,移除介电层1160的一部分以形成一另外开口1162。参照图12C,填入开口1162,而一导电垫1146形成于导电垫1144之上,且导电垫1146通过开口1162与导电垫1144连接。在图12D中,进一步在介电层1160及导电垫1146上形成一保护层1190,形成一开口以暴露导电垫1146的一部分。最后,在图12E中,在导电垫1146之上形成一凸块下金属组件。
此处公开了半导体装置各种不同的实施例。具有两个或以上导电垫的半导体装置可保护避免金属间介电层产生接合面剥离,或其他因凸块结构应力与应变或封装过程引起的缺陷。所公开的特定实施例与附图并不是最详尽的。虽然此公开只描述了三个导电垫,但可以使用更多的导电垫,以进一步增强凸块结构在结构上的支撑以及封装过程。因此可在更多导电垫所带来的好处,与更多晶片处理步骤及芯片翘曲所引起的更高内应力所带来的坏处之中取舍,并找到一个恰当的平衡点。
此关于示范说明用的实施例叙述应与相对应的附图一起阅读,因这些附图被视为是整个叙述的一部分。在叙述里相关的术语,例如较下方、较上方、水平、垂直、之上、之下、上、下、顶部、最下方、以及其他衍生词(例:水平地、向下地、向上地等等)应可被理解成有关当时描述或正在讨论的附图的方向。这些相关词是为了描述的便利,并不需要装置在一特定方向被建构或被使用。有关相连或相接,以及其他同类词,例如连接,内连接,除非特别叙述,皆是指结构之间彼此直接或通过中间结构间接被稳固或附着的关系,并可包括固定式或可动式的结合或关系。
虽然本发明已以多个较佳实施例公开如上,然其并非用以限定本发明,任何所属技术领域中普通技术人员,在不脱离本发明的精神和范围内,当可作任意的更动与润饰,因此本发明的保护范围当视所附的权利要求所界定的范围为准。
Claims (10)
1.一种半导体装置,包括:
一基板;
至少两个导电垫,形成于该基板上,其中一个导电垫形成于另一个之上,且一重分布层延伸至其中至少一个导电垫;及
一凸块结构,形成于所述多个导电垫之上,并且与所述多个导电垫电性连接。
2.如权利要求1所述的半导体装置,还包括一介电层,延伸进入该至少两个导电垫的一第一导电垫与一第二导电垫的间隙。
3.如权利要求1所述的半导体装置,其中该凸块结构包括:
一金属柱,形成于所述多个导电垫之上;
一金属膜,形成于该金属柱之上;及
一盖层,形成于该金属膜之上。
4.如权利要求1所述的半导体装置,其中该至少两个导电垫包括一第一导电垫及一第二导电垫,而该第二导电垫形成于该第一导电垫之上,并且该第一导电垫与该第二导电垫其中之一具有该重分布层。
5.一种半导体装置,包括:
一基板;
三个导电垫,以一导电垫形成于另一导电垫之上的形式形成于该基板上,其中一重分布层延伸至该至少一个导电垫;及
一凸块结构,形成于所述多个导电垫之上,并与所述多个导电垫电性连接。
6.如权利要求5所述的半导体装置,其中该重分布层延伸至一中间导电垫。
7.如权利要求5所述的半导体装置,其中一中间导电垫包括铜,一顶部导电垫包括铜,而一最下方导电垫包括一铝铜合金。
8.一种半导体装置的制造方法,包括:
形成一第一导电垫在一基板之上;
形成一第二导电垫在该第一导电垫之上;
当形成该第一导电垫或第二导电垫时,形成一重分布层做为该第一导电垫或第二导电垫的一延伸部分;及
形成一凸块结构在该第二导电垫之上。
9.如权利要求8所述的半导体装置的制造方法,其中该重分布层在形成该第一导电垫时形成,并且还包括另一重分布层在形成该第二导电垫时形成。
10.如权利要求8所述的半导体装置的制造方法,还包括:
在该凸块结构形成前,在该第二导电垫之上形成一第三导电垫,其中该重分布层在形成该第二导电垫时形成。
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