CN101281893A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN101281893A
CN101281893A CNA2008100889477A CN200810088947A CN101281893A CN 101281893 A CN101281893 A CN 101281893A CN A2008100889477 A CNA2008100889477 A CN A2008100889477A CN 200810088947 A CN200810088947 A CN 200810088947A CN 101281893 A CN101281893 A CN 101281893A
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wiring layer
mentioned
interlayer dielectric
layer
semiconductor device
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CN101281893B (zh
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森川成洋
稻叶裕一
后藤祐治
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Sanyo Electric Co Ltd
System Solutions Co Ltd
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Sanyo Semiconductor Co Ltd
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Abstract

本发明提供一种半导体装置，该半导体装置具有可以缓和施加在焊盘上的机械应力的结构。在第2层间绝缘膜(9)上以覆盖第3配线层(11)的方式形成有第3层间绝缘膜(13)，该第3层间绝缘膜(13)具有导通孔(12)。在导通孔(12)内形成有第3导电层(14)。第3层间绝缘膜(13)是由平面形状为六边形的多个柱状层间绝缘膜(13a)集合而构成的。而且，以包围各柱状层间绝缘膜(13a)周围的方式形成有导通孔(12)和第3导电层(14)。形成了通过第3导电层(14)与第3配线层(11)电连接的第4配线层(15)。第4配线层(15)是本实施方式中的顶层配线层，为起到焊盘作用的层。

Description

半导体装置
技术领域
本发明涉及一种半导体装置，特别是涉及一种具有夹着层间绝缘膜形成有多个配线层的多层配线结构的半导体装置。
背景技术
在IC芯片上设置有焊盘(bonding pad)(外部端子)，该焊盘用于向在IC芯片内形成的许多半导体元件供给规定的电压(电源电压、接地电压)、各种电信号，或用于向外部输出各种电信号。
图3是表示以往的半导体装置的形成有焊盘的区域的概略剖视图。在半导体基板100的表面上形成有由晶体管、电容器等许多半导体元件构成的设备元件101。另外，在半导体基板100的表面上隔着氧化硅膜等绝缘膜103形成有第1配线层102，该第1配线层102通过未图示的配线与设备元件101电连接。
在绝缘膜103上以覆盖第1配线层102的方式形成有第1层间绝缘膜105，该第1层间绝缘膜105具有导通孔104。在导通孔104内形成有由钨等形成的导电层106。在第1层间绝缘膜105上形成有第2配线层107，该配线层107通过导电层106与第1配线层102电连接。以下同样地，在第1层间绝缘膜105上形成有第2层间绝缘膜108，在第2层间绝缘膜108上形成有第3配线层109和第3层间绝缘膜110，在第3层间绝缘膜110上形成有第4配线层111。该第4配线层111起到焊盘的作用。为了缩小芯片尺寸，第4配线层111配置在与设备元件101重叠的区域。在第3层间绝缘膜110上形成有保护膜113，该保护膜113在第4配线层111之上具有焊盘开口部112。
另外，在进行探针测试、引线结合工序时，测针或导线与从焊盘开口112露出的第4配线层111接触。在进行探针测试时，利用由由钨、镍合金等形成的测针(探针)的推压，在第4配线层111的下方集中较大的机械应力。另外，在进行引线结合工序时也是，由于超声波能量、导线的影响导致在第4配线层111的下方集中较大的机械应力。因此，有时会在第4配线层111的下方的第3层间绝缘膜110中产生裂纹114。
而且，有时裂纹114到达第3层间绝缘膜110下方的层间绝缘膜(第2层间绝缘膜108、第1层间绝缘膜105)、配线层(第3配线层109、第2配线层107、第1配线层102)。这样，水分等腐蚀物质通过裂纹114浸入到内部，因此，裂纹114成为引起抗金属迁移性变差、配线间短路等不良情况的原因。
因此，用于抑制由裂纹114所引起的可靠性变差的技术提出了如下的技术。如图4和图5所示，该技术的结构是：将与第4配线层111大致相同尺寸的第3配线层115配置成与第4配线层111重叠，另外，将第4配线层111和第3配线层115电连接起来的导电层116以环状仅配置在保护膜113的下方。这样，在具有第3配线层115和环状导电层116的结构中，即使产生了裂纹114，也可由第3配线层115阻止裂纹114向下方传播。另外，图4是表示图5的Y-Y剖视图，在图5中，为了方便说明，省略了第4配线层111、导电层116、保护膜113以外的结构。
另外，如图6和图7所示，提出了如下结构：在与第4配线层111重叠的大致整面上配置许多环状的导电层117，该环状的导电层117电连接第4配线层111和第3配线层115。这样，配置了许多环状导电层117的结构可由第3配线层115阻止裂纹的向下方传播，并且由该环状的导电层117抑制在第3层间绝缘膜110中产生的裂纹114向半导体基板100的面方向扩展。另外，图6是表示图7的Z-Z剖视图，在图7，为了方便说明，省略了第4配线层111、导电层117以外的结构。
本发明的相关技术例如记载于以下的专利文献中。
专利文献1：日本特开平06-196525号公报
可知：若进行探针测试，在上述以往的结构中，施加在焊盘上的机械应力没能被第3配线层115充分缓和。
近年来，为了对应芯片尺寸的微细化，使焊盘形成为与设备元件的形成区域重叠。因此，当第3配线层115不能充分缓和施加在焊盘上的机械应力时，该机械应力会到达设备元件。而且，构成设备元件的半导体元件、与它们相连接的配线逐年微细化，若机械应力到达设备元件，则容易产生破损，电特性(例如：晶体管的阈值)会变动。
发明内容
本发明是鉴于上述问题作出的，其主要特征如下。即，本发明的半导体装置的特征在于，具有半导体基板、配线层、层间绝缘膜、导电层和顶层配线层，该配线层形成在上述半导体基板上表面上，该层间绝缘膜形成为覆盖上述配线层，该导电层形成在上述层间绝缘膜内、并且与上述配线层电连接，该顶层配线层形成在上述层间绝缘膜上，并且通过上述导电层与上述配线层电连接；上述层间绝缘膜由以蜂窝状配置多个平面形状为六边形的柱状层间绝缘膜而成的结构构成，上述导电层形成为包围上述柱状层间绝缘膜的周围。
在本发明中，由柱状层间绝缘膜和导电层的结构(蜂窝结构)缓和施加在焊盘上的机械应力。
附图说明
图1是说明本发明的实施方式的半导体装置的剖视图。
图2是说明本发明的实施方式的半导体装置的俯视图。
图3是说明以往的半导体装置的剖视图。
图4是说明以往的半导体装置的剖视图。
图5是说明以往的半导体装置的俯视图。
图6是说明以往的半导体装置的剖视图。
图7是说明以往的半导体装置的俯视图。
具体实施方式
参照附图对本发明的实施方式进行说明。图1是表示本发明的实施方式的半导体装置的概略剖视图，图2是其俯视图。图1相当于图2的X-X剖面。另外，为了方便说明，仅图示了1个形成有焊盘的区域，而省略了半导体基板上的其他区域(内部电路区域、其他形成有焊盘的区域)的图示。
在由硅等形成的半导体基板1的表面上形成有由晶体管、电容器等许多半导体元件形成的设备元件2。设备元件2构成例如逻辑电路、驱动(driver)电路。另外，在半导体基板1的表面上隔着氧化硅膜等绝缘膜4形成有第1配线层3，该第1配线层3与设备元件2或其他半导体元件电连接。另外，第1配线层3为例如由铝形成的配线层，后述的第2配线层8、第3配线层11和第4配线层15也同样。
在绝缘膜4上以覆盖第1配线层3的方式形成有第1层间绝缘膜6，该第1层间绝缘膜6具有导通孔5a。在导通孔5a内形成有第1导电层7，该第1导电层7例如由钨或铝等形成。另外，虽然未图示，但在第1层间绝缘膜6和第1导电层7之间形成有屏障金属(barrier metal)层(例如：钨化钛(TiW)层、氮化钛(TiN)层)。以下，第2层间绝缘膜9和第2导电层10之间、第3层间绝缘膜13和第3导电层14之间也同样形成有屏障金属层。
在第1层间绝缘膜6上形成有第2配线层8，该第2配线层8通过第1导电层7与第1配线层3电连接。另外，在第1层间绝缘膜6上以覆盖第2配线层8的方式形成有第2层间绝缘膜9，该第2层间绝缘膜9具有导通孔5b，在导通孔5b中形成有第2导电层10。
在第2层间绝缘膜9上形成有第3配线层11，该第3配线层11通过第2导电层10与第2配线层8电连接。优选是第3配线层11配置在与第4配线层15重叠的位置，第3配线层11的图案面积形成为尺寸比保护膜17的开口部(后述的焊盘开口部16)的尺寸大。采用该结构的原因是，第3配线层11介于第2配线层8和第4配线层15之间而具有电连接的功能，并且具有缓和施加在第4配线层15的负荷而抑制裂纹向下方传播的作为阻止配线层的功能。在第2层间绝缘膜9上以覆盖第3配线层11的方式形成有第3层间绝缘膜13，该第3层间绝缘膜13具有导通孔12，在导通孔12中形成有第3导电层14。
在第3层间绝缘膜13上形成有第4配线层15，该第4配线层15通过第3导电层14与第3配线层11电连接。第4配线层15为本实施方式中的顶层配线层，为起到焊盘作用的层。因此，第4配线层15在引线结合时与金属线连接，在探针测试时与探针接触。从垂直于半导体基板1的方向观察，第4配线层15与设备元件2、它们的配线重叠，缩小了半导体装置的布局面积而实现小型化。在第3层间绝缘膜13上形成保护膜17，该保护膜17在第4配线层15之上具有焊盘开口部16。
在此，本实施方式的特征在于导通孔12、第3层间绝缘膜13和第3导电层14的结构。即，如图2所示，本实施方式的第3层间绝缘膜13是将平面形状为正六边形的多个柱状层间绝缘膜13a在纵向、横向、倾斜方向上以一定的间距有规则地集合起来而构成的。而且，以包围各柱状层间绝缘膜13a的周围的方式形成了导通孔12和第3导电层14。若设柱状层间绝缘膜13a的宽度为X1，第3导电层14的宽度为X2，则例如使X1形成为X2的2倍左右。另外，由于柱状层间绝缘膜13a集合而形成为蜂窝状，因此，以下称这样的第3层间绝缘膜13和第3导电层14的结构为蜂窝(honeycomb)结构。
例如通过以下的制造工艺形成该蜂窝结构。首先，在第2层间绝缘膜9和第3配线层11上堆积氧化硅膜等层间绝缘膜，再涂布保护层(rasist)，该保护层用于将该层间绝缘膜布置成蜂窝状。接着，以该保护层为掩膜对层间绝缘膜进行布图，形成柱状层间绝缘膜13a和导通孔12。在此，使X1为X2的2倍左右时，保护层设计为使X1为X2的3倍左右。接着，在导通孔12内埋入金属材料钨、铝，接着，通过由化学机械研磨(CMP)除去附着在导通孔12内以外的金属材料，从而形成第3导电层14，制成了本实施方式的蜂窝结构。
另外，也可以通过在导通孔12中埋入铝、且在第3层间绝缘膜13上堆积该铝而在同一工序中形成第3导电层14和第4配线层15这两者，另外，也可以通过在导通孔12中埋入钨而形成第3导电层14，在其后的别的工序中形成由铝构成的第4配线层15。
接着，举出具体例子进行说明上述实施方式的半导体装置的结构(以下称为第1结构)的探针测试中的裂纹产生率。在此，使用探针卡A和探针卡B这2种探针卡，测定第4配线层15和第3配线层11之间的裂纹产生率(4M-3M裂纹：NG率)、以及第3配线层11和第2配线层8之间的裂纹产生率(3M-2M裂纹：NG率)。另外，在半导体装置的制造工序中进行的通常的探针测试中，过驱动(overdrive)量(针插的强度)为30μm左右，但，在本次的试验中在比通常高的过驱动量(65μm～105μm)下分成5个阶段，在各过驱动量下进行各计3回的针插，调查由第1结构对机械应力的缓和达到什么程度(参照表1的评价结果)。另外，与探针卡B相比，探针卡A在测定时针的柔韧性较大。
表1是说明本发明的实施方式的半导体装置的裂纹产生率的表。
另外，将第1结构的测定结果作为比较例，对已经使用图4和图5说明了的半导体装置的结构(第2结构)、和已经使用图6和图7说明了的半导体装置的结构(第3结构)也进行与第1结构同样的试验。
如由表1所示的评价结果判定的那样，在使用了探针卡A时，对于第4配线层15和第3配线层11之间的裂纹产生率(4M-3M裂纹：NG率)而言，第2结构为94.1％～100％，第3结构为51.5％～100％，与此相对，第1结构为58.8％～100％。另外，在使用了探针卡B时，对该裂纹产生率而言，第2结构为96.1％～100％，第3结构为93.1％～100％，与此相对，第1结构为84.3％～100％。由以上可知，与第2结构相比，第1结构和第3结构较大地减少了在第4配线层15和第3配线层11之间的裂纹产生率。
另外，考虑到半导体装置的可靠性，重要的是机械应力是否到达半导体元件。从该观点从发，探讨第3配线层11和第2配线层8之间的裂纹产生率。
如由表1所示的评价结果判定的那样，在使用了探针卡A时，对于第3配线层11和第2配线层8之间的裂纹产生率(3M-2M裂纹：NG率)而言，第2结构为0.00％～0.47％，第3结构为0.00％～0.58％，任何一种结构都在过驱动量为105μm时产生了裂纹。与此相对，第1结构在包含过驱动量为105μm时的所有过驱动量下其裂纹产生率为0.00％。从该结果可知，对缓和机械应力向第3配线层11下方传播的程度而言，第1结构比其他结构高。
另外，使用了探针卡B时，对于该裂纹产生率而言，第2结构为0.00％～3.02％，第3结构为0.00％～1.40％，任何一种结构都在过驱动量为95μm和105μm时产生了裂纹。与此相对，第1结构在到过驱动量为95μm之前的裂纹产生率为0.00％，即使为105μm的过驱动量也可将裂纹产生率抑制到仅为0.23％。过驱动量为105μm时，与第2结构相比，第1结构的裂纹产生率约为其15分之1；与第3结构相比，第1结构的裂纹产生率约为其7分之1。从该结果可知，对于缓和机械应力向第3配线层11下方传播的程度而言，第1结构比其他结构高得多。
以上，由探针测试的结果可知，第1结构为机械应力难以传播到第2配线层8和第3配线层11的下方、且更难以到达半导体元件的结构。另外，还确认了在引线结合工序后和模制树脂密封后也是，第1结构难以产生裂纹，机械应力难以传播到第2配线层8和第3配线层11的下方。
这样，采用本实施方式的结构，不仅在探针测试时，而且在引线结合工序、形成凸块(bump)电极的工序、密封工序等时，也可由蜂窝结构(第3层间绝缘膜13和第3导电层11)缓和施加在焊盘(第4配线层15)的机械应力。因此，可以抑制物理损伤向该蜂窝结构的下方传播，提高半导体装置的可靠性。
另外，各柱状层间绝缘膜13a通过第3导电层11相互分开，因此，成为如下结构：即使假定在第3层间绝缘膜13a的一部分产生裂纹，裂纹也难以传播到其他第3层间绝缘膜13a。
另外，不言而喻，本发明不限于上述实施方式，在不脱离其主旨的范围内可进行变更。
例如，也可将本发明应用于4层以上多层配线结构，只要是2层以上的多层配线结构就可应用本发明。即，只要由上述柱状层间绝缘膜构成在最上层的配线层(焊盘)和最下层的配线层之间形成的多层层间绝缘膜的至少1层层间绝缘膜，且将导电层形成为包围各柱状层间绝缘膜的周围即可。另外，在图2中，第4配线层15或第3配线层11的俯视形状为正方形，但也可以为其他的俯视形状(例如长方形或三角形等)。本发明作为缓和施加在焊盘上的机械应力的技术，可广泛应用于具有多层配线结构的半导体装置。
Figure A20081008894700121

Claims (4)

1.一种半导体装置，其特征在于，
该半导体装置包括半导体基板、配线层、层间绝缘膜、导电层和顶层配线层，该配线层形成在上述半导体基板的表面上，该层间绝缘膜形成为覆盖上述配线层，该导电层形成在上述层间绝缘膜内、并且与上述配线层电连接，该顶层配线层形成在上述层间绝缘膜上，并且通过上述导电层与上述配线层电连接；
上述层间绝缘膜由以蜂窝状配置多个平面形状为六边形的柱状层间绝缘膜而成的结构构成；
上述导电层形成为包围上述柱状层间绝缘膜的周围。
2.根据权利要求1所述的半导体装置，其特征在于，
上述半导体装置具有设备元件、和形成在上述配线层之下的与上述层间绝缘膜不同的层间绝缘膜，该设备元件形成在上述半导体基板的表面上；
上述设备元件和上述顶层配线层重叠配置。
3.根据权利要求1或2所述的半导体装置，其特征在于，
上述顶层配线层是焊盘。
4.根据权利要求1～3中任一项所述的半导体装置，其特征在于，
上述半导体装置具有保护膜，该保护膜具有使上述顶层配线层的一部分露出的开口部；
上述配线层的图案面积形成为大于上述开口部的尺寸。
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TW200845252A (en) 2008-11-16
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US7741724B2 (en) 2010-06-22
CN101281893B (zh) 2010-06-16

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