JP4579621B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4579621B2 JP4579621B2 JP2004246549A JP2004246549A JP4579621B2 JP 4579621 B2 JP4579621 B2 JP 4579621B2 JP 2004246549 A JP2004246549 A JP 2004246549A JP 2004246549 A JP2004246549 A JP 2004246549A JP 4579621 B2 JP4579621 B2 JP 4579621B2
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- pad
- insulating film
- metal pattern
- wiring
- semiconductor device
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- H—ELECTRICITY
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
- H01L2224/05096—Uniform arrangement, i.e. array
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
102 拡散層
103 素子分離絶縁膜
104 ゲート絶縁膜
105 ゲート電極
106 サイドウォール
107 第1の層間絶縁膜
108 第1のビア
109 第1の配線
110 第2の層間絶縁膜
111 第2のビア
112 第2の配線
113 第3の層間絶縁膜
114 第3のビア
115 第3の配線
116 第1のパッド
117(117a、117b) 第4の層間絶縁膜
117c 第1の開口部
117d 第2の開口部
118 第4のビア
119 ネットワークビア
119a、119b ビア
120 第4の配線
121 第2のパッド
122 保護膜
122a パッド開口部
4A 進入方向
Rv 半径
Tw 膜厚
L1 センターライン
P1 交差点
Rh 距離
Claims (3)
- 半導体基板上に形成された第1の絶縁膜と、前記第1の絶縁膜の上に形成された第1の金属パターンと、前記第1の金属パターンの上に形成された第2の絶縁膜と、前記第2の絶縁膜の上に形成されたパッドである第2の金属パターンと、前記第2の絶縁膜中に形成された、前記第1の金属パターンと前記第2の金属パターンとを接続する第3の金属パターンとを備え、
前記第3の金属パターンは、ハニカム構造を有する連続した1つの構造体であり、
前記第3の金属パターンを構成する金属は、タングステンであり、
前記タングステンの結晶配向主軸は、前記半導体基板の主面と平行であり、前記結晶配向主軸は<110>軸であり、その方位分布は、前記半導体基板の主面と平行な面内において一様であることを特徴とする半導体装置。 - 前記第1の金属パターンを構成する金属は、アルミニウム又は銅であることを特徴とする請求項1に記載の半導体装置。
- 前記第2の金属パターンを構成する金属は、アルミニウム又は銅であることを特徴とする請求項1に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004246549A JP4579621B2 (ja) | 2003-09-26 | 2004-08-26 | 半導体装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003335267 | 2003-09-26 | ||
JP2004246549A JP4579621B2 (ja) | 2003-09-26 | 2004-08-26 | 半導体装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008174485A Division JP4630919B2 (ja) | 2003-09-26 | 2008-07-03 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005123587A JP2005123587A (ja) | 2005-05-12 |
JP4579621B2 true JP4579621B2 (ja) | 2010-11-10 |
Family
ID=34622078
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004246549A Expired - Fee Related JP4579621B2 (ja) | 2003-09-26 | 2004-08-26 | 半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP4579621B2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007005536A (ja) * | 2005-06-23 | 2007-01-11 | Renesas Technology Corp | 半導体装置 |
JP2007019128A (ja) * | 2005-07-06 | 2007-01-25 | Sony Corp | 半導体装置 |
KR100784889B1 (ko) | 2005-11-29 | 2007-12-11 | 주식회사 하이닉스반도체 | 프로빙 패드 제어 장치 및 방법 |
JP2008258258A (ja) * | 2007-04-02 | 2008-10-23 | Sanyo Electric Co Ltd | 半導体装置 |
JP5329068B2 (ja) * | 2007-10-22 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US10038025B2 (en) | 2015-12-29 | 2018-07-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Via support structure under pad areas for BSI bondability improvement |
JP6623824B2 (ja) * | 2016-02-23 | 2019-12-25 | 株式会社デンソー | 半導体装置およびその製造方法 |
US20220367554A1 (en) * | 2021-05-17 | 2022-11-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bond pad structure with high via density |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1154544A (ja) * | 1997-05-01 | 1999-02-26 | Texas Instr Inc <Ti> | ボンド・パッドを増強するシステムおよび方法 |
JP2000195866A (ja) * | 1998-12-28 | 2000-07-14 | Samsung Electronics Co Ltd | 半導体素子のボンディングパッド構造及びその製造方法 |
JP2000195896A (ja) * | 1998-12-25 | 2000-07-14 | Nec Corp | 半導体装置 |
JP2001085465A (ja) * | 1999-09-16 | 2001-03-30 | Matsushita Electronics Industry Corp | 半導体装置 |
JP2002016069A (ja) * | 2000-06-29 | 2002-01-18 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2002134509A (ja) * | 2000-08-31 | 2002-05-10 | Texas Instruments Inc | シリコン・レベル相互接続層の機械的性能を構造的に増強する方法 |
JP2002203858A (ja) * | 2000-10-26 | 2002-07-19 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2002208610A (ja) * | 2000-12-21 | 2002-07-26 | Samsung Electronics Co Ltd | 集積回路のためのボンディングパッド及びその製造方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6439035A (en) * | 1987-08-04 | 1989-02-09 | Nec Corp | Semiconductor device |
-
2004
- 2004-08-26 JP JP2004246549A patent/JP4579621B2/ja not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1154544A (ja) * | 1997-05-01 | 1999-02-26 | Texas Instr Inc <Ti> | ボンド・パッドを増強するシステムおよび方法 |
JP2000195896A (ja) * | 1998-12-25 | 2000-07-14 | Nec Corp | 半導体装置 |
JP2000195866A (ja) * | 1998-12-28 | 2000-07-14 | Samsung Electronics Co Ltd | 半導体素子のボンディングパッド構造及びその製造方法 |
JP2001085465A (ja) * | 1999-09-16 | 2001-03-30 | Matsushita Electronics Industry Corp | 半導体装置 |
JP2002016069A (ja) * | 2000-06-29 | 2002-01-18 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2002134509A (ja) * | 2000-08-31 | 2002-05-10 | Texas Instruments Inc | シリコン・レベル相互接続層の機械的性能を構造的に増強する方法 |
JP2002203858A (ja) * | 2000-10-26 | 2002-07-19 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2002208610A (ja) * | 2000-12-21 | 2002-07-26 | Samsung Electronics Co Ltd | 集積回路のためのボンディングパッド及びその製造方法 |
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JP2005123587A (ja) | 2005-05-12 |
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