RU2008112657A - Полупроводниковое устройство - Google Patents

Полупроводниковое устройство Download PDF

Info

Publication number
RU2008112657A
RU2008112657A RU2008112657/28A RU2008112657A RU2008112657A RU 2008112657 A RU2008112657 A RU 2008112657A RU 2008112657/28 A RU2008112657/28 A RU 2008112657/28A RU 2008112657 A RU2008112657 A RU 2008112657A RU 2008112657 A RU2008112657 A RU 2008112657A
Authority
RU
Russia
Prior art keywords
semiconductor device
interconnect layer
layer
uppermost
conductive layer
Prior art date
Application number
RU2008112657/28A
Other languages
English (en)
Other versions
RU2447540C2 (ru
Inventor
Сигехиро МОРИКАВА (JP)
Сигехиро МОРИКАВА
Юити ИНАБА (JP)
Юити ИНАБА
Юдзи ГОТО (JP)
Юдзи ГОТО
Original Assignee
Санио Электрик Ко., Лтд. (Jp)
Санио Электрик Ко., Лтд.
Санио Семикондактор Ко., Лтд. (Jp)
Санио Семикондактор Ко., Лтд.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Санио Электрик Ко., Лтд. (Jp), Санио Электрик Ко., Лтд., Санио Семикондактор Ко., Лтд. (Jp), Санио Семикондактор Ко., Лтд. filed Critical Санио Электрик Ко., Лтд. (Jp)
Publication of RU2008112657A publication Critical patent/RU2008112657A/ru
Application granted granted Critical
Publication of RU2447540C2 publication Critical patent/RU2447540C2/ru

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05096—Uniform arrangement, i.e. array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0494—4th Group
    • H01L2924/04941—TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

1. Полупроводниковое устройство, содержащее ! полупроводниковую подложку; ! слой межсоединений, расположенный на полупроводниковой подложке; ! межслойную изоляционную пленку и проводящий слой, которые расположены на слое межсоединений так, что проводящий слой образует сотовую структуру относительно плоскости, параллельной главной плоскости полупроводниковой подложки, а межслойная изоляционная пленка заполняет шестиугольные столбики сотовой структуры так, чтобы она была электрически соединена со слоем межсоединений; и ! самый верхний слой межсоединений, расположенный на межслойной изоляционной пленке и проводящем слое так, чтобы он был электрически соединен со слоем межсоединений посредством проводящего слоя. ! 2. Полупроводниковое устройство по п.1, дополнительно содержащее другую межслойную изоляционную пленку, расположенную между полупроводниковой подложкой и слоем межсоединений, и элемент устройства, образованный в полупроводниковой подложке, причем самый верхний слой межсоединений покрывает элемент устройства. ! 3. Полупроводниковое устройство по п.1, в котором слой межсоединений является большим по площади, чем самый верхний слой межсоединений. ! 4. Полупроводниковое устройство по п.2, в котором слой межсоединений является большим по площади, чем самый верхний слой межсоединений. ! 5. Полупроводниковое устройство по п.1, в котором самый верхний слой межсоединений содержит контактную площадку. ! 6. Полупроводниковое устройство по п.2, в котором самый верхний слой межсоединений содержит контактную площадку. ! 7. Полупроводниковое устройство по п.1, дополнительно содержащее защитную пленку, расположенн�

Claims (20)

1. Полупроводниковое устройство, содержащее
полупроводниковую подложку;
слой межсоединений, расположенный на полупроводниковой подложке;
межслойную изоляционную пленку и проводящий слой, которые расположены на слое межсоединений так, что проводящий слой образует сотовую структуру относительно плоскости, параллельной главной плоскости полупроводниковой подложки, а межслойная изоляционная пленка заполняет шестиугольные столбики сотовой структуры так, чтобы она была электрически соединена со слоем межсоединений; и
самый верхний слой межсоединений, расположенный на межслойной изоляционной пленке и проводящем слое так, чтобы он был электрически соединен со слоем межсоединений посредством проводящего слоя.
2. Полупроводниковое устройство по п.1, дополнительно содержащее другую межслойную изоляционную пленку, расположенную между полупроводниковой подложкой и слоем межсоединений, и элемент устройства, образованный в полупроводниковой подложке, причем самый верхний слой межсоединений покрывает элемент устройства.
3. Полупроводниковое устройство по п.1, в котором слой межсоединений является большим по площади, чем самый верхний слой межсоединений.
4. Полупроводниковое устройство по п.2, в котором слой межсоединений является большим по площади, чем самый верхний слой межсоединений.
5. Полупроводниковое устройство по п.1, в котором самый верхний слой межсоединений содержит контактную площадку.
6. Полупроводниковое устройство по п.2, в котором самый верхний слой межсоединений содержит контактную площадку.
7. Полупроводниковое устройство по п.1, дополнительно содержащее защитную пленку, расположенную на самом верхнем слое межсоединений и имеющую отверстие, в котором обнажен участок самого верхнего слоя межсоединений, причем слой межсоединений является большим, чем это отверстие.
8. Полупроводниковое устройство по п.2, дополнительно содержащее защитную пленку, расположенную на самом верхнем слое межсоединений и имеющую отверстие, в котором обнажен участок самого верхнего слоя межсоединений, причем слой межсоединений является большим, чем это отверстие.
9. Полупроводниковое устройство по п.5, дополнительно содержащее защитную пленку, расположенную на самом верхнем слое межсоединений и имеющую отверстие, в котором обнажен участок самого верхнего слоя межсоединений, причем слой межсоединений является большим, чем это отверстие.
10. Полупроводниковое устройство по п.6, дополнительно содержащее защитную пленку, расположенную на самом верхнем слое межсоединений и имеющую отверстие, в котором обнажен участок самого верхнего слоя межсоединений, причем слой межсоединений является большим, чем это отверстие.
11. Полупроводниковое устройство по п.1, в котором ширина проводящего слоя больше или равна утроенному расстоянию между парой противоположных боковых поверхностей шестиугольного столбика сотовой структуры.
12. Полупроводниковое устройство по п.2, в котором ширина проводящего слоя больше или равна утроенному расстоянию между парой противоположных боковых поверхностей шестиугольного столбика сотовой структуры.
13. Полупроводниковое устройство по п.3, в котором ширина проводящего слоя больше или равна утроенному расстоянию между парой противоположных боковых поверхностей шестиугольного столбика сотовой структуры.
14. Полупроводниковое устройство по п.4, в котором ширина проводящего слоя больше или равна утроенному расстоянию между парой противоположных боковых поверхностей шестиугольного столбика сотовой структуры.
15. Полупроводниковое устройство по п.5, в котором ширина проводящего слоя больше или равна утроенному расстоянию между парой противоположных боковых поверхностей шестиугольного столбика сотовой структуры.
16. Полупроводниковое устройство по п.6, в котором ширина проводящего слоя больше или равна утроенному расстоянию между парой противоположных боковых поверхностей шестиугольного столбика сотовой структуры.
17. Полупроводниковое устройство по п.7, в котором ширина проводящего слоя больше или равна утроенному расстоянию между парой противоположных боковых поверхностей шестиугольного столбика сотовой структуры.
18. Полупроводниковое устройство по п.8, в котором ширина проводящего слоя больше или равна утроенному расстоянию между парой противоположных боковых поверхностей шестиугольного столбика сотовой структуры.
19. Полупроводниковое устройство по п.9, в котором ширина проводящего слоя больше или равна утроенному расстоянию между парой противоположных боковых поверхностей шестиугольного столбика сотовой структуры.
20. Полупроводниковое устройство по п.10, в котором ширина проводящего слоя больше или равна утроенному расстоянию между парой противоположных боковых поверхностей шестиугольного столбика сотовой структуры.
RU2008112657/28A 2007-04-02 2008-04-01 Полупроводниковое устройство RU2447540C2 (ru)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-096327 2007-04-02
JP2007096327A JP2008258258A (ja) 2007-04-02 2007-04-02 半導体装置

Publications (2)

Publication Number Publication Date
RU2008112657A true RU2008112657A (ru) 2009-10-10
RU2447540C2 RU2447540C2 (ru) 2012-04-10

Family

ID=39792847

Family Applications (1)

Application Number Title Priority Date Filing Date
RU2008112657/28A RU2447540C2 (ru) 2007-04-02 2008-04-01 Полупроводниковое устройство

Country Status (6)

Country Link
US (1) US7741724B2 (ru)
JP (1) JP2008258258A (ru)
KR (1) KR20080090304A (ru)
CN (1) CN101281893B (ru)
RU (1) RU2447540C2 (ru)
TW (1) TWI370500B (ru)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7692315B2 (en) * 2002-08-30 2010-04-06 Fujitsu Microelectronics Limited Semiconductor device and method for manufacturing the same
CN1601735B (zh) * 2003-09-26 2010-06-23 松下电器产业株式会社 半导体器件及其制造方法
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
CN101675516B (zh) 2007-03-05 2012-06-20 数字光学欧洲有限公司 具有通过过孔连接到前侧触头的后侧触头的芯片
KR101588723B1 (ko) 2007-07-31 2016-01-26 인벤사스 코포레이션 실리콘 쓰루 비아를 사용하는 반도체 패키지 공정
US8624391B2 (en) * 2009-10-08 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Chip design with robust corner bumps
US8659170B2 (en) * 2010-01-20 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having conductive pads and a method of manufacturing the same
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
KR101059490B1 (ko) 2010-11-15 2011-08-25 테세라 리써치 엘엘씨 임베드된 트레이스에 의해 구성된 전도성 패드
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
JP5922331B2 (ja) * 2011-02-02 2016-05-24 ラピスセミコンダクタ株式会社 半導体装置の配線構造及びその製造方法
US8664113B2 (en) * 2011-04-28 2014-03-04 GlobalFoundries, Inc. Multilayer interconnect structure and method for integrated circuits
US8525168B2 (en) * 2011-07-11 2013-09-03 International Business Machines Corporation Integrated circuit (IC) test probe
US9768221B2 (en) * 2013-06-27 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Pad structure layout for semiconductor device
US9852988B2 (en) * 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
CA3015971A1 (en) * 2016-03-01 2017-09-08 Cardlab Aps A circuit layer for an integrated circuit card
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
KR20230156179A (ko) 2016-12-29 2023-11-13 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 집적된 수동 컴포넌트를 구비한 접합된 구조체
US10276909B2 (en) 2016-12-30 2019-04-30 Invensas Bonding Technologies, Inc. Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
WO2018169968A1 (en) 2017-03-16 2018-09-20 Invensas Corporation Direct-bonded led arrays and applications
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
CN111106084B (zh) * 2018-10-25 2021-08-10 株洲中车时代半导体有限公司 用于引线键合的衬底金属层结构及功率半导体器件
CN111106073B (zh) * 2018-10-26 2022-08-05 株洲中车时代半导体有限公司 一种功率半导体器件的低应力薄膜结构
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
JP7459490B2 (ja) 2019-11-28 2024-04-02 株式会社ソシオネクスト 半導体ウェハ及び半導体装置
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
KR20220058757A (ko) 2020-10-30 2022-05-10 삼성디스플레이 주식회사 표시 장치
CN112310071B (zh) * 2020-10-30 2024-04-05 上海华力微电子有限公司 测试结构、测试结构版图及其形成方法和测试方法
US11887949B2 (en) * 2021-08-18 2024-01-30 Macronix International Co., Ltd. Bond pad layout including floating conductive sections

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1044203A1 (ru) * 1981-01-04 1988-04-23 Предприятие П/Я А-1889 Полупроводникова тестова микроструктура дл интегральной схемы
US4795500A (en) * 1985-07-02 1989-01-03 Sanyo Electric Co., Ltd. Photovoltaic device
JP2906089B2 (ja) 1990-12-17 1999-06-14 忠道 政本 ランダム・アクセス・メモリ。
JP2916326B2 (ja) 1992-06-11 1999-07-05 三菱電機株式会社 半導体装置のパッド構造
JPH06196525A (ja) 1992-12-24 1994-07-15 Kawasaki Steel Corp ボンディングパッドの構造
JPH09312332A (ja) 1996-05-22 1997-12-02 Mitsubishi Electric Corp 半導体装置
US6143396A (en) * 1997-05-01 2000-11-07 Texas Instruments Incorporated System and method for reinforcing a bond pad
KR100267105B1 (ko) * 1997-12-09 2000-11-01 윤종용 다층패드를구비한반도체소자및그제조방법
TW430935B (en) * 1999-03-19 2001-04-21 Ind Tech Res Inst Frame type bonding pad structure having a low parasitic capacitance
JP3434793B2 (ja) 2000-09-29 2003-08-11 Ｎｅｃエレクトロニクス株式会社 半導体装置とその製造方法
US20020195723A1 (en) * 2001-06-25 2002-12-26 Daniel Collette Bond pad structure
JP3524908B2 (ja) * 2002-01-21 2004-05-10 株式会社半導体理工学研究センター 半導体装置
JP3935091B2 (ja) * 2003-02-27 2007-06-20 浜松ホトニクス株式会社 半導体装置、及びそれを用いた放射線検出器
CN1601735B (zh) * 2003-09-26 2010-06-23 松下电器产业株式会社 半导体器件及其制造方法
JP4579621B2 (ja) * 2003-09-26 2010-11-10 パナソニック株式会社 半導体装置
JP4639326B2 (ja) * 2004-03-24 2011-02-23 独立行政法人産業技術総合研究所 半導体装置
US7420280B1 (en) * 2005-05-02 2008-09-02 National Semiconductor Corporation Reduced stress under bump metallization structure

Also Published As

Publication number Publication date
JP2008258258A (ja) 2008-10-23
KR20080090304A (ko) 2008-10-08
US20080237877A1 (en) 2008-10-02
TWI370500B (en) 2012-08-11
RU2447540C2 (ru) 2012-04-10
CN101281893B (zh) 2010-06-16
TW200845252A (en) 2008-11-16
CN101281893A (zh) 2008-10-08
US7741724B2 (en) 2010-06-22

Similar Documents

Publication Publication Date Title
RU2008112657A (ru) Полупроводниковое устройство
JP2010147281A5 (ja) 半導体装置
JP2006203187A5 (ru)
JP2008544540A5 (ru)
JP2015173289A5 (ru)
JP2011171739A5 (ru)
AR086302A1 (es) Parabrisas con un elemento de conexion electrica
ATE497223T1 (de) Einlagen mit doppelschnittstelle
JP2014096591A5 (ru)
JP2006303488A5 (ru)
JP2012064849A5 (ru)
TW200709476A (en) Side view LED with improved arrangement of protection device
JP2009192309A5 (ru)
JP2007142436A5 (ru)
EP2107653A3 (en) Surface Emitting Laser Element Array
JP2016092414A5 (ru)
JP2012015480A5 (ru)
JP2006515956A5 (ru)
WO2009013826A1 (ja) 半導体装置
JP2012227472A5 (ru)
JP2016012707A5 (ru)
JP2011009352A5 (ja) 半導体装置
JP2013219348A5 (ru)
JP2007073976A5 (ru)
JP2009194387A5 (ru)

Legal Events

Date Code Title Description
MM4A The patent is invalid due to non-payment of fees

Effective date: 20140402