TWI370500B - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- TWI370500B TWI370500B TW097107998A TW97107998A TWI370500B TW I370500 B TWI370500 B TW I370500B TW 097107998 A TW097107998 A TW 097107998A TW 97107998 A TW97107998 A TW 97107998A TW I370500 B TWI370500 B TW I370500B
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor device
- semiconductor
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05001—Internal layers
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- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
- H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
- H01L2224/05096—Uniform arrangement, i.e. array
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/0554—External layer
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/14—Integrated circuits
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- H01L2924/181—Encapsulation
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007096327A JP2008258258A (ja) | 2007-04-02 | 2007-04-02 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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TW200845252A TW200845252A (en) | 2008-11-16 |
TWI370500B true TWI370500B (en) | 2012-08-11 |
Family
ID=39792847
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW097107998A TWI370500B (en) | 2007-04-02 | 2008-03-07 | Semiconductor device |
Country Status (6)
Country | Link |
---|---|
US (1) | US7741724B2 (zh) |
JP (1) | JP2008258258A (zh) |
KR (1) | KR20080090304A (zh) |
CN (1) | CN101281893B (zh) |
RU (1) | RU2447540C2 (zh) |
TW (1) | TWI370500B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI793971B (zh) * | 2021-08-18 | 2023-02-21 | 旺宏電子股份有限公司 | 半導體裝置及接合襯墊配置 |
Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
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US7692315B2 (en) * | 2002-08-30 | 2010-04-06 | Fujitsu Microelectronics Limited | Semiconductor device and method for manufacturing the same |
CN1601735B (zh) * | 2003-09-26 | 2010-06-23 | 松下电器产业株式会社 | 半导体器件及其制造方法 |
US7791199B2 (en) | 2006-11-22 | 2010-09-07 | Tessera, Inc. | Packaged semiconductor chips |
US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
CN101675516B (zh) | 2007-03-05 | 2012-06-20 | 数字光学欧洲有限公司 | 具有通过过孔连接到前侧触头的后侧触头的芯片 |
KR101538648B1 (ko) | 2007-07-31 | 2015-07-22 | 인벤사스 코포레이션 | 실리콘 쓰루 비아를 사용하는 반도체 패키지 공정 |
US8624391B2 (en) * | 2009-10-08 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip design with robust corner bumps |
US8659170B2 (en) * | 2010-01-20 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having conductive pads and a method of manufacturing the same |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
US8796135B2 (en) | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
US8610259B2 (en) | 2010-09-17 | 2013-12-17 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
KR101059490B1 (ko) | 2010-11-15 | 2011-08-25 | 테세라 리써치 엘엘씨 | 임베드된 트레이스에 의해 구성된 전도성 패드 |
US8637968B2 (en) | 2010-12-02 | 2014-01-28 | Tessera, Inc. | Stacked microelectronic assembly having interposer connecting active chips |
US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
US8587126B2 (en) | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US8610264B2 (en) | 2010-12-08 | 2013-12-17 | Tessera, Inc. | Compliant interconnects in wafers |
JP5922331B2 (ja) * | 2011-02-02 | 2016-05-24 | ラピスセミコンダクタ株式会社 | 半導体装置の配線構造及びその製造方法 |
US8664113B2 (en) * | 2011-04-28 | 2014-03-04 | GlobalFoundries, Inc. | Multilayer interconnect structure and method for integrated circuits |
US8525168B2 (en) * | 2011-07-11 | 2013-09-03 | International Business Machines Corporation | Integrated circuit (IC) test probe |
US9768221B2 (en) | 2013-06-27 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad structure layout for semiconductor device |
US9852988B2 (en) | 2015-12-18 | 2017-12-26 | Invensas Bonding Technologies, Inc. | Increased contact alignment tolerance for direct bonding |
AU2017226865B2 (en) | 2016-03-01 | 2022-08-25 | Cardlab Aps | A circuit layer for an integrated circuit card |
US10446487B2 (en) | 2016-09-30 | 2019-10-15 | Invensas Bonding Technologies, Inc. | Interface structures and methods for forming same |
US10580735B2 (en) | 2016-10-07 | 2020-03-03 | Xcelsis Corporation | Stacked IC structure with system level wiring on multiple sides of the IC die |
JP2020503692A (ja) | 2016-12-29 | 2020-01-30 | インヴェンサス ボンディング テクノロジーズ インコーポレイテッド | 集積された受動部品を有する接合構造物 |
US10276909B2 (en) | 2016-12-30 | 2019-04-30 | Invensas Bonding Technologies, Inc. | Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein |
WO2018169968A1 (en) | 2017-03-16 | 2018-09-20 | Invensas Corporation | Direct-bonded led arrays and applications |
US10784191B2 (en) | 2017-03-31 | 2020-09-22 | Invensas Bonding Technologies, Inc. | Interface structures and methods for forming same |
US11169326B2 (en) | 2018-02-26 | 2021-11-09 | Invensas Bonding Technologies, Inc. | Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects |
US11515291B2 (en) | 2018-08-28 | 2022-11-29 | Adeia Semiconductor Inc. | Integrated voltage regulator and passive components |
CN111106084B (zh) * | 2018-10-25 | 2021-08-10 | 株洲中车时代半导体有限公司 | 用于引线键合的衬底金属层结构及功率半导体器件 |
CN111106073B (zh) * | 2018-10-26 | 2022-08-05 | 株洲中车时代半导体有限公司 | 一种功率半导体器件的低应力薄膜结构 |
US11901281B2 (en) | 2019-03-11 | 2024-02-13 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structures with integrated passive component |
JP7459490B2 (ja) | 2019-11-28 | 2024-04-02 | 株式会社ソシオネクスト | 半導体ウェハ及び半導体装置 |
US11762200B2 (en) | 2019-12-17 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded optical devices |
KR20220058757A (ko) | 2020-10-30 | 2022-05-10 | 삼성디스플레이 주식회사 | 표시 장치 |
CN112310071B (zh) * | 2020-10-30 | 2024-04-05 | 上海华力微电子有限公司 | 测试结构、测试结构版图及其形成方法和测试方法 |
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JP2906089B2 (ja) | 1990-12-17 | 1999-06-14 | 忠道 政本 | ランダム・アクセス・メモリ。 |
JP2916326B2 (ja) | 1992-06-11 | 1999-07-05 | 三菱電機株式会社 | 半導体装置のパッド構造 |
JPH06196525A (ja) | 1992-12-24 | 1994-07-15 | Kawasaki Steel Corp | ボンディングパッドの構造 |
JPH09312332A (ja) | 1996-05-22 | 1997-12-02 | Mitsubishi Electric Corp | 半導体装置 |
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JP3434793B2 (ja) | 2000-09-29 | 2003-08-11 | Necエレクトロニクス株式会社 | 半導体装置とその製造方法 |
US20020195723A1 (en) * | 2001-06-25 | 2002-12-26 | Daniel Collette | Bond pad structure |
JP3524908B2 (ja) * | 2002-01-21 | 2004-05-10 | 株式会社半導体理工学研究センター | 半導体装置 |
JP3935091B2 (ja) * | 2003-02-27 | 2007-06-20 | 浜松ホトニクス株式会社 | 半導体装置、及びそれを用いた放射線検出器 |
JP4579621B2 (ja) * | 2003-09-26 | 2010-11-10 | パナソニック株式会社 | 半導体装置 |
CN1601735B (zh) * | 2003-09-26 | 2010-06-23 | 松下电器产业株式会社 | 半导体器件及其制造方法 |
JP4639326B2 (ja) * | 2004-03-24 | 2011-02-23 | 独立行政法人産業技術総合研究所 | 半導体装置 |
US7420280B1 (en) * | 2005-05-02 | 2008-09-02 | National Semiconductor Corporation | Reduced stress under bump metallization structure |
-
2007
- 2007-04-02 JP JP2007096327A patent/JP2008258258A/ja active Pending
-
2008
- 2008-03-07 TW TW097107998A patent/TWI370500B/zh not_active IP Right Cessation
- 2008-04-01 RU RU2008112657/28A patent/RU2447540C2/ru not_active IP Right Cessation
- 2008-04-01 US US12/060,673 patent/US7741724B2/en active Active
- 2008-04-01 KR KR1020080030277A patent/KR20080090304A/ko not_active Application Discontinuation
- 2008-04-01 CN CN2008100889477A patent/CN101281893B/zh not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI793971B (zh) * | 2021-08-18 | 2023-02-21 | 旺宏電子股份有限公司 | 半導體裝置及接合襯墊配置 |
US11887949B2 (en) | 2021-08-18 | 2024-01-30 | Macronix International Co., Ltd. | Bond pad layout including floating conductive sections |
Also Published As
Publication number | Publication date |
---|---|
CN101281893A (zh) | 2008-10-08 |
CN101281893B (zh) | 2010-06-16 |
RU2008112657A (ru) | 2009-10-10 |
US20080237877A1 (en) | 2008-10-02 |
US7741724B2 (en) | 2010-06-22 |
KR20080090304A (ko) | 2008-10-08 |
TW200845252A (en) | 2008-11-16 |
JP2008258258A (ja) | 2008-10-23 |
RU2447540C2 (ru) | 2012-04-10 |
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