JP2010147281A5 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2010147281A5 JP2010147281A5 JP2008323581A JP2008323581A JP2010147281A5 JP 2010147281 A5 JP2010147281 A5 JP 2010147281A5 JP 2008323581 A JP2008323581 A JP 2008323581A JP 2008323581 A JP2008323581 A JP 2008323581A JP 2010147281 A5 JP2010147281 A5 JP 2010147281A5
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor substrate
- main surface
- pad
- elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Claims (2)
- 厚さ方向に沿って互いに反対側に位置する第1主面と第2主面とを有する半導体基板と、
前記半導体基板の第1主面に形成された複数の素子と、
前記半導体基板の第1主面において前記複数の素子を覆うようにして形成された層間絶縁膜と、
前記複数の素子と電気的に接続するようにして、前記層間絶縁膜の表面に形成されたパッドと、
前記パッドに電気的に接続するようにして形成されたバンプ形状の第1電極と、
前記第1電極と電気的に接続するようにして、前記半導体基板の第2主面に形成された第2電極とを有し、
前記第1電極は、前記パッドを貫通し、前記半導体基板側に向かって突出するような突出部を有し、
前記第2電極は、前記半導体基板の第2主面側から第1主面側に向かって、前記第1電極の突出部に達し、かつ、前記パッドには達しないような第2電極用孔部の内側を覆うようにして形成されていることで、前記第1電極と電気的に接続されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1電極の突出部は、前記半導体基板内に達する深さまで突出していることを特徴とする半導体装置。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008323581A JP5308145B2 (ja) | 2008-12-19 | 2008-12-19 | 半導体装置 |
US12/640,766 US8106518B2 (en) | 2008-12-19 | 2009-12-17 | Semiconductor device and method of manufacturing the same |
US13/340,165 US8816506B2 (en) | 2008-12-19 | 2011-12-29 | Semiconductor device and method of manufacturing the same |
US14/464,026 US9076700B2 (en) | 2008-12-19 | 2014-08-20 | Semiconductor device and method of manufacturing same |
US14/716,791 US9318418B2 (en) | 2008-12-19 | 2015-05-19 | Semiconductor device and method of manufacturing same |
US15/061,444 US9691739B2 (en) | 2008-12-19 | 2016-03-04 | Semiconductor device and method of manufacturing same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008323581A JP5308145B2 (ja) | 2008-12-19 | 2008-12-19 | 半導体装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2010147281A JP2010147281A (ja) | 2010-07-01 |
JP2010147281A5 true JP2010147281A5 (ja) | 2012-02-02 |
JP5308145B2 JP5308145B2 (ja) | 2013-10-09 |
Family
ID=42264835
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008323581A Active JP5308145B2 (ja) | 2008-12-19 | 2008-12-19 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (5) | US8106518B2 (ja) |
JP (1) | JP5308145B2 (ja) |
Families Citing this family (73)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8569876B2 (en) | 2006-11-22 | 2013-10-29 | Tessera, Inc. | Packaged semiconductor chips with array |
US7791199B2 (en) | 2006-11-22 | 2010-09-07 | Tessera, Inc. | Packaged semiconductor chips |
CN101675516B (zh) | 2007-03-05 | 2012-06-20 | 数字光学欧洲有限公司 | 具有通过过孔连接到前侧触头的后侧触头的芯片 |
KR101538648B1 (ko) | 2007-07-31 | 2015-07-22 | 인벤사스 코포레이션 | 실리콘 쓰루 비아를 사용하는 반도체 패키지 공정 |
JP5455538B2 (ja) * | 2008-10-21 | 2014-03-26 | キヤノン株式会社 | 半導体装置及びその製造方法 |
US8304863B2 (en) * | 2010-02-09 | 2012-11-06 | International Business Machines Corporation | Electromigration immune through-substrate vias |
JP2011187681A (ja) * | 2010-03-09 | 2011-09-22 | Toshiba Corp | 半導体装置の製造方法および半導体装置 |
KR101078745B1 (ko) * | 2010-06-09 | 2011-11-02 | 주식회사 하이닉스반도체 | 반도체 칩 및 그의 제조방법 |
US8796135B2 (en) * | 2010-07-23 | 2014-08-05 | Tessera, Inc. | Microelectronic elements with rear contacts connected with via first or via middle structures |
US9640437B2 (en) | 2010-07-23 | 2017-05-02 | Tessera, Inc. | Methods of forming semiconductor elements using micro-abrasive particle stream |
US8791575B2 (en) | 2010-07-23 | 2014-07-29 | Tessera, Inc. | Microelectronic elements having metallic pads overlying vias |
US8847380B2 (en) | 2010-09-17 | 2014-09-30 | Tessera, Inc. | Staged via formation from both sides of chip |
US8610259B2 (en) | 2010-09-17 | 2013-12-17 | Tessera, Inc. | Multi-function and shielded 3D interconnects |
US8637968B2 (en) | 2010-12-02 | 2014-01-28 | Tessera, Inc. | Stacked microelectronic assembly having interposer connecting active chips |
US8587126B2 (en) | 2010-12-02 | 2013-11-19 | Tessera, Inc. | Stacked microelectronic assembly with TSVs formed in stages with plural active chips |
US8736066B2 (en) | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
US8610264B2 (en) | 2010-12-08 | 2013-12-17 | Tessera, Inc. | Compliant interconnects in wafers |
FR2969381A1 (fr) * | 2010-12-21 | 2012-06-22 | St Microelectronics Crolles 2 | Puce electronique comportant des piliers de connexion, et procede de fabrication |
JP5561190B2 (ja) | 2011-01-31 | 2014-07-30 | 富士通株式会社 | 半導体装置、半導体装置の製造方法及び電子装置 |
JP2012231096A (ja) * | 2011-04-27 | 2012-11-22 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US8853857B2 (en) * | 2011-05-05 | 2014-10-07 | International Business Machines Corporation | 3-D integration using multi stage vias |
JP5579126B2 (ja) * | 2011-05-30 | 2014-08-27 | 日本電子材料株式会社 | 三次元構成デバイス |
US8853072B2 (en) | 2011-06-06 | 2014-10-07 | Micron Technology, Inc. | Methods of forming through-substrate interconnects |
KR101918609B1 (ko) * | 2012-01-11 | 2018-11-14 | 삼성전자 주식회사 | 집적회로 소자 |
JP5970696B2 (ja) * | 2012-03-27 | 2016-08-17 | セイコーエプソン株式会社 | 電子デバイスの製造方法、電子デバイス |
FR2990297A1 (fr) | 2012-05-07 | 2013-11-08 | St Microelectronics Crolles 2 | Empilement de structures semi-conductrices et procede de fabrication correspondant |
KR20150052175A (ko) * | 2012-09-05 | 2015-05-13 | 리써치트라이앵글인스티튜트 | 돌출부들을 갖는 컨택 패드들을 이용하는 전자 소자들 및 제조 방법들 |
KR102021884B1 (ko) * | 2012-09-25 | 2019-09-18 | 삼성전자주식회사 | 후면 본딩 구조체를 갖는 반도체 소자 |
US9159699B2 (en) * | 2012-11-13 | 2015-10-13 | Delta Electronics, Inc. | Interconnection structure having a via structure |
US9343400B2 (en) * | 2013-03-13 | 2016-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual damascene gap filling process |
JP5826782B2 (ja) * | 2013-03-19 | 2015-12-02 | 株式会社東芝 | 半導体装置の製造方法 |
US9443758B2 (en) | 2013-12-11 | 2016-09-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Connecting techniques for stacked CMOS devices |
JP6254459B2 (ja) * | 2014-02-27 | 2017-12-27 | 東京エレクトロン株式会社 | 重合膜の耐薬品性改善方法、重合膜の成膜方法、成膜装置、および電子製品の製造方法 |
EP3376531B1 (en) | 2014-02-28 | 2023-04-05 | LFoundry S.r.l. | Semiconductor device comprising a laterally diffused transistor |
US9355997B2 (en) | 2014-03-12 | 2016-05-31 | Invensas Corporation | Integrated circuit assemblies with reinforcement frames, and methods of manufacture |
US20150262902A1 (en) | 2014-03-12 | 2015-09-17 | Invensas Corporation | Integrated circuits protected by substrates with cavities, and methods of manufacture |
US9165793B1 (en) | 2014-05-02 | 2015-10-20 | Invensas Corporation | Making electrical components in handle wafers of integrated circuit packages |
US9455214B2 (en) | 2014-05-19 | 2016-09-27 | Globalfoundries Inc. | Wafer frontside-backside through silicon via |
US9741649B2 (en) | 2014-06-04 | 2017-08-22 | Invensas Corporation | Integrated interposer solutions for 2D and 3D IC packaging |
US9412806B2 (en) | 2014-06-13 | 2016-08-09 | Invensas Corporation | Making multilayer 3D capacitors using arrays of upstanding rods or ridges |
US9252127B1 (en) | 2014-07-10 | 2016-02-02 | Invensas Corporation | Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture |
US9496154B2 (en) | 2014-09-16 | 2016-11-15 | Invensas Corporation | Use of underfill tape in microelectronic components, and microelectronic components with cavities coupled to through-substrate vias |
JP6436531B2 (ja) * | 2015-01-30 | 2018-12-12 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
US9478504B1 (en) | 2015-06-19 | 2016-10-25 | Invensas Corporation | Microelectronic assemblies with cavities, and methods of fabrication |
JP6290830B6 (ja) * | 2015-06-22 | 2023-10-11 | セイコーエプソン株式会社 | 半導体装置、センサーおよび電子デバイス |
CN105405821A (zh) * | 2015-12-16 | 2016-03-16 | 华进半导体封装先导技术研发中心有限公司 | 一种晶圆级tsv封装结构及封装工艺 |
WO2017209296A1 (ja) * | 2016-06-03 | 2017-12-07 | 大日本印刷株式会社 | 貫通電極基板及びその製造方法、並びに実装基板 |
US10586786B2 (en) | 2016-10-07 | 2020-03-10 | Xcelsis Corporation | 3D chip sharing clock interconnect layer |
KR102393946B1 (ko) | 2016-10-07 | 2022-05-03 | 엑셀시스 코포레이션 | 직접-접합된 네이티브 상호접속부 및 능동 베이스 다이 |
US10600780B2 (en) | 2016-10-07 | 2020-03-24 | Xcelsis Corporation | 3D chip sharing data bus circuit |
US10580735B2 (en) | 2016-10-07 | 2020-03-03 | Xcelsis Corporation | Stacked IC structure with system level wiring on multiple sides of the IC die |
US10600735B2 (en) | 2016-10-07 | 2020-03-24 | Xcelsis Corporation | 3D chip sharing data bus |
US10580757B2 (en) | 2016-10-07 | 2020-03-03 | Xcelsis Corporation | Face-to-face mounted IC dies with orthogonal top interconnect layers |
US10672745B2 (en) | 2016-10-07 | 2020-06-02 | Xcelsis Corporation | 3D processor |
US10672744B2 (en) | 2016-10-07 | 2020-06-02 | Xcelsis Corporation | 3D compute circuit with high density Z-axis interconnects |
US10672663B2 (en) | 2016-10-07 | 2020-06-02 | Xcelsis Corporation | 3D chip sharing power circuit |
US10607136B2 (en) | 2017-08-03 | 2020-03-31 | Xcelsis Corporation | Time borrowing between layers of a three dimensional chip stack |
US10593667B2 (en) | 2016-10-07 | 2020-03-17 | Xcelsis Corporation | 3D chip with shielded clock lines |
US10600691B2 (en) | 2016-10-07 | 2020-03-24 | Xcelsis Corporation | 3D chip sharing power interconnect layer |
US10672743B2 (en) | 2016-10-07 | 2020-06-02 | Xcelsis Corporation | 3D Compute circuit with high density z-axis interconnects |
EP3324436B1 (en) * | 2016-11-21 | 2020-08-05 | IMEC vzw | An integrated circuit chip with power delivery network on the backside of the chip |
JP6863574B2 (ja) * | 2017-02-22 | 2021-04-21 | 住友電工デバイス・イノベーション株式会社 | 半導体装置の製造方法 |
US10418311B2 (en) * | 2017-03-28 | 2019-09-17 | Micron Technology, Inc. | Method of forming vias using silicon on insulator substrate |
US10325870B2 (en) * | 2017-05-09 | 2019-06-18 | International Business Machines Corporation | Through-substrate-vias with self-aligned solder bumps |
US10750614B2 (en) * | 2017-06-12 | 2020-08-18 | Invensas Corporation | Deformable electrical contacts with conformable target pads |
DE102017212763A1 (de) * | 2017-07-25 | 2019-01-31 | Infineon Technologies Ag | Eine Vorrichtung und ein Verfahren zum Herstellen einer Vorrichtung |
CN110246799B (zh) * | 2018-03-07 | 2021-06-25 | 长鑫存储技术有限公司 | 连接结构及其制造方法、半导体器件 |
JP7353748B2 (ja) * | 2018-11-29 | 2023-10-02 | キヤノン株式会社 | 半導体装置の製造方法および半導体装置 |
CN110010548B (zh) * | 2018-12-26 | 2021-08-24 | 浙江集迈科微电子有限公司 | 一种底部带焊盘的空腔结构制作方法 |
CN109817659B (zh) * | 2019-02-15 | 2021-08-06 | 京东方科技集团股份有限公司 | 显示基板及其制作方法、显示装置 |
CN110211931A (zh) * | 2019-06-14 | 2019-09-06 | 上海先方半导体有限公司 | 一种三维封装结构及其制造方法 |
US11599299B2 (en) | 2019-11-19 | 2023-03-07 | Invensas Llc | 3D memory circuit |
US20220287179A1 (en) * | 2021-03-04 | 2022-09-08 | Raytheon Company | Interconnect and Method for Manufacturing the Same |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5973396A (en) * | 1996-02-16 | 1999-10-26 | Micron Technology, Inc. | Surface mount IC using silicon vias in an area array format or same size as die array |
EP0926723B1 (en) * | 1997-11-26 | 2007-01-17 | STMicroelectronics S.r.l. | Process for forming front-back through contacts in micro-integrated electronic devices |
US6833613B1 (en) * | 1997-12-18 | 2004-12-21 | Micron Technology, Inc. | Stacked semiconductor package having laser machined contacts |
JP3918350B2 (ja) | 1999-03-05 | 2007-05-23 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
WO2001018596A1 (fr) * | 1999-09-08 | 2001-03-15 | Matsushita Electric Industrial Co., Ltd. | Dispositif d'affichage et son procede de fabrication |
US7087975B2 (en) * | 2000-12-28 | 2006-08-08 | Infineon Technologies Ag | Area efficient stacking of antifuses in semiconductor device |
WO2002079853A1 (en) * | 2001-03-16 | 2002-10-10 | Corning Intellisense Corporation | Electrostatically actuated micro-electro-mechanical devices and method of manufacture |
JP4053257B2 (ja) * | 2001-06-14 | 2008-02-27 | 新光電気工業株式会社 | 半導体装置の製造方法 |
US7354798B2 (en) * | 2002-12-20 | 2008-04-08 | International Business Machines Corporation | Three-dimensional device fabrication method |
KR100497111B1 (ko) * | 2003-03-25 | 2005-06-28 | 삼성전자주식회사 | 웨이퍼 레벨 칩 스케일 패키지, 그를 적층한 적층 패키지및 그 제조 방법 |
JP4074862B2 (ja) * | 2004-03-24 | 2008-04-16 | ローム株式会社 | 半導体装置の製造方法、半導体装置、および半導体チップ |
JP4439976B2 (ja) * | 2004-03-31 | 2010-03-24 | Necエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP4441328B2 (ja) * | 2004-05-25 | 2010-03-31 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
JP2006012953A (ja) * | 2004-06-23 | 2006-01-12 | Sharp Corp | 貫通電極の形成方法、貫通電極および半導体装置 |
US7232754B2 (en) * | 2004-06-29 | 2007-06-19 | Micron Technology, Inc. | Microelectronic devices and methods for forming interconnects in microelectronic devices |
JP2006041148A (ja) * | 2004-07-27 | 2006-02-09 | Seiko Epson Corp | 半導体装置の製造方法、半導体装置、及び電子機器 |
US7276794B2 (en) * | 2005-03-02 | 2007-10-02 | Endevco Corporation | Junction-isolated vias |
US7215032B2 (en) * | 2005-06-14 | 2007-05-08 | Cubic Wafer, Inc. | Triaxial through-chip connection |
JP4694305B2 (ja) | 2005-08-16 | 2011-06-08 | ルネサスエレクトロニクス株式会社 | 半導体ウエハの製造方法 |
JP2007067216A (ja) * | 2005-08-31 | 2007-03-15 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法、回路基板およびその製造方法 |
JP2007073919A (ja) | 2005-09-06 | 2007-03-22 | Tanemasa Asano | 突起電極の製造方法およびそれに用いられるベーク装置ならびに電子装置 |
JP4609317B2 (ja) * | 2005-12-28 | 2011-01-12 | カシオ計算機株式会社 | 回路基板 |
US7563714B2 (en) * | 2006-01-13 | 2009-07-21 | International Business Machines Corporation | Low resistance and inductance backside through vias and methods of fabricating same |
TWI287274B (en) * | 2006-01-25 | 2007-09-21 | Advanced Semiconductor Eng | Three dimensional package and method of making the same |
KR100884238B1 (ko) * | 2006-05-22 | 2009-02-17 | 삼성전자주식회사 | 앵커형 결합 구조를 갖는 반도체 패키지 및 그 제조 방법 |
US7473577B2 (en) * | 2006-08-11 | 2009-01-06 | International Business Machines Corporation | Integrated chip carrier with compliant interconnect |
JP2008053568A (ja) * | 2006-08-25 | 2008-03-06 | Nec Electronics Corp | 半導体装置および半導体装置の製造方法 |
JP5117698B2 (ja) * | 2006-09-27 | 2013-01-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR100843240B1 (ko) * | 2007-03-23 | 2008-07-03 | 삼성전자주식회사 | 웨이퍼 레벨 스택을 위한 반도체 소자 및 웨이퍼 레벨스택을 위한 반도체 소자의 관통전극 형성방법 |
TWI351751B (en) * | 2007-06-22 | 2011-11-01 | Ind Tech Res Inst | Self-aligned wafer or chip structure, self-aligned |
KR20090047776A (ko) * | 2007-11-08 | 2009-05-13 | 삼성전자주식회사 | 반도체 소자 및 그 형성 방법 |
US8138036B2 (en) * | 2008-08-08 | 2012-03-20 | International Business Machines Corporation | Through silicon via and method of fabricating same |
KR20100020718A (ko) * | 2008-08-13 | 2010-02-23 | 삼성전자주식회사 | 반도체 칩, 그 스택 구조 및 이들의 제조 방법 |
US7786008B2 (en) * | 2008-12-12 | 2010-08-31 | Stats Chippac Ltd. | Integrated circuit packaging system having through silicon vias with partial depth metal fill regions and method of manufacture thereof |
-
2008
- 2008-12-19 JP JP2008323581A patent/JP5308145B2/ja active Active
-
2009
- 2009-12-17 US US12/640,766 patent/US8106518B2/en active Active
-
2011
- 2011-12-29 US US13/340,165 patent/US8816506B2/en active Active
-
2014
- 2014-08-20 US US14/464,026 patent/US9076700B2/en active Active
-
2015
- 2015-05-19 US US14/716,791 patent/US9318418B2/en active Active
-
2016
- 2016-03-04 US US15/061,444 patent/US9691739B2/en active Active
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2010147281A5 (ja) | 半導体装置 | |
JP2011086927A5 (ja) | 半導体装置 | |
JP2010135780A5 (ja) | 半導体装置 | |
JP2010283236A5 (ja) | ||
JP2013211537A5 (ja) | ||
JP2009246218A5 (ja) | ||
JP2010135777A5 (ja) | 半導体装置 | |
JP2013236066A5 (ja) | ||
JP2011054949A5 (ja) | 半導体装置 | |
JP2014206936A5 (ja) | ||
JP2010267789A5 (ja) | ||
JP2010087494A5 (ja) | 半導体装置 | |
JP2009194322A5 (ja) | ||
RU2008112657A (ru) | Полупроводниковое устройство | |
JP2010251537A5 (ja) | 半導体集積回路装置 | |
JP2009033145A5 (ja) | ||
JP2011009352A5 (ja) | 半導体装置 | |
JP2013102134A5 (ja) | 半導体装置 | |
JP2013042117A5 (ja) | ||
JP2010135778A5 (ja) | 半導体装置 | |
JP2014170940A5 (ja) | ||
JP2009044154A5 (ja) | ||
JP2016096292A5 (ja) | ||
JP2011014892A5 (ja) | ||
JP2009105311A5 (ja) |