EP1519411A3 - Semiconductor device and method for fabricating the same - Google Patents
Semiconductor device and method for fabricating the same Download PDFInfo
- Publication number
- EP1519411A3 EP1519411A3 EP04022445A EP04022445A EP1519411A3 EP 1519411 A3 EP1519411 A3 EP 1519411A3 EP 04022445 A EP04022445 A EP 04022445A EP 04022445 A EP04022445 A EP 04022445A EP 1519411 A3 EP1519411 A3 EP 1519411A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- metal pattern
- insulating film
- semiconductor device
- fabricating
- same
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title abstract 4
- 239000002184 metal Substances 0.000 abstract 9
- 239000000758 substrate Substances 0.000 abstract 2
- 239000013078 crystal Substances 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003335267 | 2003-09-26 | ||
JP2003335267 | 2003-09-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1519411A2 EP1519411A2 (en) | 2005-03-30 |
EP1519411A3 true EP1519411A3 (en) | 2010-01-13 |
Family
ID=34191523
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP04022445A Withdrawn EP1519411A3 (en) | 2003-09-26 | 2004-09-21 | Semiconductor device and method for fabricating the same |
Country Status (6)
Country | Link |
---|---|
US (2) | US7312530B2 (en) |
EP (1) | EP1519411A3 (en) |
JP (1) | JP4630919B2 (en) |
KR (1) | KR100626923B1 (en) |
CN (1) | CN1601735B (en) |
TW (1) | TWI265581B (en) |
Families Citing this family (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7692315B2 (en) * | 2002-08-30 | 2010-04-06 | Fujitsu Microelectronics Limited | Semiconductor device and method for manufacturing the same |
US7081679B2 (en) * | 2003-12-10 | 2006-07-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and method for reinforcing a bond pad on a chip |
US7241636B2 (en) * | 2005-01-11 | 2007-07-10 | Freescale Semiconductor, Inc. | Method and apparatus for providing structural support for interconnect pad while allowing signal conductance |
US7646087B2 (en) * | 2005-04-18 | 2010-01-12 | Mediatek Inc. | Multiple-dies semiconductor device with redistributed layer pads |
US20060244156A1 (en) * | 2005-04-18 | 2006-11-02 | Tao Cheng | Bond pad structures and semiconductor devices using the same |
JP2007005539A (en) | 2005-06-23 | 2007-01-11 | Seiko Epson Corp | Semiconductor device |
JP2007043071A (en) | 2005-07-06 | 2007-02-15 | Seiko Epson Corp | Semiconductor device |
JP5234239B2 (en) | 2005-07-06 | 2013-07-10 | セイコーエプソン株式会社 | Semiconductor device |
JP4605378B2 (en) | 2005-07-13 | 2011-01-05 | セイコーエプソン株式会社 | Semiconductor device |
JP2007027481A (en) | 2005-07-19 | 2007-02-01 | Seiko Epson Corp | Semiconductor device |
JP2007036021A (en) * | 2005-07-28 | 2007-02-08 | Seiko Epson Corp | Semiconductor device |
JP2007087975A (en) * | 2005-09-16 | 2007-04-05 | Ricoh Co Ltd | Semiconductor device |
US7808117B2 (en) * | 2006-05-16 | 2010-10-05 | Freescale Semiconductor, Inc. | Integrated circuit having pads and input/output (I/O) cells |
US20070267748A1 (en) * | 2006-05-16 | 2007-11-22 | Tran Tu-Anh N | Integrated circuit having pads and input/output (i/o) cells |
US7573115B2 (en) * | 2006-11-13 | 2009-08-11 | International Business Machines Corporation | Structure and method for enhancing resistance to fracture of bonding pads |
JP2008177249A (en) * | 2007-01-16 | 2008-07-31 | Sharp Corp | Bonding pad for semiconductor integrated circuit, manufacturing method for the bonding pad, semiconductor integrated circuit, and electronic equipment |
JP2008258258A (en) * | 2007-04-02 | 2008-10-23 | Sanyo Electric Co Ltd | Semiconductor device |
KR101349373B1 (en) * | 2007-07-31 | 2014-01-10 | 삼성전자주식회사 | Semiconductor device and method of manufacturing a semiconductor device |
US20100072624A1 (en) * | 2008-09-19 | 2010-03-25 | United Microelectronics Corp. | Metal interconnection |
JP2010093161A (en) * | 2008-10-10 | 2010-04-22 | Panasonic Corp | Semiconductor device |
US8084858B2 (en) * | 2009-04-15 | 2011-12-27 | International Business Machines Corporation | Metal wiring structures for uniform current density in C4 balls |
US8278733B2 (en) * | 2009-08-25 | 2012-10-02 | Mediatek Inc. | Bonding pad structure and integrated circuit chip using such bonding pad structure |
US8748305B2 (en) | 2009-11-17 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad structure for semiconductor devices |
JP5383446B2 (en) * | 2009-11-18 | 2014-01-08 | パナソニック株式会社 | Semiconductor device |
US20110156260A1 (en) * | 2009-12-28 | 2011-06-30 | Yu-Hua Huang | Pad structure and integrated circuit chip with such pad structure |
US8659170B2 (en) * | 2010-01-20 | 2014-02-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having conductive pads and a method of manufacturing the same |
KR101046673B1 (en) * | 2010-01-25 | 2011-07-05 | 주식회사 티엘아이 | Bonding pad of semiconductor chip for reducing destroyment |
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US8664113B2 (en) * | 2011-04-28 | 2014-03-04 | GlobalFoundries, Inc. | Multilayer interconnect structure and method for integrated circuits |
US9041204B2 (en) | 2012-03-30 | 2015-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding pad structure with dense via array |
US9699897B2 (en) * | 2012-09-28 | 2017-07-04 | Taiwan Semiconductor Manufacturing Company Limited | Pad structure |
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JP2014212276A (en) * | 2013-04-22 | 2014-11-13 | 日本電波工業株式会社 | Composite electronic component |
US9768221B2 (en) | 2013-06-27 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad structure layout for semiconductor device |
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US20150206855A1 (en) * | 2014-01-22 | 2015-07-23 | Mediatek Inc. | Semiconductor package |
US9245846B2 (en) * | 2014-05-06 | 2016-01-26 | International Business Machines Corporation | Chip with programmable shelf life |
US10804153B2 (en) | 2014-06-16 | 2020-10-13 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method to minimize stress on stack via |
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US9673287B2 (en) * | 2014-12-15 | 2017-06-06 | Infineon Technologies Americas Corp. | Reliable and robust electrical contact |
US10038025B2 (en) | 2015-12-29 | 2018-07-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Via support structure under pad areas for BSI bondability improvement |
JP6557367B2 (en) * | 2016-02-15 | 2019-08-07 | 京セラ株式会社 | Pressure sensor |
US10192832B2 (en) * | 2016-08-16 | 2019-01-29 | United Microelectronics Corp. | Alignment mark structure with dummy pattern |
US10056332B2 (en) * | 2016-09-05 | 2018-08-21 | Renesas Electronics Corporation | Electronic device with delamination resistant wiring board |
CN111584450A (en) * | 2020-05-26 | 2020-08-25 | 四川中微芯成科技有限公司 | IO pad structure for wire bonding |
KR20220058757A (en) | 2020-10-30 | 2022-05-10 | 삼성디스플레이 주식회사 | Display device |
US11308257B1 (en) | 2020-12-15 | 2022-04-19 | International Business Machines Corporation | Stacked via rivets in chip hotspots |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5700735A (en) * | 1996-08-22 | 1997-12-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bond pad structure for the via plug process |
JPH118264A (en) * | 1997-06-13 | 1999-01-12 | Nec Corp | Semiconductor device and its manufacture |
US6143396A (en) * | 1997-05-01 | 2000-11-07 | Texas Instruments Incorporated | System and method for reinforcing a bond pad |
US20010010404A1 (en) * | 1999-03-19 | 2001-08-02 | Ming-Dou Ker | Low-capacitance bonding pad for semiconductor device |
US20020025417A1 (en) * | 2000-08-31 | 2002-02-28 | Chisholm Michael F. | Novel approach to structurally reinforcing the mechanical performance of silicon level interconnect layers |
US20020060362A1 (en) * | 1998-07-31 | 2002-05-23 | Takaaki Miyamoto | Wiring structure in semiconductor device and method for forming the same |
WO2003001595A2 (en) * | 2001-06-25 | 2003-01-03 | Koninklijke Philips Electronics N.V. | Electronic device |
US20030102475A1 (en) * | 2001-12-03 | 2003-06-05 | Samsung Electronics Co., Ltd. | Semiconductor devices with bonding pads having intermetal dielectric layer of hybrid configuration and methods of fabricating the same |
Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6439035A (en) * | 1987-08-04 | 1989-02-09 | Nec Corp | Semiconductor device |
JP2718854B2 (en) | 1992-06-10 | 1998-02-25 | 株式会社東芝 | Semiconductor device |
JP2916326B2 (en) | 1992-06-11 | 1999-07-05 | 三菱電機株式会社 | Pad structure of semiconductor device |
JP3432284B2 (en) * | 1994-07-04 | 2003-08-04 | 三菱電機株式会社 | Semiconductor device |
JP3457123B2 (en) * | 1995-12-07 | 2003-10-14 | 株式会社リコー | Semiconductor device |
US5764485A (en) * | 1996-04-19 | 1998-06-09 | Lebaschi; Ali | Multi-layer PCB blockade-via pad-connection |
US6507989B1 (en) * | 1997-03-13 | 2003-01-21 | President And Fellows Of Harvard College | Self-assembly of mesoscale objects |
KR100267105B1 (en) * | 1997-12-09 | 2000-11-01 | 윤종용 | Semiconductor device with multi-layer pad and manufacturing method |
JPH11261010A (en) * | 1998-03-13 | 1999-09-24 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
US6448650B1 (en) * | 1998-05-18 | 2002-09-10 | Texas Instruments Incorporated | Fine pitch system and method for reinforcing bond pads in semiconductor devices |
US6163074A (en) * | 1998-06-24 | 2000-12-19 | Samsung Electronics Co., Ltd. | Integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein |
US6552438B2 (en) * | 1998-06-24 | 2003-04-22 | Samsung Electronics Co. | Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same |
KR100319896B1 (en) | 1998-12-28 | 2002-01-10 | 윤종용 | Bonding pad structure of semiconductor device and fabrication method thereof |
JP2974022B1 (en) * | 1998-10-01 | 1999-11-08 | ヤマハ株式会社 | Bonding pad structure of semiconductor device |
US6037668A (en) * | 1998-11-13 | 2000-03-14 | Motorola, Inc. | Integrated circuit having a support structure |
JP2000195896A (en) | 1998-12-25 | 2000-07-14 | Nec Corp | Semiconductor device |
US6031293A (en) * | 1999-04-26 | 2000-02-29 | United Microelectronics Corporation | Package-free bonding pad structure |
JP2001085465A (en) | 1999-09-16 | 2001-03-30 | Matsushita Electronics Industry Corp | Semiconductor device |
JP2001203329A (en) | 2000-01-18 | 2001-07-27 | Toshiba Corp | Semiconductor device and its manufacturing method |
JP2001313293A (en) * | 2000-05-01 | 2001-11-09 | Seiko Epson Corp | Semiconductor device |
US6411492B1 (en) * | 2000-05-24 | 2002-06-25 | Conexant Systems, Inc. | Structure and method for fabrication of an improved capacitor |
JP2002016069A (en) | 2000-06-29 | 2002-01-18 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
US6477054B1 (en) * | 2000-08-10 | 2002-11-05 | Tektronix, Inc. | Low temperature co-fired ceramic substrate structure having a capacitor and thermally conductive via |
JP2002118235A (en) * | 2000-10-10 | 2002-04-19 | Mitsubishi Electric Corp | Semiconductor device, method for manufacturing semiconductor, and mask for manufacturing the same |
JP3408527B2 (en) | 2000-10-26 | 2003-05-19 | 松下電器産業株式会社 | Method for manufacturing semiconductor device |
KR100421043B1 (en) | 2000-12-21 | 2004-03-04 | 삼성전자주식회사 | Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein |
CN1175489C (en) | 2001-04-20 | 2004-11-10 | 华邦电子股份有限公司 | Wiring pad with edge-reinforcing structure |
JP3524908B2 (en) * | 2002-01-21 | 2004-05-10 | 株式会社半導体理工学研究センター | Semiconductor device |
US6650010B2 (en) | 2002-02-15 | 2003-11-18 | International Business Machines Corporation | Unique feature design enabling structural integrity for advanced low K semiconductor chips |
US6762466B2 (en) * | 2002-04-11 | 2004-07-13 | United Microelectronics Corp. | Circuit structure for connecting bonding pad and ESD protection circuit |
KR100476900B1 (en) * | 2002-05-22 | 2005-03-18 | 삼성전자주식회사 | Semiconductor integrated circuit device with test element group circuit |
US7023090B2 (en) * | 2003-01-29 | 2006-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding pad and via structure design |
TWI220565B (en) * | 2003-02-26 | 2004-08-21 | Realtek Semiconductor Corp | Structure of IC bond pad and its formation method |
US7026664B2 (en) * | 2003-04-24 | 2006-04-11 | Power-One, Inc. | DC-DC converter implemented in a land grid array package |
US7453158B2 (en) * | 2003-07-31 | 2008-11-18 | Nvidia Corporation | Pad over active circuit system and method with meshed support structure |
JP2008258258A (en) * | 2007-04-02 | 2008-10-23 | Sanyo Electric Co Ltd | Semiconductor device |
-
2004
- 2004-09-21 CN CN2004100826041A patent/CN1601735B/en not_active Expired - Fee Related
- 2004-09-21 EP EP04022445A patent/EP1519411A3/en not_active Withdrawn
- 2004-09-22 US US10/945,902 patent/US7312530B2/en not_active Expired - Fee Related
- 2004-09-23 KR KR1020040076285A patent/KR100626923B1/en not_active IP Right Cessation
- 2004-09-24 TW TW093129046A patent/TWI265581B/en not_active IP Right Cessation
-
2007
- 2007-11-14 US US11/984,127 patent/US7741207B2/en not_active Expired - Fee Related
-
2008
- 2008-07-03 JP JP2008174485A patent/JP4630919B2/en not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5700735A (en) * | 1996-08-22 | 1997-12-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bond pad structure for the via plug process |
US6143396A (en) * | 1997-05-01 | 2000-11-07 | Texas Instruments Incorporated | System and method for reinforcing a bond pad |
JPH118264A (en) * | 1997-06-13 | 1999-01-12 | Nec Corp | Semiconductor device and its manufacture |
US20020060362A1 (en) * | 1998-07-31 | 2002-05-23 | Takaaki Miyamoto | Wiring structure in semiconductor device and method for forming the same |
US20010010404A1 (en) * | 1999-03-19 | 2001-08-02 | Ming-Dou Ker | Low-capacitance bonding pad for semiconductor device |
US20020025417A1 (en) * | 2000-08-31 | 2002-02-28 | Chisholm Michael F. | Novel approach to structurally reinforcing the mechanical performance of silicon level interconnect layers |
WO2003001595A2 (en) * | 2001-06-25 | 2003-01-03 | Koninklijke Philips Electronics N.V. | Electronic device |
US20030102475A1 (en) * | 2001-12-03 | 2003-06-05 | Samsung Electronics Co., Ltd. | Semiconductor devices with bonding pads having intermetal dielectric layer of hybrid configuration and methods of fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
CN1601735B (en) | 2010-06-23 |
CN1601735A (en) | 2005-03-30 |
JP2008235944A (en) | 2008-10-02 |
KR100626923B1 (en) | 2006-09-20 |
JP4630919B2 (en) | 2011-02-09 |
US20080284026A1 (en) | 2008-11-20 |
TW200512857A (en) | 2005-04-01 |
US7312530B2 (en) | 2007-12-25 |
KR20050030571A (en) | 2005-03-30 |
US20050067707A1 (en) | 2005-03-31 |
TWI265581B (en) | 2006-11-01 |
US7741207B2 (en) | 2010-06-22 |
EP1519411A2 (en) | 2005-03-30 |
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