CN1175489C - Wiring pad with edge-reinforcing structure - Google Patents

Wiring pad with edge-reinforcing structure Download PDF

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Publication number
CN1175489C
CN1175489C CNB011166878A CN01116687A CN1175489C CN 1175489 C CN1175489 C CN 1175489C CN B011166878 A CNB011166878 A CN B011166878A CN 01116687 A CN01116687 A CN 01116687A CN 1175489 C CN1175489 C CN 1175489C
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China
Prior art keywords
dendroid
wiring pad
pad
wiring
edge
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Expired - Fee Related
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CNB011166878A
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Chinese (zh)
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CN1381887A (en
Inventor
陈庆宗
林锡聪
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Winbond Electronics Corp
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Winbond Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates to a wiring pad for the encapsulating and the wiring of a semiconductor assembly. The present invention comprises a metal wiring pad and at least one branch-shaped sub structure, wherein the metal wiring pad is formed in an open window region surrounded by the edge of a dielectric layer and is formed above the edge of the dielectric layer; the branch-shaped sub structure is formed on at least one part of the edge of the dielectric layer; the branch-shaped sub structure is formed by metal materials and extends from the bottom of the metal wiring pad in a lateral direction. Because a vertical extension contact surface is formed between a metal wiring pad layer and the dielectric layer arranged in the branch-shaped sub structure, the contact area is enlarged, the adhesive force is enhanced, and the crack formation is effectively stopped and prevented through the discontinuous branch-shaped sub structure at the edge of the dielectric layer.

Description

Wiring pad with insulation intensifying structure
Technical field
The wiring pad that the relevant a kind of semiconductor packages wiring of the present invention is used.
Background technology
During printed circuit board (PCB) or other integrated circuit (IC) encapsulation, the semiconductor subassembly that is provided on the printed circuit board (PCB) can be connected with the external world by a wiring technology respectively.In this technology, provide the particular contact on the conductive layer of semiconductor subassembly outermost therewith of one or more wiring pads.Then, a closing line be engaged to this wiring pad make this semiconductor subassembly therewith IC encapsulation inner lead electrically contact.In general, wiring technology can roughly be divided into two kinds of main types: gold thread/gold goal joint technology and aluminum steel wedge bond technology.This aluminum steel wedge joint technology is widely used in the application of circuit board chip (COB), and wherein said aluminum steel is to be soldered on this wiring pad by ultrasonic oscillation and the pressure that affacts this wedge.Described gold thread/gold goal joint technology generally is to be formed as spherical lead earlier and to finish on the wiring pad by pushing this when an ascending temperature.This aluminum steel wedge type joint technology is generally more inaccurate when setting up bonding station, and more inhomogeneous when applying activating pressure, therefore, with respect to this gold thread/ball bond technology, mainly due to the inhomogeneities of machinery or thermal stress, make its easier problem of peeling off.
When the adhesion strength between any adjacent layer in the multilevel semiconductor assembly can not toughly be enough to resist in the wiring technology when engaging this and being wired to the thermal stress that occurred during this joint sheet and mechanical stress, the problem that this joint peels off just can take place.For example, this can occur between metal bond pads and the polysilicon layer below, between metal level and the dielectric layer, and between dielectric layer and the polysilicon layer, and between barrier layer and the dielectric layer or the like.
Except top the discussion, peeling off or peeling off of joint sheet has been the main unresolved problem that constantly puzzlement comprises the integrated circuit encapsulation technology of wiring technology.Many may being proposed and implementing, prior art references described as follows by settling mode arranged.
United States Patent (USP) the 4th, 060 has disclosed a kind of semiconductor device with multi-layer wiring structure No. 828, and it has an additional through hole that is formed in the wiring of the wiring layer insulating barrier under rebasing.The purpose of this ' 828 patent is to provide one additional and shieldedly electrically contact between wiring pad and other wiring layer in its lower floor; if the exposed portion of feasible wiring pad is corroded and caused when breaking off, additionally electrically contacting still of insulating barrier passed in formation can provide required connection.Yet this ' 828 patent is not directly addressed the wiring pad and is peeled off problem, but the idea that a through hole interconnection structure is provided in the directly insulating barrier under metal level that ' 828 patent is disclosed is peeled off the method for the prior art of problem and is adopted by dealing with the wiring pad, so that a fixed structure to be provided, although the overwhelming majority all is the form of revising.
United States Patent (USP) the 4th, 981 has disclosed for No. 061 and a kind ofly to comprise one and be formed at the semiconductor subassembly that forms first insulating barrier on the main surface of semiconductor substrate of active area.First contact hole is formed on corresponding on the position in first insulating barrier of active area, and first conductive layer is formed in first contact hole and this contact hole around the some of first insulating barrier among.Afterwards, second insulating barrier is formed on first conductive layer and first insulating barrier, and second contact hole is formed on corresponding on the position in second insulating barrier of first conductive layer and be positioned on first contact hole.Then, second conductive layer is formed on second insulating barrier and described second contact hole of filling.At last, a wiring is connected to described second conductive layer that is positioned at the zone on first and second contact hole.With regard to the structure that ' 061 patent is disclosed, the pressure that puts on described second insulating barrier when wiring is that the column structure by first and second conductive layer of filling in first and second contact hole is supported.
United States Patent (USP) the 5th, 309 has disclosed a wiring mat structure No. 025, and it forms on described barrier layer then depositing one first conductive layer on the lower region of semiconductor assembly by deposition one deck barrier layer.Then, described barrier layer of patterning and etching and conductive layer and form a conductive region.In the patent of ' 205, described conductive region is shaped as a lattice shape, and deposits second conductive layer on this conductive region and exposure lower region partly.Therefore the lower region contact of well adhering therewith of this second conductive layer has avoided peeling off of joint sheet.
United States Patent (USP) the 5th, 248 has disclosed a wiring mat structure No. 903, and the wiring pad that it is suffered from when providing a compound wiring pad to alleviate wiring peels off problem.This compound wiring pad comprises that the wiring pad reaches wiring pad on one, and an insulation assembly betwixt.An opening that passes this insulation assembly is provided at least, and it extends to the wiring pad by bottom wiring pad.Described at least one opening is to align with a peripheral region of bottom wiring pad.Provide an electric conducting material to fill described several openings then, and be electrically connected to top and bottom wiring pad.Described at least one opening can be several conductive channels, a circular opening of extending along this peripheral region, or the elongated open of one or more prolongation.
United States Patent (USP) the 5th, 309 has disclosed a kind of improved wiring mat structure No. 025, and it has reduced the problem that the wiring electricity peels off.The wiring pad that ' 025 patent is disclosed has comprised a barrier layer, and by at first depositing the lower region of a barrier layer at the semiconductor assembly, and deposits one first conductive layer again on described barrier layer and form.Then, described barrier layer of patterning and etching and conductive layer are to form a conductive region.Form several conductive regions, each conductive region is isolated from the outside by forming an isolated side wall.One second conductive layer then is deposited over this conductive region and is exposed to partially on the outer lower region.Described second conductive layer has good adhesion with lower region and contacts, thereby avoids peeling off of wiring pad.
United States Patent (USP) the 5th, 707, the technology that has disclosed a kind of improved wiring mat structure and be used for forming this wiring pad for No. 894, the wiring pad that it can reduce between wiring layer and the lower floor peels off problem.The method that is disclosed in ' 894 patent is included in the step that forms several fixed bolsters on the substrate surface in the wiring pad area.Secondly, form one first insulating barrier on this substrate surface and fixed bolster.Form several access openings and pass first insulating barrier, and filled,, so can form a conduction and be connected and fixed pad and one second metal level so cover described first insulating barrier by same material as second metal level.This passage has the area of section little than fixed bolster, makes very little " hook " of being combined to form of the fixed bolster and second metal level among first insulating barrier, so described second metal level (wiring bed course just) is fixed on beneath layer.
United States Patent (USP) the 5th, 874, disclose a kind of zigzag rim openings that in semiconductor structure, forms for No. 356, eliminate the generation of volcano (volcano) defective with the membrane stress in the resistance barrier/adhesive linkage that reduces titanium nitride, titanium nitride wherein takes place from the contact openings layering or peel off.
The scheme of top all prior aries that disclose another one wiring all not to be noted pad peels off the reason of problem.It usually is that the crack of one or more edge parts of the dielectric layer below the corresponding part that is formed at the metal connection pad is caused that co-inventor of the present invention observes the wiring pad of the being found problem of peeling off.In case because thermal stress in the wiring manufacturing process and/or mechanical stress and have the crack produce at the part edge of dielectric layer, it just distributes along the interface between metal connection pad and the dielectric layer, and causes this wiring pad from then on to come off on the semiconductor subassembly at last.When the size of this wiring pad becomes more hour, because the wiring pad problem of peeling off that fractue spacing caused just becomes more serious.
In addition, prior art scheme great majority discussed above comprise and form a plurality of metal filled hole or the passage that completely cut off pass wiring pad that wiring will the connect insulating barrier below partly, but wherein desired temperature can rise quite high.Except the top non-directly by be connected to individually metal level, described a plurality of metal filled passages do not interconnect each other.If described a plurality of metal filled passages are layout suitably not, or wiring is not connected on the designed position, and the inequality of the metal connection bed course in the different metal filling channel is conducted heat to cause and do not wished the thermal stress issues that takes place.United States Patent (USP) the 5th, 248 has disclosed one for No. 903 and has been positioned at the last wiring pad of compound wiring mat structure and a ring-type fixed structure between the wiring pad down.Yet because the big distance between this circulus opposite side, unbalanced heat transfer problem still exists.
Summary of the invention
An object of the present invention is to provide improved wiring pad that a kind of integrated circuit package encapsulation wiring uses and preparation method thereof, it can make the problem of peeling off be reduced to bottom line and can stop the growth in crack, can eliminate potential uneven heat in addition and transmit or the mechanical stress problem.
For achieving the above object, the wiring pad that semiconductor subassembly encapsulation wiring is according to an aspect of the present invention used, be characterized in, it comprises: a metal connection pad is formed in the open window zone that the edge part branch of a dielectric layer centers on and partly is formed on the described edge part of described dielectric layer; And at least one dendroid minor structure, being formed at least a portion edge of described dielectric layer, described at least one dendroid minor structure is formed by a kind of metal material, and extends laterally out from described metal connection pad below.
For achieving the above object, the wiring pad that according to a further aspect in the invention semiconductor subassembly encapsulation wiring is used is characterized in that it comprises: a stepped construction, and it comprises a metal connection bed course, a dielectric layer and is formed on a lower floor on the chip; And a single fixed structure, be formed in the described dielectric layer that is connected to described metal connection pad and described lower floor; Wherein, described single fixed structure comprises several line segments, and they are connected to each other to form described single fixed structure.
For achieving the above object, the method for making a wiring pad on the chip of integrated circuit according to another aspect of the invention is characterized in, described method comprises the following steps: to form a dielectric layer above described wafer and cover on the lower floor; The use photoetching technique forms open window zone and forms at least one dendroid through hole on an edge part of described dielectric layer, and described at least one dendroid through hole is connected on the described open window zone; And deposit a metal material in described open window zone and form a metal connection pad, wherein, described metal material also is deposited in described at least one dendroid through hole and forms at least one the dendroid minor structure that is connected to described metal connection pad.
For achieving the above object, the method at chip surface formation wiring pad in accordance with a further aspect of the present invention is characterized in that described method comprises the steps: to form on the lower floor of a dielectric layer above described chip; Use photoetching technique to form a single master and bore a hole in described dielectric layer, wherein, described single main perforation comprises several line segments, and they are connected to each other to form described single through hole and to be arranged on the radiation direction; Deposit a metal material and form a single fixed structure to described single leading in the perforation, it has the metal filled line segment of several interconnection; And simultaneously or then deposit described metal connection bed course and on described dielectric layer top and with described fixed structure, be connected.
Of the present inventionly have multiple line segment but the metal connection pad of single fixed structure for forming, at first form the surface of a dielectric layer in chip, described chip generally comprises a metal level, a polysilicon layer or even another insulating barrier; Use the traditional photography making sheet described dielectric layer of etching technique etching and form a single through hole with this fixed structure shape; Afterwards, more satisfactory is to use under the identical photoresistance, filling metal material in described through hole by metal deposition; At last, remove photoresistance and form a metal connection pad on the dielectric layer of described fixed structure and sub-fraction.
In wiring pad of the present invention, described at least one dendroid minor structure is prolonged from the marginal portion of metal connection pad and is extended among the adjacent dielectric layer, form one or more dendroid through holes by first edge, be filled metal material again and be formed by connecting with the edge of metal connection pad along dielectric layer.
In wiring pad of the present invention, at least one dendroid through hole is formed at the marginal portion of dielectric layer, and they are connected to and therefore become an extension from the wiring pad open area (or " window area ") of (or tributary) reservation to the wiring pad.This dendroid through hole can form in formation connects the identical shielding etching step of electricity pad open area.Afterwards, a wiring pad metal level forms by deposition.Described dendroid through hole can give filling with tungsten plug, perhaps fills with other metal material.Yet, because the width of dendroid through hole generally is very little, be deposited on general and other metal fusion of metal material of this dendroid through hole sidewall, therefore cause whole dendroid minor structure all to be filled into this top surface.During wiring pad layer metal deposition, a ledge also is formed at two location between this dendroid minor structure and top thereof on the dielectric layer top.Covered by protective layer because described ledge is most, so in general do not need planarization process.
In all preferred embodiments of the present invention, this dendroid minor structure has " ten " word shape, and it is long partly perpendicular to the edge of wiring pad, and short then is in parallel partly.The cross dendroid minor structure of this quadrature is the most effective geometry to stoping the crack to be grown up, and therefore can the most effectively stop in the wiring process forming distribution of cracks because of height vibrations and/or thermal stress at the dielectric layer fringe region.Array that comprises several such minor structures can along a part of of single or a plurality of edges of wiring pad or whole edge forms.If necessary, the second layer of this dendroid minor structure can be from the end of the dendroid minor structure of ground floor grow up (just extending).
Provide single fixed structure in wiring mat structure of the present invention, it is imbedded within the dielectric layer and with a lower floor and contacts, and described lower floor can be metal level, polysilicon layer, or other has the non-conduction or the semiconductor layer of excellent adhesion to fixed structure.Disclosed single fixed structure has comprised several interconnected line segments (they can be a curve or a straight line).The line segment of interconnection has identical thickness, and generally also has identical width.This fixed structure provides the reinforcement contact surface with lower floor, so the metal connection cushion material provides than strong adhesive force for this reason.In addition, this fixed structure also forms the contact surface of strengthening (it is a vertical extent) between metal connection mat structure and dielectric layer, so also can strengthen adhesive force therebetween.
Single fixed structure of the present invention also can have different shapes, and for example square wave ring, a tree, a ruling structure, a curved structure, a serpentine configuration, a helicoidal structure, a labyrinth-like structure or the like are opened or sealed to the coil of an open loop structure, an enclosed ring (both all have radial whiskers for this), an annular or rectangle.A key element of the present invention is that described line segment is connected to each other the uneven hot arraign topic that multiple fixed structure was experienced of being eliminated prior art with the fixed structure that forms single integral body.
Because the present invention adopts the dendroid minor structure, form the contact surface that extends between metal connection bed course wherein and the dielectric layer, it for this reason the metal connection pad contact area and the corresponding adhesive force of an increase are provided; This dendroid minor structure produces discontinuous in the marginal portion of dielectric layer, it can stop and therefore stop to be formed at this crack growth effectively.Like this, by the crack being stopped to grow up and provides the adhesive force of enhancing, the problem that can effectively prevent the wiring pad to peel off.The present invention has also eliminated potential uneven the heat transfer or the mechanical stress problem.In addition, because wiring mat structure of the present invention need not form any passage or fixed structure on the insulating barrier in the zone under the wiring pad, therefore make easily thereby save cost.
Another benefit of the single fixed structure of multiple line segment of the present invention is, because the difference of thermal coefficient of expansion, will make the thermal expansion meeting of adjacent segments of this single fixed structure with respect to producing an inlay resultant force (clamping force) on the dielectric layer of sealing.This inlay resultant force more provides a stability force to make that this wiring pad can not peel off in the wiring technical process.
Be clearer understanding purpose of the present invention, characteristics and advantage, below in conjunction with accompanying drawing to of the present invention preferable
Embodiment is elaborated.
Description of drawings
Fig. 1 shows a kind of end view that does not have the traditional wired pad of fixed structure;
Fig. 2 shows a kind of end view with existing wiring pad of multiple fixed structure;
Fig. 3 is for showing the vertical view according to a preferred embodiment of the present invention wiring pad, and it comprises one along four sides of wiring pad open area and dendroid minor structure array externally;
Fig. 4 is the cross-sectional view of this wiring mat structure of demonstration of getting along Fig. 3 center line 3-3 ' place;
Fig. 5 is the cross-sectional view of this wiring mat structure of demonstration of getting along Fig. 3 center line 4-4 ' place;
Fig. 6 is the cross-sectional view of this wiring mat structure of demonstration of getting along Fig. 3 center line 5-5 ' place;
Fig. 7 is the vertical view that shows the wiring pad of second preferred embodiment according to the present invention, and it has comprised one only along a side of this wiring pad open area and dendroid minor structure array externally;
Fig. 8 is the vertical view that shows the wiring pad of the 3rd preferred embodiment according to the present invention, and it has comprised one along a whole side of wiring pad open area and two part sides adjacent and dendroid minor structure array externally;
Fig. 9 is the vertical view that shows the wiring pad of the 4th preferred embodiment according to the present invention, wherein said dendroid minor structure also since then partly long the or short end end partly of dendroid minor structure increase a part of and branches extending and going out further;
Figure 10 is the vertical view that shows the wiring pad of the 5th preferred embodiment according to the present invention, and wherein said dendroid minor structure also prolongs linear portions from it and connects a snake shape more partly and extend out;
Figure 11 shows that dendroid minor structure of the present invention can be any shape arbitrarily, and it can include one and prolong curved section, and prolong straightway, one and be connected to the huge part of this metal connection pad or the combination of these forms by a straightway;
Figure 12 shows the end view with wiring pad of single fixed structure of the present invention;
Figure 13 shows the plane graph with wiring pad of single snakelike fixed structure of the present invention;
Figure 14 shows the plane graph with wiring pad of single square-wave form fixed structure of the present invention;
Figure 15 shows the plane graph with wiring pad of the annular fixed structure of single opening of the present invention;
Figure 16 shows the plane graph with wiring pad of single tree-shaped fixed structure of the present invention;
Figure 17 shows the plane graph with wiring pad of single coil shape fixed structure of the present invention;
Figure 18 shows the plane graph with wiring pad of single ruling fixed in shape structure of the present invention;
Figure 19 shows the plane graph with wiring pad of single spiral-shaped fixed structure of the present invention;
Figure 20 shows the plane graph with wiring pad of identical single snakelike fixed structure as shown in figure 13 of the present invention, and it also comprises a dendroid minor structure array that extends into the edge part of dielectric layer in addition;
Figure 21 shows the plane graph with wiring pad of identical ruling fixed in shape structure as shown in figure 18 of the present invention, and it has also comprised a dendroid minor structure array that extends into the edge part of dielectric layer in addition;
Figure 22 shows the plane graph with wiring pad of spiral-shaped fixed structure as shown in figure 19 of the present invention, and it has also comprised a dendroid minor structure array that extends into the edge part of dielectric layer in addition;
Figure 23 shows of the present inventionly to have a sealing rectangular ring fixed structure and one and extend into the plane graph of wiring pad of dendroid minor structure array of the edge part of dielectric layer in the straight-flanked ring place since then.
Embodiment
The present invention has disclosed the wiring pad that wiring is used during the integrated circuit package encapsulation operation, and it has been eliminated or has reduced to bottom line to the wiring pad problem of peeling off that the major general has been regarded as reducing a main cause of production qualification rate.Wiring pad of the present invention is made quite easily and escapable cost, and it has wide range of applications, and promptly can be applicable to by the simplest to the most complicated structure.Another advantage of wiring pad of the present invention is, except the adhesive force that reinforcement can be provided, it has also eliminated multilayer fixed structure incident potential unbalanced thermal stress of institute and the mechanical stress problem of using the prior art design, and grows up in the crack that can stop to be formed on the marginal portion of the dielectric layer that is adjacent to the wiring pad.
Fig. 1 is an example schematic, and it shows a kind of end view that does not have the traditional wired pad of fixed structure.Different with the design of many prior aries is, the present invention can advantageously be implemented in various wiring pad structure, by the simplest to the most complicated.As shown in the figure, a wiring pad 10 is formed directly on the polysilicon layer 2.In general, extend described wiring pad metal level 1 forming an overhang 3, and provide an extra adhesive force between the two at this in the top of described dielectric layer 4.In wiring operating period, the crack can be developed under this overhang.Consequently, when vibrations or thermal stress is when having exceeded the restriction of adhesive force, this wiring pad metal level 1 just can peel off.
Most wiring pad design that is disclosed in the prior art all attempts will go to alleviate the problem of peeling off of wiring pad, they once used general concept comprise following step: (1) deposits a dielectric layer on a metal or polysilicon layer, (2) form several metal filled passage or fixtures in insulating barrier, (3) are forming wiring pad metal with metal filled passage or the contacted insulating barrier of fixture top.Fig. 2 is that illustration is intended at one stroke, and it shows a kind of end view with existing wiring pad of multiple fixed structure.This metal connection pad 103 is connected to lower floor 101 by several fixed structures 104 that are imbedded under the dielectric layer 102.In wiring operating period, heat is to be sent to this fixed structure by wiring 105.As discussed above, the scheme of all prior aries discussed above all comprises forming and passes multi-metal filler opening or the passage that wiring will be adhered to the insulating barrier of wiring pad under partly on it basically, and wherein to rise expection can be quite high to temperature.Except non-directly its top be connected to individually through them metal level, the passage that described multi-metal is filled does not interconnect.If the multi-metal filling channel is not applied on the designed position without suitable layout or wiring, the inhomogeneous heat transmission that the metal connection bed course in the different metal filling channel is sent just can be taken place.Because the everywhere all is that this unbalanced hot transmission will cause undesirable thermal stress issues according to the ratio reduction.And uneven thermal stress and/or mechanical stress will cause the wiring pad to peel off problem.
In wiring pad of the present invention, form a dendroid minor structure at least, extend in the adjacent dielectric layers from the edge part of metal connection pad.When enforcement is of the present invention, form the metal connection pad to cover each different layers, for example polysilicon layer, multi-crystal silicification metal level, dielectric layer, barrier layer or additional metals layer.This dendroid minor structure is to form one or more dendroid through holes and form by at first extending internally from the edge of dielectric layer.Afterwards, described dendroid hole is filled by metal material, has formed the dendroid minor structure of one or more correspondences so be interconnected to the edge of metal connection pad.
As discussed above, in the present invention, at least form a dendroid minor structure in the edge part of dielectric layer, form the extension part of the edge or the branch of wiring pad open area (or " window area ") after it is connected to and is regarded as to remain in by depositing metal layers.In general, the dendroid through hole in the edge part of dielectric layer is that identical shielding etching step when being formed by wiring pad open area is formed.Afterwards, wiring pad metal level generally adopts chemical vapour deposition technique to form.And described dendroid minor structure can partly be filled by metal material; all the other are partly then follow-up is filled by protective layer; because the width of in general described dendroid minor structure is very little; so the metal material that is deposited on this dendroid minor structure sidewall will mix, therefore caused the whole dendroid through hole in the dielectric layer to be filled into top surface at least fully.Another selection is to fill this dendroid minor structure with tungsten plug.This need to select an additional step.During the same metal deposition process, a metal ledge also can be formed on the top that can be done the dielectric layer edge part of burying this dendroid minor structure.Because described overhang is most possibly covered by protective layer, so generally be not need planarization process.
Preferably, this dendroid minor structure has " ten " word shape, and is long partly short partly then parallel with it perpendicular to the edge of wiring pad.This criss-cross dendroid minor structure is preferable, because it is the most effective structure with regard to the growth that stops the crack, therefore can stop most effectively because the effect of the vibrations of the height of wiring and/or thermal stress and in the growth in the formed crack, edge part of dielectric layer during the wiring process.If necessary, can form the dendroid minor structure of the second layer, from the weak point of the dendroid minor structure of ground floor or long part place extend.According to the seriousness of forcing stress, perhaps need not form the dendroid minor structure along four edges of wiring pad.Only along the whole length at a part of or single edge at single edge, or their merging and to form dendroid minor structure array also be very suitable under many situations.
The present invention will give more clearly describing now by consulting following specific embodiment.Be noted that purpose that following preferred embodiment proposes just in order to reach explanation for example, rather than in order to limit the present invention.
Embodiment one
Fig. 3 is the vertical view that has shown according to the wiring pad of a preferred embodiment of the present invention, the outside of wiring pad 100 and comprise dendroid minor structure 101 arrays of " ten " font along its four side.It is vertical that each dendroid minor structure has one long section 102 edge 103 with wiring pad 100, and a short section 111 is parallel with the edge 103 of wiring pad 100.Described dendroid minor structure 101 is formed among the dielectric layer 104.One little edge part 105 of described dendroid minor structure 101, dielectric layer 104 and wiring pad is covered by protective layer 106.One gold thread/107 in ball is to join on this wiring pad 100.Dotted line 108 has been pointed out the edge of the overhang of wiring pad 100.This gold thread/ball also can be replaced by aluminium.
Fig. 4 is the cross-sectional view of the demonstration wiring mat structure got along Fig. 3 center line 3-3 ' place, and it is to stretch along long section 102.In the present embodiment, the thickness of described wiring pad 100 is identical with the thickness of dielectric layer 104, and the simple extension part that the long section 102 of dendroid minor structure rises for 103 places, edge of wiring pad 100.Fig. 4 shows a very little overhang 109, and its end from the part of the length of wiring pad extends and forms, and is deposited on the top of dielectric layer.In this example, lower floor is a polysilicon layer, yet as discussed above, it can be a dielectric layer, a barrier layer, a metal compound layer (for example titanium nitride, tungsten silicide, titanium silicide etc.) or other metal level.
Fig. 5 is the cross-sectional view of the demonstration wiring mat structure got along Fig. 3 center line 4-4 ' place, and it crosses short section 111.Metal connection bed course 100 extends from the edge of wiring pad, fills described through hole and is deposited on the top of described dielectric layer, so become this outstanding some.
Fig. 6 be along Fig. 3 center line 5-5 ' got cross-sectional view.This is partly in general same as shown in Figure 1, the sidewall of the soaring described dielectric layer of wherein said metal connection bed course, and on described dielectric layer, form an overhang 109.Because this embodiment of the present invention does not comprise any fixed structure in the wiring pad area, just can before layer metal deposition, remove so be used to form the photoresistance of dendroid through hole in dielectric layer in advance.Allow described outstanding formation like this.If do not remove photoresistance when metal deposition, this overhang just can not form so.
Embodiment two
Wiring pad among the embodiment two except the dendroid minor structure only along a side of wiring pad forms, basic identical with embodiment one, as shown in Figure 7.
Embodiment three
Wiring pad among the embodiment three except the dendroid minor structure only along a whole side of wiring pad and partly along two adjacent side forms, identical with embodiment one, as shown in Figure 8.
Embodiment four
Fig. 9 shows that described dendroid minor structure is by increasing to the end of the dendroid minor structure part of ground floor and further branch and going out of line segment.
Figure 10 shows that described dendroid minor structure partly prolongs linear portions and extends out in it by increasing by a snake shape.
Figure 11 one exemplifies schematic diagram, has shown that described dendroid minor structure can be a shape arbitrarily.The main purpose of described dendroid minor structure be to go to provide the extensional surface that adheres to and and then improve its shearing, and cause a discontinuous place, to stop the growth in the crack that forms owing to stress in the edge part of dielectric layer.It can comprise a prolongation curved section, a prolongation straightway, is connected to the huge part of described metal connection pad or their combination by a straightway.In order effectively to stop growth perpendicular to crack on the direction at wiring pad edge, be preferably except line segment perpendicular to wiring pad edge direction, described dendroid minor structure comprises a straightway at least on the direction that is parallel to wiring pad edge.
In addition, the present invention has also disclosed a kind of link pad, can be used for wiring usefulness during the integrated circuit package encapsulation operation, and can not introduce other unnecessary problem.One of advantage of wiring pad of the present invention is that it has been eliminated to follow in the employed isolation multi-metal of existing wiring pad and fills the potential uneven heat conduction that fixture lived through.And single fixed structure of the present invention can be modified and one or more dendroid minor structures are provided, and extra adhesive force can be provided whereby and can effectively stop to be formed on the growth in the crack on the dielectric layer edge part that is adjacent to the wiring pad.
Figure 12 is an example schematic, and it is to show the end view with wiring pad of single fixed structure 201 of the present invention.In wiring pad of the present invention, be different from any prior art expansion wiring pad provide single fixed structure, its be embedded in dielectric layer in and contact with lower floor, described lower floor can be non-conduction or the semiconductor layer that a polysilicon layer or other and metal material have good adhesion.The single fixed structure that is disclosed in the present invention has comprised several interconnected line segments (it can be curve or straight line).Described interconnected line segment all has identical thickness, and generally has identical width.This fixed structure provides the reinforcement contact surface with bottom, so as to provide and metal material between than strong adhesive force.In addition, this fixed structure also forms the contact surface of strengthening (it is a vertical extent) between metal connection pad and dielectric layer, so also strengthened adhesive force therebetween.
Single fixed structure of the present invention also can have different shapes, for example the coil of an open loop structure, an enclosed ring (both all have radial whiskers for this), an annular or rectangle, an open or sealing square wave ring, a tree, a ruling structure, a curved structure, a serpentine configuration, a helicoidal structure, fixed structure and eliminated the uneven hot arraign topic that multiple fixed structure experienced of prior art.
Another benefit of the single fixed structure of multiple line segment of the present invention is, because the difference of thermal coefficient of expansion, will make the thermal expansion meeting of adjacent segments of this single fixed structure with respect to producing an inlay resultant force (clamping force) on the dielectric layer of sealing.This inlay resultant force also provides a stability force to make that this wiring pad can not peel off in the wiring technical process.Transmit in order to be fit to balance heat, this single fixed structure must allow to make multiple obstruction (for example fixed structure of a coil shape) on the radiation direction, or comprises several line segments (a for example ring with whiskers) in radial direction.
Of the present inventionly have multiple line segment but be the metal connection pad of single fixed structure for forming, at first form a dielectric layer on chip surface, generally on silicon substrate, comprise a metal level, a polysilicon layer, or or even another insulating barrier.Use traditional film mechanical etching technique to come the described dielectric layer of etching and form single through hole with this fixed structure shape.Afterwards, be preferably and use identical photoresistance, fill metal material in described through hole by metal deposition.Remove photoresistance at last and form a metal dielectric layer on the dielectric layer of this fixed structure and sub-fraction.
The present invention can further also be improved with one or more dendroid minor structures by means of the fixed structure edge part.It can be finished from one or more branch shape through holes of the edge part of fixed structure by forming extension simply.Described dendroid through hole just is filled metal material between the fixed structure depositional stage.
Embodiment 5
Figure 13 is that illustration is intended at one stroke, and it is to show the plane graph with wiring pad of single snakelike fixed structure 201a of the present invention, and it is formed under the metal connection pad 103 and is buried among the dielectric layer.As mentioned above, be different from the existing fixed structure that comprises the fixture of several isolation, described snakelike fixed structure comprises the single structure of several interconnected line segments.Each line segment can be counted as the arbitrary part between the bending section of this snakelike line segment fixed structure.
Embodiment 6
Figure 14 is that illustration is intended at one stroke, and it is to show the plane graph with wiring pad of single square-wave form fixed structure 201b of the present invention.
Embodiment 7
Figure 15 is an illustration intention at one stroke, and it is the plane graph that shows the wiring pad of the annular fixed structure of single opening with whiskers 201c of the present invention.Described whiskers can allow and thermal source between preferable hot link is arranged.
Embodiment 8
Figure 16 is that illustration is intended at one stroke, and it is to show the plane graph with wiring pad of single tree-shaped fixed structure 201d of the present invention.
Embodiment 9
Figure 17 is that illustration is intended at one stroke, and it is to show the plane graph with wiring pad of single coil shape fixed structure 201e of the present invention.
Embodiment 10
Figure 18 is that illustration is intended at one stroke, and it is to show the plane graph with wiring pad of single grid line fixed in shape structure 201f of the present invention.
Embodiment 11
Figure 19 is that illustration is intended at one stroke, and it is to show the plane graph with wiring pad of single helical form fixed structure 201g of the present invention.This line segment can be as the curved section in the spiral.
Embodiment 12
Figure 20 is that illustration is intended at one stroke, it is to show the plane graph with wiring pad of an identical single serpentine shaped fixed structure 201a as shown in figure 13 of the present invention, except it also comprises an edge dendroid minor structure 301a array partly that extends into dielectric layer.
Embodiment 13
Figure 21 is that illustration is intended at one stroke, it is to show the plane graph with wiring pad of a same mesh wire shaped fixed structure 201f as shown in figure 18 of the present invention, except it also comprises a dendroid minor structure 301f array that extends into the dielectric layer edge part.
Embodiment 14
Figure 22 is an illustration intention at one stroke, and it is to show the plane graph with wiring pad of same-handed fixed in shape structure 201g as shown in figure 19 of the present invention, except it also comprises a dendroid minor structure 301g array that extends into the dielectric layer edge part.
Embodiment 15
Figure 23 is an illustration intention at one stroke, and it is to show a sealing rectangular ring fixed structure 201h and one extend to the dendroid minor structure 301h array of dielectric layer edge part from straight-flanked ring the plane graph of wiring pad that has of the present invention.
Compare with the wiring pad design of prior art, dendroid minor structure of the present invention has two advantages.The first, the extension contact surface that newly causes in the dendroid minor structure forms the contact area through strengthening, and the adhesive force that therefore strengthens.But the more important thing is that this dendroid minor structure has generated a discontinuous place in the dielectric layer edge part, when suitable layout, it can effectively stop also thereby the growth in the crack that stops having formed.As discussed previously, the growth in crack is to cause the wiring pad to peel off the one of the main reasons of problem.By the growth that stops this crack and the adhesive force of enhancing is provided, wiring pad of the present invention has been proved to be and can have effectively prevented the wiring pad to peel off problem.In addition, disclosed dendroid minor structure can be applied on many structures.For example, it can be used on the expansion wiring pad of that prior art with adding.
The present invention is illustrated by preferred embodiment; person skilled in the art person can propose all conspicuous equivalence variations by the prompting of instructing previously spirit according to the present invention and replace with equivalence; yet these equivalences change and equivalent replacement all should be included in the scope of patent protection of the present invention.

Claims (27)

1. wiring pad of using in semiconductor subassembly encapsulation wiring is characterized in that it comprises:
One metal connection pad is formed in the open window zone that the edge part branch of a dielectric layer centers on and partly is formed on the described edge part of described dielectric layer; And
At least one dendroid minor structure is formed at least a portion edge of described dielectric layer, and described at least one dendroid minor structure is formed by a kind of metal material, and extends laterally out from described metal connection pad below.
2. wiring pad as claimed in claim 1, it is characterized in that, described dendroid minor structure comprises that one prolongs curved portion, one prolongs straight line portion, one extension that partly is connected to described metal connection pad by a straight line is partly: one tilt partly, J-shaped partly, L shaped part or a branch partly, or the combining structure of described each several part.
3. wiring pad as claimed in claim 1 is characterized in that, being shaped as rectangle and four edges are arranged of described metal connection pad.
4. wiring pad as claimed in claim 3 is characterized in that, it comprises respectively along at least one array of the formed described dendroid minor structure at least one edge of described metal connection pad.
5. wiring pad as claimed in claim 3 is characterized in that, it comprises along the single array of the formed described dendroid minor structure in whole edge of described metal connection pad.
6. wiring pad as claimed in claim 5 is characterized in that, also comprises the additional arrays of at least one part along the formed described dendroid minor structure of a neighboring edge of described metal connection pad.
7. wiring pad as claimed in claim 1 is characterized in that, described dendroid minor structure comprises a first and a second portion, and they are with greater than 0 degree but intersect less than predetermined angulars of 180 degree.
8. wiring pad as claimed in claim 1 is characterized in that, also comprises a ledge, extends and is covered on the marginal portion of described dielectric layer from the metal connection pad.
9. wiring pad as claimed in claim 1, it is characterized in that, described dendroid minor structure is cross shaped head, and it comprises one first part at the described metal connection pad edge that is connected perpendicular to described dendroid minor structure, and a second portion parallel with described edge.
10. a method of making a wiring pad on the chip of integrated circuit is characterized in that described method comprises the following steps:
Form a dielectric layer above described wafer and cover on the lower floor;
The use photoetching technique forms open window zone and forms at least one dendroid through hole on an edge part of described dielectric layer, and described at least one dendroid through hole is connected on the described open window zone; And
Deposit a metal material in described open window zone and form a metal connection pad, wherein, described metal material also is deposited in described at least one dendroid through hole and forms at least one the dendroid minor structure that is connected to described metal connection pad.
11. method of on the chip of integrated circuit, making the wiring pad as claimed in claim 10, it is characterized in that, described dendritic through hole comprises that one prolongs curved portion, one prolongs straight line portion, one partly is connected to the huge part of described metal connection pad by a straight line: one tilt partly, J-shaped partly, L shaped part or a branch partly, or the combination of described each several part.
12. method of making the wiring pad on the chip of integrated circuit as claimed in claim 10 is characterized in that the shape in described open window zone is rectangle and four edges are arranged.
13. method of making the wiring pad on the chip of integrated circuit as claimed in claim 12 is characterized in that, at least one array of described dendroid through hole is to form along at least one edge in described open window zone respectively.
14. method of making the wiring pad on the chip of integrated circuit as claimed in claim 12 is characterized in that the single array of described dendroid through hole is to form along the whole edge in described open window zone.
15. method of making the wiring pad on the chip of integrated circuit as claimed in claim 14 is characterized in that, at least one additional arrays part of described dendroid through hole forms along the neighboring edge in described open window zone.
16. method of on the chip of integrated circuit, making the wiring pad as claimed in claim 10, it is characterized in that, described dendroid through hole form comprise extension from described dendroid through hole described first partly or at least one extention of an end of described second portion.
17. method of making the wiring pad on the chip of integrated circuit as claimed in claim 10 is characterized in that the step of described deposit metallic material forms a ledge, it extends and covers the marginal portion of described dielectric layer from described metal connection pad.
18. method of on the chip of integrated circuit, making the wiring pad as claimed in claim 10, it is characterized in that, described through hole has one first partly, the described open window edges of regions that it is connected perpendicular to described dendroid through hole, and one second partly, it is parallel to the edge in described open window zone.
19. an integrated circuit that comprises the wiring pad, described wiring pad comprises:
One metal connection pad is formed in the open window zone that the edge part branch of a dielectric layer centers on; And
At least one dendroid minor structure is formed at the marginal portion of described dielectric layer, and described at least one dendroid minor structure is formed by a metal material, and extends from the edge part of described metal connection pad in described open window zone.
20. integrated circuit as claimed in claim 19, it is characterized in that, described dendritic minor structure comprises that one prolongs curved portion, one prolongs straight line portion, one partly is connected to the huge part of described metal connection pad by a straight line: one tilt partly, J-shaped partly, L shaped part, or one branch partly, or the combination of described each several part.
21. integrated circuit as claimed in claim 19 is characterized in that, the shape of described wiring pad is rectangle and four edges is arranged.
22. integrated circuit as claimed in claim 21 is characterized in that, described wiring pad comprises respectively along at least one edge of described wiring pad and at least one array of the described dendroid minor structure that forms.
23. integrated circuit as claimed in claim 21 is characterized in that, described metal connection pad comprises the single array of the described dendroid minor structure that forms along the whole edge of described wiring pad.
24. integrated circuit as claimed in claim 23 is characterized in that, at least one additional arrays of the described dendroid minor structure that comprises that part forms along a neighboring edge of described wiring pad is paid somebody's debt and expected repayment later in described wiring.
25. integrated circuit as claimed in claim 19 is characterized in that, described dendroid minor structure comprises at least one first and at least one second portion, they with greater than 0 the degree but less than 180 the degree predetermined angulars and intersect.
26. integrated circuit as claimed in claim 19 is characterized in that, described wiring is paid somebody's debt and expected repayment later and is comprised a ledge, extends from described metal connection pad place and is covered on the marginal portion of described dielectric layer.
27. integrated circuit as claimed in claim 19 is characterized in that, described dendroid minor structure has one first part at the described metal connection pad edge that is connected perpendicular to described dendroid minor structure, and a second portion parallel with described edge.
CNB011166878A 2001-04-20 2001-04-20 Wiring pad with edge-reinforcing structure Expired - Fee Related CN1175489C (en)

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