CN1797726A - Semiconductor structured chip embedded structure of base plate and method of preparation - Google Patents
Semiconductor structured chip embedded structure of base plate and method of preparation Download PDFInfo
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- CN1797726A CN1797726A CNA2004101016380A CN200410101638A CN1797726A CN 1797726 A CN1797726 A CN 1797726A CN A2004101016380 A CNA2004101016380 A CN A2004101016380A CN 200410101638 A CN200410101638 A CN 200410101638A CN 1797726 A CN1797726 A CN 1797726A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The method provides a structure possessing first loading plate and second loading plate with a through opening. Non-circuit surface of semiconductor chip is placed on the first loading plate and accommodated in the opening of the second loading plate. Dielectric layer is formed between the chip and surface of the second loading plate, and the dielectric is filled in the opening. Blind holes are formed on the dielectric to expose electrode pads. Being formed on surface on the dielectric layer and inner part, circuit layer and blind holes are possible to connect to electrode pads of chips. Being setup on surface of circuit layer, chips on loading plate are connected to outer devices. The invention improves warp issue of semiconductor device, increases effect of heat elimination, quality of chip and yields as well as saves cost.
Description
Technical field
The invention relates to a kind of chip buried base plate structure and method for making of semi-conductor packaging, particularly about the semiconductor package structure and the method for making thereof of a kind of integral chip and bearing part.
Background technology
Flourish along with electronic industry, electronic product is also gradually to multi-functional, high performance R﹠D direction development.For satisfying the encapsulation requirement of semiconductor package part high integration (Integration) and microminiaturized (Miniaturization), the circuit board (Circuit board) that provides a plurality of masters, passive device and circuit to connect also develops into multi-layer sheet (Multi-layer board) by lamina gradually, under limited space, cooperate highdensity integrated circuit (Integrated circuit) demand, enlarge available wiring area on the circuit board by interlayer interconnection technique (Interlayer connection).
The conducting wire number of plies and component density raising because of circuit board, the heat that the operation of Highgrade integration (Integration) semiconductor chip produces also can significantly increase, these heats are if untimely discharge can cause semiconductor package part overheated, the serious threat chip life-span.At present, ball grid array (BGA) structure reaches will needing of can't having met more than the high frequency 5GHz electrically and dispel the heat more than more number of pins (1500pin).Ball grid array (FCBGA) structure of covering crystalline substance then can be used for more number of pins and reaches the more product of high frequency, but whole packaging cost height, and still have many restrictions technically, especially electrically connecting part, because the environmental protection demand, electrically connect material, for example the forbidding of the lead of soldering tin material (Pb) etc., but after being to use other substitution material, quality wild effect electrical, mechanical transitivity has appearred.
For this reason, new solution is that semiconductor is directly imbedded substrate.As shown in Figure 1, be United States Patent (USP) the 6th, 709, the radiating semiconductor packer of No. 898 propositions.As shown in the figure, this semiconductor package part comprises a heating panel 102, and this heating panel 102 has at least one recess 104; Semiconductor chip 114, the non-action face 118 of this semiconductor chip 114 are to connect by a heat conduction sticky material 120 to put in this recess 104; One circuit layer reinforced structure 122 is to be formed on this heating panel 102 and this semiconductor chip 114 by increasing a layer technology.
See also Fig. 2, it is the cross section view of this heating panel 102, and as shown in the figure, the recess 104 of this heating panel 102 extends to this certain perforate degree of depth in heating panel 102 inside from the upper surface of this heating panel 102.
See also Fig. 3, the metal material that is used to support the heating panel 102 of these semiconductor chip 114 elements is single metal material, though can form earlier by the mode that etches partially (half etching) and connect the recess 104 of putting semiconductor chip 114, but because of etched uniformity wayward, each recess 104 degree of depth of these heating panel 102 justifying faces are differed, can't form burnishing surface, the implantation and the contact that are unfavorable for semiconductor element connect, its height and the more difficult control of uniformity, even can influence follow-up operation quality and electric connection reliability of carrying out the circuit layer reinforced structure.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of chip buried base plate structure and method for making of semi-conductor packaging, simultaneously integrating semiconductor chip and bearing part thereof.
Another purpose of the present invention is to provide a kind of chip buried base plate structure and method for making of semi-conductor packaging, can promote the operation acceptance rate of chip embedding bury at bearing part.
Another object of the present invention is to provide a kind of chip buried base plate structure and method for making of semi-conductor packaging, can evenly control the planarization that bearing part and chip connect the face of putting.
Another object of the present invention is to provide a kind of chip buried base plate structure and method for making of semi-conductor packaging, can promote follow-up reliability of carrying out circuit layer reinforced structure operation quality and electric connection.
Another object of the present invention is to provide a kind of chip buried base plate structure and method for making of semi-conductor packaging, but the prying problem of improved semiconductor device.
Another object of the present invention is to provide a kind of chip buried base plate structure and method for making of semi-conductor packaging, can promote the heat dissipation of chip.
For reaching above-mentioned and other purpose, the invention provides a kind of chip buried base plate structure and method for making of semi-conductor packaging, this method for making may further comprise the steps: at first, one bearing structure is provided, this bearing structure has first loading plate and is formed directly into second loading plate on this first loading plate, and this second loading plate has at least one perforate that runs through; Then, semiconductor chip at least connect put on this first loading plate and be accommodated in the perforate of this second loading plate, the surface of this semiconductor chip is formed with a plurality of electrode pad; Subsequently, carry out circuit and increase a layer operation, form a dielectric layer at this chip and second loading plate surface, and dielectric layer material is filled in the gap of this second loading plate perforate and chip; And in this dielectric layer, be formed with blind hole, expose the electrode pad of this chip; Forming patterned line layer on this dielectric layer and in this blind hole, forming conductive blind hole, make this line layer can be electrically connected to the electrode pad of this chip at last.
In addition, when finishing this line layer that increases layer, also can on this line layer, cover a resistance layer, then etching removes and before connects first loading plate of putting chip, this chip back can directly be exposed outside, can promote radiating effect by further directly external other heat abstractor, further reduce the whole height of assembling structure simultaneously, effectively reach compact purpose.
Moreover, when finishing this first line layer that increases layer, also can on this line layer, cover a resistance layer, then remove previous confession and connect first loading plate of putting chip, expose outside chip, the bearing bed of this chip exposed surface and homonymy is carried out surface treatment, then when increasing the follow-up circuit operation of layer, form metal level at bearing bed, make chip directly connect metal level, reach the purpose that promotes heat dissipation this chip exposed surface and homonymy.
Via above-mentioned operation, the chip buried base plate structure of semi-conductor packaging of the present invention comprises a bearing structure, this bearing structure comprises first loading plate and is formed directly into second loading plate on this first loading plate, and this second loading plate has at least one perforate that runs through; At least one semiconductor chip is accommodated in this second loading plate perforate and connects and put on this first loading plate, and this semiconductor chip surface is formed with electrode pad; And a circuit layer reinforced structure, be formed on this second loading plate and this semiconductor chip, and be formed with a plurality of conductive blind holes in this circuit layer reinforced structure, be electrically connected to the electrode pad on this semiconductor chip.
The chip buried base plate structure of another kind of semi-conductor packaging provided by the invention comprises: a surface is formed with the semiconductor chip of electrode pad; One coats the loading plate around this semiconductor chip; And at least one circuit layer reinforced structure, be formed on a side of this loading plate of taking in semiconductor chip and this semiconductor chip, and the conductive blind hole that forms in this circuit layer reinforced structure is electrically connected to the electrode pad on this semiconductor chip, exposes outside the side that this chip is not provided with electrode pad.
The chip buried base plate structure of semi-conductor packaging of the present invention and method for making thereof provide at least one semiconductor chip to connect by a heat-conducting glue adhesion coating and put in a heat radiation bearing structure, the heat that effective this semiconductor chip of loss produces when operation, and this semiconductor chip is to be accommodated in to connect to put in the perforate of second loading plate of this bearing structure, can shorten the integral thickness of semiconductor device, reach compact purpose; In addition, the present invention directly is formed with at least one circuit layer reinforced structure on this takes in the bearing structure of semiconductor chip, make this circuit layer reinforced structure be electrically conducted electrode pad to this semiconductor chip by conductive blind hole, at last, can be provided with conducting elements such as a plurality of for example soldered balls, pin or the protruding pad of metal at the outer surface of this circuit layer reinforced structure, provide this semiconductor package structure to be electrically connected to external device (ED); Moreover, because bearing structure of the present invention is to adopt two kinds of combinations of different materials, can be two kinds of different metal levels, therefore can utilize etching or plating mode, in this second loading plate, form the smooth face of putting that connects, or in conjunction with a ceramic layer and a metal level, by ceramic layer precasting opening on metal level, or metal level is formed with the smooth face of putting that connects at etching openings on the ceramic layer in second loading plate at this bearing structure, for for example the electronic component of semiconductor chip can be steady, as one man connect and put on this bearing structure, promote chip embedding bury in the operation acceptance rate of bearing structure and evenly control bearing structure and chip connect and put the face planarization, and utilize dissimilar material properties to reduce the prying of semiconductor device, even can promote follow-up operation quality and electric connection reliability of carrying out the circuit layer reinforced structure.
In addition, also removable this first loading plate of the present invention gets directly this chip and exposes, and the whole height of reduction assembling structure effectively reaches compact purpose, can further provide direct external other heat abstractor to promote radiating effect simultaneously.
Therefore, the present invention can be by integrating heat radiation bearing structure, semiconductor chip and circuit layer reinforced structure, while is in conjunction with the operation of semiconductor packaging, can avoid the shortcoming of existing semiconductor packaging and the operation integration of interface problem of semiconductor device, simultaneously, can improve quality and acceptance rate, save cost, improve output, obtain the structure dress quality and the product reliability of good semiconductor buried base plate.
Description of drawings
Fig. 1 is a United States Patent (USP) the 6th, 709, the generalized section of the semiconductor device of No. 898 case propositions;
Fig. 2 is United States Patent (USP) the 6th, 709, the cross section view of the heating panel of No. 898 case propositions;
Fig. 3 is heating panel shown in Figure 2 produces disappearance when ccontaining chip a partial cutaway schematic;
Fig. 4 A to Fig. 4 J is the generalized section of method for making embodiment 1 of the chip buried base plate structure of semi-conductor packaging of the present invention;
Fig. 5 A to Fig. 5 J is the generalized section of method for making embodiment 2 of the chip buried base plate structure of semi-conductor packaging of the present invention;
Fig. 5 I ' is the generalized section of putting metal level at a side joint that exposes chip in the chip buried base plate structure of semi-conductor packaging of the present invention; And
Fig. 5 J ' figure correspondingly in the chip buried base plate structure of semi-conductor packaging of the present invention connects the generalized section that the line layer surface that is equipped with metal level is provided with conducting element.
Embodiment
Embodiment 1
Fig. 4 A to Fig. 4 J describes the generalized section of method for making embodiment 1 of the chip buried base plate structure of semi-conductor packaging of the present invention in detail.These accompanying drawings are the schematic diagram of simplification, basic framework of the present invention only is described in a schematic way, therefore only show the formation relevant with the present invention, and shown formation is not, and number, shape and dimension scale when implementing with reality drawn, number, shape and dimension scale during actual enforcement is a kind of optionally design, and the formation arrangement form may be more complicated.
See also Fig. 4 A, one first loading plate 400 and second loading plate 401 at first are provided, this first loading plate 400 has a upper surface 400a and reaches and this upper surface 400a opposing lower surface 400b, and this second loading plate 401 can be formed on this upper surface 400a by methods such as heating, pressurization, plating.Wherein, the material of this first, second loading plate 400,401 is different, it can be following combination: Cu/Ni, Cu/Al, Al/Ni, Ni/Al, in addition selectivity combination such as stainless steel/Cu, Cu/ stainless steel, Al/ stainless steel, if this first, second loading plate is the mutual corresponding combination of metal and pottery, then metal can be any material in Cu, Al, Ni and the stainless steel, pottery is in addition selectivity combination such as aluminium oxide or aluminium nitride, and the thickness of this first, second loading plate 400,401 can depend on the needs.
See also Fig. 4 B, then on this second loading plate 401, form a patterning resistance layer 41, this resistance layer 41 can for example be photoresist layers (Photoresist) such as dry film or liquid photoresistance, it is to utilize modes such as printing, spin coating or applying to be formed on this second loading plate, 401 surfaces, relend by modes such as exposure, development patterning in addition, make this resistance layer 41 only cover part second loading plate 401.
See also Fig. 4 C, carry out etching work procedure, with first loading plate 400 as etch stop layer, by selecting suitable etching solution, only this second loading plate 401 is carried out selective etch, remove second loading plate 401 that is not covered by this resistance layer 41, and then formation runs through the perforate 401a on these second loading plate, 401 surfaces, form the surface and be preset with many bearing structures 40 of putting the electronic component opening for the back continued access, wherein because this bearing structure 40 is to adopt two kinds of different metal levels, therefore can be at first and second loading plate 400 of this bearing structure 40, form the smooth face of putting that connects in 401 interfaces, electronic component for follow-up for example semiconductor chip can be steady, as one man connect and put on this bearing structure 40, promote chip embedding bury the acceptance rate of bearing structure operation and evenly the control bearing structure connect the planarization of the face of putting with chip, even can promote follow-up operation quality and electric connection reliability of carrying out the circuit layer reinforced structure.In addition, if should attention person be 40 production methods of the bearing structure with two layers of loading plate of metal material, put the face opening except utilizing above-mentioned selective etch mode to form smooth connecing, also can be by on first loading plate 400, forming patterning resistance layer (figure is mark not) earlier, form second loading plate 401 on first loading plate 400 of electronic component by plating mode follow-up again, form the smooth face of putting that connects in first and second loading plate 400,401 junctions for being provided with.
See also Fig. 4 D, also can utilize photoresistance to divest technology modes such as (Stirpping process) and remove this resistance layer 41.Wherein, are prior aries owing to remove the operation of this resistance layer 41, do not repeat them here.Moreover if first and second loading plate is metal and ceramic selectivity combination, the mode of then available precasting, sintering forms perforate at ceramic segment, so as to forming the double-deck carrying plate structure shown in Fig. 4 D.Wherein this second loading plate is to be formed directly on this first loading plate, does not combine by adhesion system.
See also Fig. 4 E, by a heat-conducting glue adhesion coating 42 the inverter circuit face 430 of semiconductor chip 43 is connect and put on this first loading plate 400 and be contained among the perforate 401a of this second loading plate 401.Wherein, the size of this perforate 401a is the size that cooperates this semiconductor chip 43.Has many strip electrodes weld pad 431a on the circuit face 431 of this chip 43.
See also Fig. 4 F, then on this second loading plate 401 and this semiconductor chip 43 circuit face 431, form a dielectric layer 402, and this dielectric layer 402 is filled among the perforate 401a of this second loading plate.Wherein, this dielectric layer is moral sense optical activity resin for example, epoxy resin, and for example preimpregnation material (prepeg), BT, the ABF of film like (film), PPE, PTFE etc., or photoinduction resin (Photo-imagable Resin) etc.
See also Fig. 4 G, also can utilize for example mode such as laser drill (laser drilling) or electric paste etching, also or corresponding photoinduction resin on this dielectric layer 402, form many blind hole 402a in the exposure imaging mode in the exposure imaging mode, expose outside the electrode pad 431a on these chip 43 circuit face 431.
See also Fig. 4 H, then, on this dielectric layer 402, form patterned line layer 403, and to forming conductive blind hole 402b by blind hole 402a, make this line layer 403 can be electrically connected to the electrode pad 431a of this chip 43 by this conductive blind hole 402b, wherein, the structure of this conductive blind hole can adopt the general blind hole conductive layer that fills up conductive layer (Cu via filled) entirely or do not fill up, and can promote electrical characteristic and heat dissipation for the structure kenel of filling up conductive layer entirely.
See also Fig. 4 I, also sustainablely increase floor operation on these bearing structure 40 enterprising line roads thereafter, on this takes in the bearing structure 40 of semiconductor chip 43, be formed with circuit layer reinforced structure 44, and make this circuit layer reinforced structure 44 can be electrically connected to the electrode pad 431a of this chip 43.
See also Fig. 4 J, then the outer fringe surface at this circuit layer reinforced structure 44 forms patterned anti-soldering layer 405, make this welding resisting layer 405 form many perforates, expose outside electric connection pad 404 parts of these circuit layer reinforced structure 44 outer fringe surfaces, on the electric connection pad 404 of these circuit layer reinforced structure 44 outer fringe surfaces, form conducting elements such as a plurality of for example soldered balls 406, pin or the protruding pad of metal, can be electrically conducted to external device (ED) for this semiconductor chip 43 that is embedded into into bearing structure 40.
Therefore, shown in Fig. 4 J, the chip buried base plate structure of the semi-conductor packaging that obtains by the above-mentioned operation of the present invention mainly comprises: a bearing structure 40, this bearing structure 40 comprises first loading plate 400 and is formed directly into second loading plate 401 on this first loading plate 400, and is formed with at least one perforate 401a that runs through in this second loading plate 401; At least one semiconductor chip 43 connects by a heat-conducting glue adhesion coating 42 and to put on this first loading plate 400 and be accommodated among the perforate 401a of this second loading plate 401; And at least one circuit layer reinforced structure 44, be formed on semiconductor chip 43 and this second loading plate 401, and this circuit layer reinforced structure 44 is by conductive blind hole 402b, be electrically connected to the electrode pad 431a of this semiconductor chip 43.
Wherein, this semiconductor chip 43 has an inverter circuit face 430 and a circuit face 431, and on the circuit face 431 of this semiconductor chip 43, be formed with electrode pad 431a, it is the inverter circuit face 430 with this semiconductor chip 43, connect by heat-conducting glue adhesion coating 42 and to put in the groove that this first loading plate 400 and this second loading plate 401 perforate 401a form, by this thermal conductivity glue adhesion coating 42 and the heat radiation approach (Thermally conductivepath) that this bearing structure 40 constitutes, the heat that produces when directly getting rid of these semiconductor chip 43 operations.
This circuit layer reinforced structure 44 is formed on semiconductor chip 43 and this second loading plate 401, and this circuit layer reinforced structure 44 comprises at least one dielectric layer 402, with the staggered stacked line layer 403 of this dielectric layer and run through these dielectric layers 402 electrically connecting the conductive blind hole 402b of this line layer, and these a plurality of conductive blind hole 402b can be electrically connected to the electrode pad 431a on this semiconductor chip 43 that is accommodated among this second loading plate perforate 401a.On the line layer of these circuit layer reinforced structure 44 outmost surface, then be formed with a plurality of electric connection pads 404, be equipped with a plurality of for example soldered balls (Solder ball) 406 conducting elements such as grade in order to provide to plant, provide this semiconductor chip 43 that is accommodated in this bearing structure to be electrically connected to external device (ED) by its surperficial electrode pad 431a, conductive blind hole 402b, line layer 403 and soldered ball 406.
Embodiment 2
Other sees also Fig. 5 A to Fig. 5 J, describes the method for making embodiment 2 of the chip buried base plate structure of semi-conductor packaging of the present invention in detail.Embodiments of the invention 2 are roughly the same with embodiment 1, its main difference is embodiment 2 removable first loading plates, this chip can directly be exposed, the whole height of reduction structure, reach compact purpose, in addition it also can be further directly external other heat abstractor to promote radiating effect.
See also Fig. 5 A, one first loading plate 500 and second loading plate 501 at first are provided, this first loading plate 500 has a upper surface 500a and reaches and this upper surface 500a opposing lower surface 500b, and this second loading plate 501 is formed directly on this upper surface 500a.Wherein, this first, second loading plate 500,501 can be adopt the metal level of unlike material or one be ceramic layer another be the selectivity combination of metal level, and the thickness of this first, second loading plate can depend on the needs.
See also Fig. 5 B, the material of this first, second loading plate 500,501 is different metals, or first and second loading plate 500,501 materials are respectively metal and pottery, then on this second loading plate 501, form patterning resistance layer 51, this resistance layer 51 can be a photoresist layer such as dry film or liquid photoresistance (Photoresist) for example, it is to utilize modes such as printing, spin coating or applying to be formed on this second loading plate, 501 surfaces, relend by modes such as exposure, development patterning in addition, make this resistance layer 51 only cover part second loading plate 501.
See also Fig. 5 C, if this is first years old, second loading plate 500,501 material is different metal, or first loading plate 500 are ceramic wafers, second loading plate 501 is metallic plates, then, carry out etching work procedure, with first loading plate 500 as etch stop layer, by selecting suitable etching solution that this second loading plate 501 is carried out selective etch, remove second loading plate 501 that is not covered by this resistance layer 51, and then formation runs through the perforate 501a on these second loading plate, 501 surfaces, form the surface and be preset with a plurality of bearing structures 50 of putting the electronic component opening for the back continued access, wherein because this bearing structure 50 is to adopt two kinds of different materials, therefore can be at first and second loading plate 500 of this bearing structure 50, be formed with the smooth face of putting that connects in the 501 crossing interfaces, electronic component for follow-up for example semiconductor chip can be steady, as one man connect and put on this bearing structure, promote chip embedding bury the operation acceptance rate of bearing part and evenly the control bearing part connect the planarization of the face of putting with chip, even can promote follow-up operation quality and electric connection reliability of carrying out the circuit layer reinforced structure.In addition, should attention person be the production method of this metal material bearing structure 50, put the face opening except utilizing above-mentioned selective etch mode to form smooth connecing, also can be by on first loading plate 500, forming patterning resistance layer (figure is mark not) earlier, on not for first loading plate 500 that electronic component is set, form second loading plate 501 by plating mode again, form the smooth face of putting that connects in first and second loading plate 500,501 junctions.
See also Fig. 5 D, also can utilize photoresistance to divest technology modes such as (Stirpping process) and remove this resistance layer 51.Wherein, belong to prior art, do not repeat them here owing to remove the operation of this resistance layer 51.Moreover if first and second loading plate is metal and ceramic selectivity combination, then available precasting sintering processing forms perforate at ceramic segment, so as to forming the double-deck carrying plate structure shown in Fig. 5 D.Wherein this second loading plate is to be formed directly on this first loading plate, does not take adhesion system to combine.
See also Fig. 5 E, by an adhesion coating 52 at least the inverter circuit face 530 of semiconductor chip 53 connect and put on this first loading plate 500 and be contained among the perforate 501a of this second loading plate 501.Wherein, the size of this perforate 501a is the size that cooperates this semiconductor chip 53.
See also Fig. 5 F, then on this second loading plate 501 and this semiconductor chip 53 circuit face 531, form a dielectric layer 502, and this dielectric layer 502 is filled among the perforate 501a of this second loading plate, have a plurality of electrode pad 531a on the circuit face 531 of this chip 53, wherein, this dielectric layer 502 is moral sense optical activity resin for example, epoxy resin, for example preimpregnation material (prepeg), BT, the ABF of film like (film), PPE, PTFE etc., or photoinduction resin (Photo-imagable Resin) etc.And can utilize for example mode such as laser drill (laserdrilling) or electric paste etching, also or corresponding photoinduction resin on this dielectric layer 502, form a plurality of blind hole 502a in the exposure imaging mode, expose outside the electrode pad 531a on these chip 53 circuit face 531.
See also Fig. 5 G, then, on this dielectric layer 502, form patterned line layer 503, and in this blind hole 502a, form conductive blind hole 502b, make this line layer 503 be electrically connected to electrode pad 531a on these chip 53 circuit face 531 by this conductive blind hole 502b.
See also Fig. 5 H, thereafter, also sustainable these bearing structure 50 enterprising line roads increase floor operation, and make this circuit layer reinforced structure 54 can be electrically connected to the electrode pad 531a of this chip 53.
See also Fig. 5 I, also removable this first loading plate 500 makes a side of this semiconductor chip 53 can directly be emerging in the external world, can reduce the whole height of assembling structure, reaches compact purpose.Even removing this first loading plate 500, when one side of this semiconductor chip 53 is exposed, expose side and the homonymy loading plate carries out surface treatment at this chip, increase in layer operation simultaneously at this surface treated side formation metal level 55 at the formation circuit, make a side of chip can directly connect metal level 55, so as to promoting radiating effect (shown in Fig. 5 I ' figure).
See also Fig. 5 J, then can form patterned anti-soldering layer 505 at the outer fringe surface of this circuit layer reinforced structure 54, make this welding resisting layer 505 be formed with a plurality of perforates, expose outside electric connection pad 504 parts of these circuit layer reinforced structure 54 outer fringe surfaces, on the electric connection pad 504 of these circuit layer reinforced structure 54 outer fringe surfaces, be formed with the conducting element of a plurality of for example soldered ball 506 grades, can be electrically conducted to external device (ED) for this chip 53.In addition, shown in the corresponding diagram 5I ', on the circuit layer reinforced structure 54 that provides chip 53 to link to each other with direct connection metal level 55, also can be formed with the conducting element of a plurality of for example soldered ball 506 grades, can be electrically conducted external device (ED) (shown in Fig. 5 J ') for this chip 53.
Therefore, shown in Fig. 5 J and Fig. 5 J ', the chip buried base plate structure of the semi-conductor packaging that obtains by the above embodiment of the present invention 2 operations mainly comprises: a surface is formed with the semiconductor chip 53 of electrode pad 531a; One coats the loading plate 501 around this semiconductor chip 53; An and circuit layer reinforced structure 54, be formed on this loading plate of taking in semiconductor chip 53 501 and this chip 53, and this circuit layer reinforced structure 54 is formed with conductive blind hole 502b, be electrically connected to the electrode pad 531a of this semiconductor chip 53, and expose outside the side that this chip is not provided with electrode pad.In addition, this semiconductor chip 53 side of not being electrically connected with the circuit layer reinforced structure can connect and be equipped with a metal level 55.
Wherein, this circuit layer reinforced structure 54 is formed on this semiconductor chip 53 and the loading plate 501, and this circuit layer reinforced structure 54 comprises at least one dielectric layer 502, with the staggered stacked line layer 503 of this dielectric layer and run through these dielectric layers 502 electrically connecting the conductive blind hole 502b of this line layer 503, and these a plurality of conductive blind hole 502b can be electrically connected to the electrode pad 531a on this semiconductor chip 53.On the conducting wire layer of these circuit layer reinforced structure 54 outmost surface, then be formed with a plurality of electric connection pads 504, provide and plant the conducting element that is equipped with a plurality of for example soldered ball 506 grades, provide conductive blind hole 502a that this semiconductor chip 53 can be by its surperficial electrode pad 531a, this circuit layer reinforced structure 54 and line layer 503 and soldered ball 506 to be electrically connected to external device (ED).
The chip buried base plate structure of semi-conductor packaging of the present invention and method for making thereof mainly provide at least one semiconductor chip by a heat conduction adhesion coating connect put one the heat radiation bearing structure in, the heat that effective this semiconductor chip of loss produces when operation, and this semiconductor chip is to be accommodated in to connect to put in the perforate of second loading plate of this bearing structure, can shorten the integral thickness of semiconductor device, reach compact purpose; In addition, the present invention directly is formed with at least one circuit layer reinforced structure on this takes in the bearing structure of semiconductor chip, and make this circuit layer reinforced structure can be by conductive blind hole, be electrically conducted the electrode pad to this semiconductor chip, at last, can be provided with the conducting element of a plurality of for example soldered balls at the outer surface of this circuit layer reinforced structure, this semiconductor package structure can directly be electrically connected to external device (ED); Moreover, because bearing structure of the present invention is to adopt two kinds of different metal levels, or the combination of pottery and metal, therefore can utilize modes such as etching, plating or precasting sintering, in second loading plate of this bearing structure, form the smooth face of putting that connects, can steadily, as one man connect for the electronic component of semiconductor chip for example and to put on this bearing structure, the lifting chip embedding bury is in the operation acceptance rate of bearing structure and evenly control the planarization that bearing structure and chip connect the face of putting, very to promoting follow-up operation quality and electric connection reliability of carrying out the circuit layer reinforced structure.
In addition, in the embodiments of the invention, also removable this first loading plate can directly expose this chip, and the whole height of reduction structure effectively reaches compact purpose, can further provide direct external other heat abstractor to promote radiating effect simultaneously.
Therefore, the chip buried base plate structure of semi-conductor packaging of the present invention can be by integrating heat radiation bearing structure, semiconductor chip and circuit layer reinforced structure, while is in conjunction with the operation of semiconductor packaging, avoid the shortcoming of existing semiconductor packaging and the operation integration of interface problem of semiconductor device, simultaneously, can improve acceptance rate, save cost, improve output, obtain good semiconductor chip and imbed quality and the product reliability of adorning as the circuit board structure of substrate.
Claims (18)
1. the method for making of the chip buried base plate structure of a semi-conductor packaging is characterized in that, this method for making comprises:
One bearing structure is provided, and this bearing structure has first loading plate and is formed directly into second loading plate on this first loading plate, and this second loading plate has at least one perforate that runs through;
At least semiconductor chip connect put on this first loading plate and be accommodated in the perforate of this second loading plate, the surface of this semiconductor chip is formed with a plurality of electrode pad;
Carry out circuit and increase a layer operation, form a dielectric layer at this chip and second loading plate surface, and dielectric layer material is filled in the gap of this second loading plate perforate and chip;
In this dielectric layer, be formed with blind hole, expose the electrode pad of this chip; And
Forming patterned line layer on this dielectric layer and in this blind hole, forming conductive blind hole, make this line layer can be electrically connected to the electrode pad of this chip.
2. the method for making of the chip buried base plate structure of semi-conductor packaging as claimed in claim 1 is characterized in that, the material of this first, second loading plate is a kind of in different metallic combination or metal and the ceramic combination.
3. the method for making of the chip buried base plate structure of semi-conductor packaging as claimed in claim 1 or 2 is characterized in that, the operation of this bearing structure comprises:
On this first loading plate, connect and put second loading plate;
On this second loading plate, form a patterning resistance layer; And
Second loading plate that exposes outside this patterning resistance layer is carried out selective etch, remove second loading plate of part, expose outside this first loading plate.
4. the method for making of the chip buried base plate structure of semi-conductor packaging as claimed in claim 1 or 2 is characterized in that, the operation of this bearing structure comprises:
On this first loading plate, form the patterning resistance layer; And
This first loading plate is electroplated, on this first loading plate, formed second loading plate with perforate.
5. the method for making of the chip buried base plate structure of semi-conductor packaging as claimed in claim 1 is characterized in that, this method for making also comprises and increases a layer operation, forms the circuit layer reinforced structure on this semiconductor chip and this second loading plate.
6. the method for making of the chip buried base plate structure of semi-conductor packaging as claimed in claim 5 is characterized in that, this method for making also is included in this outer most edge circuit surface conducting element is set.
7. the method for making of the chip buried base plate structure of semi-conductor packaging as claimed in claim 1 is characterized in that, this method for making also comprises and removes this second loading plate, and a side of this semiconductor chip is exposed.
8. the method for making of the chip buried base plate structure of semi-conductor packaging as claimed in claim 7, it is characterized in that, this method for making is included in also that this chip exposes side and the homonymy loading plate carries out surface treatment, increases in layer operation and forms metal level in this surface treated side simultaneously forming circuit.
9. the method for making of the chip buried base plate structure of semi-conductor packaging as claimed in claim 1 is characterized in that, this semiconductor chip is by a heat conduction adhesion coating, connects to put in the groove of this first loading plate and this second loading plate perforate formation.
10. the chip buried base plate structure of a semi-conductor packaging is characterized in that, this board structure comprises:
One bearing structure, this bearing structure comprise first loading plate and are formed directly into second loading plate on this first loading plate, and this second loading plate has at least one perforate that runs through;
At least one semiconductor chip is accommodated in this second loading plate perforate and connects and put on this first loading plate, and this semiconductor chip surface is formed with electrode pad; And
One circuit layer reinforced structure is formed on this second loading plate and this semiconductor chip, and is formed with a plurality of conductive blind holes in this circuit layer reinforced structure, is electrically connected to the electrode pad on this semiconductor chip.
11. the chip buried base plate structure of semi-conductor packaging as claimed in claim 10 is characterized in that, plants on the outer surface of this circuit layer reinforced structure to be equipped with a plurality of conducting elements.
12. the chip buried base plate structure of semi-conductor packaging as claimed in claim 10 is characterized in that, this circuit layer reinforced structure comprises dielectric layer, be stacked in the line layer of this dielectric layer and be formed on conductive blind hole in this dielectric layer.
13. the chip buried base plate structure of semi-conductor packaging as claimed in claim 10 is characterized in that, the material of this bearing structure, first loading plate and second loading plate is different metallic combination or a kind of combination in metal and the ceramic combination.
14. the chip buried base plate structure of a semi-conductor packaging is characterized in that, this board structure comprises:
One surface is formed with the semiconductor chip of electrode pad;
One coats the loading plate around this semiconductor chip; And
At least one circuit layer reinforced structure, be formed on a side of this loading plate of taking in semiconductor chip and this semiconductor chip, and the conductive blind hole that forms in this circuit layer reinforced structure is electrically connected to the electrode pad on this semiconductor chip, exposes outside the side that this chip is not provided with electrode pad.
15. the chip buried base plate structure of semi-conductor packaging as claimed in claim 14 is characterized in that, this board structure comprises that also one connects to put at this semiconductor chip and is not electrically connected with metal level on the side of circuit.
16. the chip buried base plate structure of semi-conductor packaging as claimed in claim 14 is characterized in that, this circuit layer reinforced structure comprises dielectric layer, be stacked in the line layer of this dielectric layer and be formed on conductive blind hole in this dielectric layer.
17. the chip buried base plate structure as claim 14 or 15 described semi-conductor packagings is characterized in that, plants on the outer surface of this circuit layer reinforced structure to be equipped with a plurality of conducting elements.
18. the chip buried base plate structure of semi-conductor packaging as claimed in claim 15 is characterized in that, the material of this loading plate is a kind of in metal and the pottery.
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| CNB2004101016380A CN100388447C (en) | 2004-12-20 | 2004-12-20 | Semiconductor structured chip embedded structure of base plate and method of preparation |
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| CNB2004101016380A CN100388447C (en) | 2004-12-20 | 2004-12-20 | Semiconductor structured chip embedded structure of base plate and method of preparation |
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