CN101360393B - Circuit board construction embedded with semi-conductor chip and preparation thereof - Google Patents
Circuit board construction embedded with semi-conductor chip and preparation thereof Download PDFInfo
- Publication number
- CN101360393B CN101360393B CN2007101398162A CN200710139816A CN101360393B CN 101360393 B CN101360393 B CN 101360393B CN 2007101398162 A CN2007101398162 A CN 2007101398162A CN 200710139816 A CN200710139816 A CN 200710139816A CN 101360393 B CN101360393 B CN 101360393B
- Authority
- CN
- China
- Prior art keywords
- layer
- circuit
- dielectric layer
- embedded
- semi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Abstract
The invention discloses a circuit board structure of an embedded semiconductor chip and the preparing method. The structure thereof includes: a bearing plate, which is provided with at least one through hole; a semiconductor chip, which is arranged in the through hole of the bearing plate, and the semiconductor chip is provided with an active plane and a passive plane, and the active plane is provided with a plurality of electrode mats; a dielectric layer, which is shaped on surface of the bearing plate and the semiconductor chip, and the dielectric layer is provided with a plurality of openings to expose the electrode mat of the semiconductor chip; and a compound circuitry layer, which is formed on the dielectric layer, and the compound circuitry layer is composed of a thinned metal layer, a conductive layer and a plated metal layer in turn, a conductive structure shaped in the opening of the dielectric layer is used to electrically connect the compound circuitry layer to the electrode mat of the semiconductor chip; thereby reducing warping generated by the process pyrometric effect through the characteristics of solidity and fine adhesion of the compound circuitry layer which is shaped on the dielectric layer.
Description
Technical field
The present invention relates to a kind of board structure of circuit and method for making thereof of embedded with semi-conductor chip, particularly relate to a kind of structure and method for making thereof about being embedded with semiconductor chip in the circuit board.
Background technology
Since IBM Corporation introduces chip package (Flip Chip Package) technology in early days in nineteen sixty, than routing (Wire Bond) technology, Flip Chip is characterised in that the electric connection between semiconductor chip and substrate is by the tin ball but not general gold thread.And the advantage of this kind Flip Chip is that this technology can improve packaging density with reduction potted element size, and need not use the long metal wire of length, so can improve electrical functionality.
Moreover, in recent years because high density, at a high speed and the increase of semiconductor chip demand cheaply, while is in response to the requirement of diminishing trend of the volume of electronic product and high integration, industry develops then semiconductor chip is placed in earlier in the opening of circuit board, on the surface of circuit board and semiconductor chip, form the technology of circuit layer reinforced structure again, use the packaging density that increases semiconductor chip; And the making of this circuit layer reinforced structure, shown in Figure 1A to Fig. 1 C.
See also Figure 1A, provide a loading plate 11 with opening 110, ccontaining semiconductor chip 12 in this opening 110, and this semiconductor chip 12 have an active surface 12a and with the corresponding non-active surface 12b of this active surface, this active surface 12a has a plurality of electronic padses 121.
See also Figure 1B, form a dielectric layer 13, and form the electronic pads 121 of a plurality of perforates 130 to expose this semiconductor chip 12 in this dielectric layer 13 in the active surface 12a of this loading plate 11 and semiconductor chip 12.
See also Fig. 1 C, form line layers 14 in this dielectric layer 13 surfaces, and form conductive structure 141 in this dielectric layer perforate 130, this conductive structure 141 also electrically connects the electronic pads 121 of this semiconductor chip 12; Wherein this line layer 14 is to make with semi-additive process, and this no longer gives unnecessary details for literary composition for mature technique; Follow-uply also can repeat above-mentioned processing procedure forming multilayer line, and this semiconductor chip 12 can be encapsulated in the loading plate 11, and reach electric connection.
But, in the aforementioned processing procedure, and the thermal coefficient of expansion of this loading plate 11, dielectric layer 13 and line layer 14 (Coefficient of thermal expansion, CTE) difference is big, easily cause warpage (Warpage) phenomenon under the variations in temperature in processing procedure, thereby reduce the quality of product.
Therefore, how to provide a kind of circuit of existing embedded with semi-conductor chip of avoiding to increase in layer processing procedure, because of the not good problem of the big reliability that causes of material expansion coefficient difference, real to become the problem that present industry is demanded urgently overcoming.
Summary of the invention
Defective in view of above-mentioned prior art, main purpose of the present invention provides a kind of board structure of circuit and method for making thereof of embedded with semi-conductor chip, the characteristic that can have firm and preferable adhesion by the gum element that is formed with a metal level on the dielectric layer, and be improved the combined type circuit layer formed by thinning metal level, conductive layer and electroplated metal layer and the adhesion of dielectric layer, and effectively reduce the warping phenomenon of circuit board.
For reaching above-mentioned main purpose, the method for making of the board structure of circuit of a kind of embedded with semi-conductor chip of the present invention comprises: a loading plate is provided, and this loading plate is formed with at least one opening that runs through; Ccontaining at least one semiconductor chip in the opening of this loading plate, this semiconductor chip have active surface and reach and the corresponding non-active surface of this active surface, have a plurality of electronic padses in this active surface; In the active surface pressing one gum element of this loading plate and semiconductor chip, this gum element is to be formed with a metal level on a dielectric layer; Layer on surface of metal in this gum element carries out the thinning processing procedure and becomes a thinning metal level; This gum element is formed with a plurality of perforates to expose the electronic pads of this semiconductor chip; In the thinning layer on surface of metal of this gum element and perforate, be formed with a conductive layer; Form a resistance layer in this conductive layer surface, and the patterned processing procedure of this resistance layer forms the conductive layer of a plurality of perforates with exposed portions serve; Conductive layer surface in the perforate of this resistance layer forms electroplated metal layer; And remove this resistance layer and conductive layer that is covered and thinning metal level, the dielectric layer that exposes this gum element, thereby forming a combined type circuit layer of being formed by thinning metal level, conductive layer and electroplated metal layer, and in this gum element dielectric layer perforate, form conductive structure.
This gum element is in dielectric layer surface pressure unification metal level, or this gum element be in a dielectric layer surface with an adhesion layer in conjunction with a metal level.
The metal level of this gum element can be Copper Foil, and the dielectric layer of this gum element can be the preimpregnation material; The layer on surface of metal of this gum element is to carry out the thinning processing procedure to form this thinning metal level with physics or chemical mode.
The dielectric layer and the combined type circuit laminar surface that also are included in this gum element according to above-mentioned method for making form a circuit layer reinforced structure, this circuit layer reinforced structure is constituted by the dielectric layer and the combined type circuit layer of a plurality of gum elements, and this circuit layer reinforced structure has conductive structure to electrically connect this semiconductor chip, this circuit layer reinforced structure outer surface forms a plurality of electric connection pads again, this circuit layer reinforced structure comprises at least one dielectric layer, be stacked and placed on the combined type circuit layer on this dielectric layer, and be formed at conductive structure in this dielectric layer, and on this circuit layer reinforced structure, form a welding resisting layer, and form a plurality of perforates in this welding resisting layer to expose this electric connection pad.
In addition according to above-mentioned method for making, the dielectric layer and the combined type circuit laminar surface that also are included in this gum element form a circuit layer reinforced structure, and this circuit layer reinforced structure is constituted with a plurality of dielectric layers and line layer, and this line layer is constituted by conductive layer and electroplated metal layer, this circuit layer reinforced structure comprises at least one dielectric layer, be stacked and placed on the line layer on this dielectric layer, and be formed at conductive structure in this dielectric layer, and this conductive structure electrically connects this line layer, this circuit layer reinforced structure outer surface forms a plurality of electric connection pads again, and on this circuit layer reinforced structure, be formed with a welding resisting layer, and form a plurality of perforates in this welding resisting layer to expose described electric connection pad.
According to the method for making of the above, the present invention also provides a kind of board structure of circuit of embedded with semi-conductor chip, comprising: loading plate has at least one opening that runs through; Semiconductor chip is placed in the opening of this loading plate, and this semiconductor chip has active surface and non-active surface, has a plurality of electronic padses in this active surface; Dielectric layer is formed at this loading plate and semiconductor chip surface, and this dielectric layer has a plurality of perforates to expose the electronic pads of this semiconductor chip; And combined type circuit layer, be formed on this dielectric layer, this combined type circuit layer includes thinning metal level, conductive layer and electroplated metal layer in regular turn, and is formed with conductive structure is electrically connected to this semiconductor chip for this combined type circuit layer electronic pads in this dielectric layer perforate.
According to above-mentioned structure, also be included in this dielectric layer and the combined type circuit laminar surface is formed with the circuit layer reinforced structure, and this circuit layer reinforced structure constituted by the dielectric layer and the line layer of a plurality of gum elements, or this circuit layer reinforced structure is constituted by a plurality of dielectric layers and line layer; This circuit layer reinforced structure has conductive structure to be electrically connected to this combined type circuit layer, this circuit layer reinforced structure outer surface forms a plurality of electric connection pads again, this circuit layer reinforced structure comprises at least one dielectric layer, is stacked and placed on the combined type circuit layer on this dielectric layer, and be formed at conductive structure in this dielectric layer, and on this circuit layer reinforced structure, be formed with a welding resisting layer, and form a plurality of perforates in this welding resisting layer to expose described electric connection pad.
In addition according to aforesaid structure, also be included in this dielectric layer and combined type circuit laminar surface and form a circuit layer reinforced structure, and this circuit layer reinforced structure is constituted with a plurality of dielectric layers and line layer, and this line layer is constituted by conductive layer and electroplated metal layer, this circuit layer reinforced structure comprises at least one dielectric layer, be stacked and placed on the line layer on this dielectric layer, and be formed at conductive structure in this dielectric layer, and this conductive structure electrically connects this combined type circuit layer, this circuit layer reinforced structure outer surface forms a plurality of electric connection pads again, and on this circuit layer reinforced structure, be formed with a welding resisting layer, and form a plurality of perforates in this welding resisting layer to expose described electric connection pad.
Gum element of the present invention is to be formed with a metal level on dielectric layer, this metal level the best can be Copper Foil, and utilize that its material of a dielectric layer is the preimpregnation material in the matsurface pressing of Copper Foil, or the matsurface of Copper Foil is combined with the preimpregnation material and can produce preferable adhesion by adhesion layer, wherein, utilize the preimpregnation material that contains glass can effectively reduce warpage and size variation as dielectric layer.The present invention must be because of the combination of aforementioned metal layer and dielectric layer, and improves the combined type circuit layer be made up of thinning metal level, conductive layer and electroplated metal layer and the adhesion of dielectric layer, and effectively reduces the warping phenomenon of circuit board.
Description of drawings
Figure 1A to Fig. 1 C is that the semiconductor chip of prior art is embedded in the method for making generalized section in the circuit board;
Fig. 2 A to Fig. 2 G is the board structure of circuit of embedded with semi-conductor chip of the present invention and the method for making generalized section of method for making thereof;
Fig. 2 A ' is that another of Fig. 2 A of the board structure of circuit of embedded with semi-conductor chip of the present invention and method for making thereof implemented generalized section;
Fig. 2 B ' is that another of Fig. 2 B of the board structure of circuit of embedded with semi-conductor chip of the present invention and method for making thereof implemented generalized section;
Fig. 3 A and Fig. 3 B are the generalized section that board structure of circuit of the present invention carries out the circuit layer reinforced structure; And
Fig. 4 carries out the generalized section of another embodiment of circuit layer reinforced structure for board structure of circuit of the present invention.
The component symbol explanation
11,21 loading plates
110,210 openings
12,22 semiconductor chips
121,221 electronic padses
12a, 22a active surface
The non-active surface of 12b, 22b
13,231,271,271 ' dielectric layer
130,230,250,280 perforates
14,272 line layers
141,261,273,273 ' conductive structure
20 combined type circuit layers
The 21a release film
The 21b adhesion material
23,23 ' gum element
232 ' thinning metal level
232 metal levels
233 adhesion layers
24 conductive layers
25 resistance layers
26 electroplated metal layers
27,27 ' circuit layer reinforced structure
274,274 ' electric connection pad
28 welding resisting layers
Embodiment
Below by particular specific embodiment explanation embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.
See also Fig. 2 A to Fig. 2 G, be the board structure of circuit of embedded with semi-conductor chip of the present invention and the embodiment generalized section of method for making.
Shown in Fig. 2 A, thing forms in a loading plate 21 and at least always wears opening 210, and in this opening 210, be equipped with at least one semiconductor chip 22, this semiconductor chip 22 has active surface 22a and reaches and the corresponding non-active surface 22b of this active surface, has a plurality of electronic padses 221 in this active surface 22a; And a gum element 23, this gum element 23 are provided is to be formed with a metal level 232 on a dielectric layer 231, and this metal level 232 has matsurface and preferable associativity must be arranged to be combined into one with this dielectric layer 231; Wherein this metal level 232 can be Copper Foil, and this dielectric layer is the preimpregnation material; Other sees also Fig. 2 A ', or this gum element 23 also can be in a dielectric layer 231 surfaces with an adhesion layer 233 in conjunction with this metal level 232.Aforesaid metal level 232 the bests can be Copper Foil, and can utilize a preimpregnation material in the matsurface pressing of Copper Foil or the matsurface of Copper Foil is combined with the preimpregnation material and can produce preferable adhesion, and utilize the preimpregnation material that contains glass can reduce effectively as dielectric layer 231 that plate sticks up and the size variation by adhesion layer 233; For convenience of description, explain with the graphic of Fig. 2 B below.
Shown in Fig. 2 B, the dielectric layer 231 of this gum element 23 is pressed together on the active surface 22a of this loading plate 21 and semiconductor chip 22, and this dielectric layer 231 is pressed in the gap between this semiconductor chip 22 and the opening 210, thereby so that this semiconductor chip 22 is fixed in this opening 210.
Other sees also Fig. 2 B ', a release film 21a can fit earlier in the bottom surface of this loading plate 21, again this semiconductor chip 22 is placed this opening 210, insert in the gap between this semiconductor chip 22 and the opening 210 with adhesion material 21b then, thereby so that this semiconductor chip 22 is fixed in this opening 210; For convenience of description, explain with the graphic of Fig. 2 B below.
Shown in Fig. 2 C, then the thinning processing procedure is carried out with physics or chemical mode in metal level 232 surfaces of this gum element 23, and becomes a thinning metal level 232 '.
Shown in Fig. 2 D, form a plurality of perforates 230 in this gum element 23, with the electronic pads 221 that exposes this semiconductor chip 22.
Shown in Fig. 2 E, in the thinning metal level 232 ' surface of this gum element 23 and perforate 230, form a conductive layer 24, and make this conductive layer 24 electrically connect the electronic pads 221 of this semiconductor chip 22, and in this conductive layer 24 surface formation one resistance layer 25, and these resistance layer 25 patterned processing procedures (as exposure, development) are formed with the conductive layer 24 of perforate 250 with exposed portions serve.
Shown in Fig. 2 F, as current conduction path, form an electroplated metal layer 26 to go up, and in these dielectric layer 231 perforates 230, form conductive structure 261 in conductive layer 24 surfaces of this resistance layer perforate 250 by this conductive layer 24.
Shown in Fig. 2 G, then remove this resistance layer 25 and conductive layer 24 that is covered and thinning metal level 232 ', thereby forming the combined type circuit layer 20 that is constituted by this electroplated metal layer 26, conductive layer 24 and thinning metal level 232 ', and make this combined type circuit layer 20 must electrically connect the electronic pads 221 of these semiconductor chips 22 through this conductive structure 261.
Because this combined type circuit layer 20 is to go up in the thinning metal level 232 ' of gum element 23 to form conductive layer 24 and electroplated metal layer 26, and can be by this gum element 23 to reduce warpage (Warpage) phenomenon that thermal expansion coefficient difference was caused, to improve the quality of product.
See also Fig. 3 A and Fig. 3 B, go up pressing one another gum element 23 ' in the dielectric layer 231 and combined type circuit layer 20 surface of this gum element 23 in addition, as shown in Figure 3A; Then this gum element 23 ' will be to form another combined type circuit layer through aforementioned processing procedure, thereby dielectric layer 231 and combined type circuit layer 20 with a plurality of gum elements 23 constitute a circuit layer reinforced structure 27, shown in Fig. 3 B, this circuit layer reinforced structure 27 comprises at least one dielectric layer 271, be stacked and placed on the line layer 272 on this dielectric layer 271, and be formed at conductive structure 273 in this dielectric layer 271, and this conductive structure 273 is electrically connected to and is formed at this combined type circuit layer 20, this circuit layer reinforced structure outer surface forms a plurality of electric connection pads 274 again, and on this circuit layer reinforced structure 27, form a welding resisting layer 28, be formed with a plurality of perforates 280 in this welding resisting layer 28 to expose described electric connection pad 274.
See also Fig. 4, dielectric layer 231 and combined type circuit layer 20 surface in this gum element 23 form a circuit layer reinforced structure 27 ', it is to form a dielectric layer 271 ' earlier at the dielectric layer 231 of this gum element 23 and combined type circuit layer 20 surface, form a line layer 272 ' in this dielectric layer 271 ' surface again, reach and in this dielectric layer 271 ', form at least one conductive structure 273 ', and this line layer is made of conductive layer and electroplated metal layer, it is mature technique that this kind circuit increases layer technology, no longer gives unnecessary details for literary composition in this; This circuit layer reinforced structure 27 ' outer surface forms a plurality of electric connection pads 274 ' again, and goes up formation one welding resisting layer 28 in this circuit layer reinforced structure 27 ', and forms a plurality of perforates 280 to expose described electric connection pad 274 ' in this welding resisting layer 28.
Gum element of the present invention is to form a metal level on a dielectric layer, this metal level the best can be Copper Foil, and the matsurface with this Copper Foil is pressed together on this dielectric layer, and this dielectric layer material is the preimpregnation material, or combine with the preimpregnation material by the matsurface of adhesion layer with Copper Foil, and can produce preferable adhesion, wherein, utilize the preimpregnation material that contains glass also can effectively reduce the variation of warpage and size as dielectric layer.The present invention must be because of the combination of aforementioned metal layer and dielectric layer, and improves the combined type circuit layer be made up of thinning metal level, conductive layer and electroplated metal layer and the adhesion of dielectric layer, and effectively reduces the warping phenomenon of circuit board.
The foregoing description only is illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any those skilled in the art all can be under spirit of the present invention and category, and the foregoing description is modified and changed.Therefore, the scope of the present invention should be foundation with the scope of claims.
Claims (21)
1. the board structure of circuit of an embedded with semi-conductor chip comprises:
Loading plate has at least one opening that runs through;
Semiconductor chip is placed in the opening of this loading plate, and this semiconductor chip has active surface and non-active surface, has a plurality of electronic padses in this active surface;
Dielectric layer be to contain the preimpregnation material of glass and be formed at this loading plate and semiconductor chip surface, and this dielectric layer has a plurality of perforates to expose the electronic pads of this semiconductor chip;
The combined type circuit layer, be formed on this dielectric layer, this combined type circuit layer is made up of thinning metal level, conductive layer and electroplated metal layer in regular turn, and is formed with conductive structure is electrically connected to this semiconductor chip for this combined type circuit layer electronic pads in this dielectric layer perforate; And
One circuit layer reinforced structure is formed at this dielectric layer and combined type circuit laminar surface, wherein, have conductive structure in this circuit layer reinforced structure being electrically connected to this combined type circuit layer, and this circuit layer reinforced structure outer surface forms a plurality of electric connection pads.
2. the board structure of circuit of embedded with semi-conductor chip according to claim 1, wherein, this circuit layer reinforced structure is constituted by a plurality of dielectric layers and combined type circuit layer.
3. the board structure of circuit of embedded with semi-conductor chip according to claim 1 comprises that also a welding resisting layer is formed at this circuit layer reinforced structure surface, and forms a plurality of perforates in this welding resisting layer to expose this electric connection pad.
4. the board structure of circuit that is embedded into the semiconductive chip according to claim 2, wherein, this circuit layer reinforced structure comprises at least one dielectric layer, is stacked and placed on the combined type circuit layer on this dielectric layer, and is formed at the conductive structure in this dielectric layer.
5. the board structure of circuit of embedded with semi-conductor chip according to claim 1, wherein, this circuit layer reinforced structure is constituted by a plurality of dielectric layers and line layer, and this line layer is made of an electroplated metal layer and conductive layer.
6. the board structure of circuit of embedded with semi-conductor chip according to claim 5 have conductive structure in this circuit layer reinforced structure being electrically connected to this combined type circuit layer, and this circuit layer reinforced structure outer surface forms a plurality of electric connection pads.
7. the board structure of circuit of embedded with semi-conductor chip according to claim 6 comprises that also a welding resisting layer is formed on this circuit layer reinforced structure, and forms a plurality of perforates in this welding resisting layer to expose this electric connection pad.
8. the board structure of circuit that is embedded into the semiconductive chip according to claim 5, wherein, this circuit layer reinforced structure comprises at least one dielectric layer, is stacked and placed on the line layer on this dielectric layer, and is formed at the conductive structure in this dielectric layer.
9. the method for making of the board structure of circuit of an embedded with semi-conductor chip comprises:
One loading plate is provided, and this loading plate is formed with at least one opening that runs through;
Ccontaining at least one semiconductor chip in the opening of this loading plate, this semiconductor chip have active surface and reach and the corresponding non-active surface of this active surface, have a plurality of electronic padses in this active surface;
In the active surface pressing one gum element of this loading plate and semiconductor chip, this gum element is to be formed with a metal level on a dielectric layer;
Layer on surface of metal in this gum element carries out the thinning processing procedure and becomes a thinning metal level;
This gum element is formed with a plurality of perforates to expose the electronic pads of this semiconductor chip;
In the thinning layer on surface of metal of this gum element and perforate, be formed with a conductive layer;
Form a resistance layer in this conductive layer surface, and the patterned processing procedure of this resistance layer forms the conductive layer of a plurality of perforates with exposed portions serve;
Conductive layer surface in the perforate of this resistance layer forms electroplated metal layer; And
Remove this resistance layer and the conductive layer that is covered thereof and thinning metal level, the dielectric layer that exposes this gum element, thereby forming a combined type circuit layer of being formed by thinning metal level, conductive layer and electroplated metal layer, and in this gum element dielectric layer perforate, form conductive structure is electrically connected to this semiconductor chip for this combined type circuit layer electronic pads.
10. the method for making of the board structure of circuit of embedded with semi-conductor chip according to claim 9 also is included in this dielectric layer and combined type circuit laminar surface and forms a circuit layer reinforced structure.
11. the method for making of the board structure of circuit of embedded with semi-conductor chip according to claim 9, wherein, this circuit layer reinforced structure is constituted by the dielectric layer and the combined type circuit layer of a plurality of gum elements.
12. the method for making of the board structure of circuit of embedded with semi-conductor chip according to claim 11 wherein, have conductive structure in this circuit layer reinforced structure being electrically connected to this combined type circuit layer, and this circuit layer reinforced structure outer surface forms a plurality of electric connection pads.
13. the method for making of the board structure of circuit of embedded with semi-conductor chip according to claim 12 comprises that also a welding resisting layer is formed at this circuit layer reinforced structure surface, and forms a plurality of perforates in this welding resisting layer to expose this electric connection pad.
14. the method for making that is embedded into the board structure of circuit of semiconductive chip according to claim 11, wherein, this circuit layer reinforced structure comprises at least one dielectric layer, is stacked and placed on the combined type circuit layer on this dielectric layer, and is formed at the conductive structure in this dielectric layer.
15. the method for making of the board structure of circuit of embedded with semi-conductor chip according to claim 10, wherein, this circuit layer reinforced structure is constituted by a plurality of dielectric layers and line layer, and this line layer is made of a conductive layer and electroplated metal layer.
16. the method for making of the board structure of circuit of embedded with semi-conductor chip according to claim 15 have conductive structure in this circuit layer reinforced structure being electrically connected to this combined type circuit layer, and this circuit layer reinforced structure outer surface forms a plurality of electric connection pads.
17. the method for making of the board structure of circuit of embedded with semi-conductor chip according to claim 16 comprises that also a welding resisting layer is formed on this circuit layer reinforced structure, and forms a plurality of perforates in this welding resisting layer to expose this electric connection pad.
18. the method for making that is embedded into the board structure of circuit of semiconductive chip according to claim 15, wherein, this circuit layer reinforced structure comprises at least one dielectric layer, is stacked and placed on the line layer on this dielectric layer, and is formed at the conductive structure in this dielectric layer.
19. the method for making of the board structure of circuit of embedded with semi-conductor chip according to claim 9, this gum element are in a dielectric layer surface pressure metal layer.
20. the method for making of the board structure of circuit of embedded with semi-conductor chip according to claim 9, this gum element are with an adhesion layer bond layer in a dielectric layer surface.
21. the method for making of the board structure of circuit of embedded with semi-conductor chip according to claim 9, wherein, this dielectric layer is the preimpregnation material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101398162A CN101360393B (en) | 2007-08-01 | 2007-08-01 | Circuit board construction embedded with semi-conductor chip and preparation thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101398162A CN101360393B (en) | 2007-08-01 | 2007-08-01 | Circuit board construction embedded with semi-conductor chip and preparation thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101360393A CN101360393A (en) | 2009-02-04 |
| CN101360393B true CN101360393B (en) | 2010-12-08 |
Family
ID=40332704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101398162A Active CN101360393B (en) | 2007-08-01 | 2007-08-01 | Circuit board construction embedded with semi-conductor chip and preparation thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101360393B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130072B (en) * | 2010-01-15 | 2013-03-13 | 矽品精密工业股份有限公司 | Bearing plate and manufacturing method thereof |
| CN102013218B (en) * | 2010-12-29 | 2013-07-10 | 利亚德光电股份有限公司 | Led display board and led display |
| CN102024389B (en) * | 2010-12-29 | 2014-08-27 | 利亚德光电股份有限公司 | LED display panel and LED display |
| CN103632979B (en) * | 2012-08-27 | 2017-04-19 | 碁鼎科技秦皇岛有限公司 | Chip packaging substrate and structure, and manufacturing methods thereof |
| DE102017212233A1 (en) * | 2017-07-18 | 2019-01-24 | Siemens Aktiengesellschaft | Electrical assembly and method of making an electrical assembly |
| CN111261047A (en) * | 2020-02-27 | 2020-06-09 | 昆山国显光电有限公司 | Display panel and display device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1797726A (en) * | 2004-12-20 | 2006-07-05 | 全懋精密科技股份有限公司 | Semiconductor structured chip embedded structure of base plate and method of preparation |
-
2007
- 2007-08-01 CN CN2007101398162A patent/CN101360393B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1797726A (en) * | 2004-12-20 | 2006-07-05 | 全懋精密科技股份有限公司 | Semiconductor structured chip embedded structure of base plate and method of preparation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101360393A (en) | 2009-02-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7656015B2 (en) | Packaging substrate having heat-dissipating structure | |
| KR102107037B1 (en) | Printed circuit board and method of manufacturing the same | |
| JP5572684B2 (en) | Package carrier and manufacturing method thereof | |
| US7719104B2 (en) | Circuit board structure with embedded semiconductor chip and method for fabricating the same | |
| CN100561696C (en) | The structure of embedded with semi-conductor chip and method for making thereof | |
| JP5389770B2 (en) | Printed circuit board with built-in electronic element and manufacturing method thereof | |
| US9338886B2 (en) | Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device | |
| US20060267188A1 (en) | Memory module with improved mechanical strength of chips | |
| US8669653B2 (en) | Semiconductor device having electronic component in through part, electronic device, and manufacturing method of semiconductor | |
| US20100006331A1 (en) | Printed Circuit Board With Embedded Semiconductor Component and Method for Fabricating the Same | |
| JP2007123524A (en) | Substrate with built-in electronic part | |
| TWI493671B (en) | Package substrate having holder and fabricating method thereof, package structure having holder and fabricating method thereof | |
| JP2009194322A (en) | Semiconductor device manufacturing method, semiconductor device and wiring substrate | |
| TW201244034A (en) | Package structure having embedded electronic component and fabrication method thereof | |
| JP2008218979A (en) | Electronic packaging and manufacturing method thereof | |
| EP2763518A1 (en) | Component embedded substrate mounting body, method for manufacturing same and component embedded substrate | |
| CN101360393B (en) | Circuit board construction embedded with semi-conductor chip and preparation thereof | |
| TW201537719A (en) | Stacked semiconductor package | |
| US9041180B2 (en) | Semiconductor package and method of manufacturing the semiconductor package | |
| JP2017195261A (en) | Interposer and method of producing interposer | |
| CN102376678B (en) | Chip scale package and manufacturing method thereof | |
| JP2009135391A (en) | Electronic device and method of manufacturing the same | |
| CN102751203A (en) | Semiconductor encapsulation structure and manufacture method of semiconductor encapsulation structure | |
| TWI658557B (en) | Load circuit board and methord for manufacturing the same | |
| TW201408148A (en) | Substrate structure having embedded electronic component and method of fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |