WO2013037102A1

WO2013037102A1 - Encapsulation method for embedding chip into substrate and structure thereof

Info

Publication number: WO2013037102A1
Application number: PCT/CN2011/079575
Authority: WO
Inventors: 霍如肖; 谷新; 丁鲲鹏
Original assignee: 深南电路有限公司
Priority date: 2011-09-13
Filing date: 2011-09-13
Publication date: 2013-03-21
Also published as: CN103477423A; CN103477423B

Abstract

Provided are an encapsulation method for embedding a chip into a substrate and a structure thereof. The method includes: providing at least one chip embedding part inside a substrate, the chip embedding part being a through-hole and/or a recess, the number of chip embedding parts being equal to that of the chip (107) to be encapsulated, the depth of the chip embedding part matched with the thickness of the chip (107) to be encapsulated; embedding the chip (107) into the chip embedding part; wiring on a first contact face and/or a second contact face of the chip (107), and wiring correspondingly on the substrate to form a wiring layer, so that the substrate and the chip (107) are electrically connected to each other.

Description

Chip embedding method and structure thereof

The present invention relates to the field of chip packaging, and in particular to a method of packaging a chip embedded in a substrate and a structure thereof.

Background technique

With the development of the information society, the amount of information processing of various electronic devices continues to increase, and the demand for high-frequency, high-speed signal transmission is increasing. The semiconductor chip is embedded in the package substrate, because it can effectively shorten the connection distance between the semiconductor and the package substrate, and can provide strong guarantee for high-frequency and high-speed signal transmission, and the chip embedded in the substrate can satisfy the high integration degree of the package structure and the electronic product. The development needs of miniaturization.

There is a special type of chip in the semiconductor package, such as a metal oxide semiconductor field effect transistor.

Active devices such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), diodes, and transistors have single-sided or double-sided electrical connections, and different types of active devices have different thicknesses.

Buried semiconductor chips of different thicknesses are embedded in the substrate. When the thickness of the substrate is required to be different from the thickness of the chip due to the necessity of insulation, it is necessary to ensure that at least one side of the chip is coplanar with the substrate, and the chip is ensured. Single-sided or double-sided with good electrical connection to the substrate, the prior art is usually achieved by lamination, which requires a lot of pressure during lamination, and requires laser drilling, copper sinking and electroplating to achieve electrical connection. Bringing a lot of risk to the integrity of the chip.

Summary of the invention

The embodiment of the invention provides a method for packaging a chip embedded in a substrate and a structure thereof, which are used for solving the coplanarity of the chip and the substrate and the electrical connection between the chip contact surface and the lower layer when the chip is integrally packaged, thereby improving the reliability of the chip package. .

According to an embodiment of the invention, a method for packaging a chip embedded substrate, the chip having a first contact surface and a second contact surface, comprising the following steps:

Step S1: at least one chip embedding portion is disposed on the substrate, the chip embedding portion is a through hole and/or a groove, and the number of the chip embedding portion is the same as the number of required packaged chips, and the chip embedding portion is The depth matches the chip thickness of the desired package;

Step S2: embedding the chip into the chip embedding portion; Step S3: forming a wiring layer on the first contact surface and/or the second contact surface of the chip, and corresponding wiring on the substrate, so that the substrate and the chip are electrically connected.

According to still another embodiment of the present invention, a package structure of a chip embedded in a substrate, the package structure of the chip embedded in the substrate includes a substrate, a chip, and a wiring layer.

The substrate is provided with at least one chip embedding portion, the chip has a first contact surface and a second contact surface, the chip embedding portion is a through hole and/or a groove, and the depth of the chip embedding portion and the corresponding embedding Chip thickness matching,

The wiring layer includes a wiring disposed on the first contact surface and/or the second contact surface of the chip, and a wiring disposed on the substrate corresponding to the wiring of the chip for realizing electrical connection between the chip and the substrate .

As can be seen from the above technical solutions, the embodiments of the present invention have the following advantages:

(1) placing chips of different thicknesses through grooves having different depths, and the depth of the grooves is matched with the thickness of the chip to be buried, so as to ensure that the chips of different thickness are coplanar after being packaged into the substrate;

(2) According to different setting methods of setting the pad on one side of the chip or different pads on both sides of the chip, different connection methods are selected to electrically connect the chip, so that the packaging process has good expandability and strong applicability.

DRAWINGS

1 is a schematic flow chart of a method for packaging a chip embedded in a substrate according to Embodiment 1 of the present invention; and FIG. 2 is a schematic diagram showing a process step of a first embodiment of a method for packaging a chip embedded in a substrate according to Embodiment 1 of the present invention;

3a to 3g are schematic diagrams showing process steps of a second embodiment of a method for packaging a chip embedded in a substrate according to Embodiment 1 of the present invention;

4a to 4h are schematic diagrams showing three steps of an application example of a method for packaging a chip embedded in a substrate according to Embodiment 1 of the present invention;

5 is a schematic diagram showing four steps of an application example of a method for packaging a chip embedded in a substrate according to Embodiment 1 of the present invention;

6 is a schematic flow chart of a method for packaging a chip embedded substrate according to a second embodiment of the present invention; FIG. 7 is a schematic diagram showing a process step of a method for packaging a chip embedded substrate according to a second embodiment of the present invention;

8 is a schematic flow chart of a method for packaging a chip embedded in a substrate according to Embodiment 3 of the present invention; 9a to 9d are schematic diagrams showing process steps of an application example of a method of packaging a chip embedded in a substrate according to a third embodiment of the present invention;

10 is a schematic diagram of a package structure of a chip embedded in a substrate according to Embodiment 4 of the present invention;

11 is a schematic diagram of a package structure of a chip embedded in a substrate according to Embodiment 5 of the present invention;

FIG. 12 is a schematic diagram of a package structure of a chip embedded substrate according to Embodiment 6 of the present invention.

detailed description

Embodiments of the present invention provide a method for packaging a chip embedded in a substrate and a structure thereof, which are used to solve the problem of coplanarity and electrical connection between the chip and the substrate in the chip package, and realize high frequency and high speed transmission of the electrical signal. The implementation of the present invention will be described in detail below with reference to the specific embodiments, and some of the more common technical means are not described in detail to avoid the unnecessary limitation of the present invention.

Embodiment 1

Referring to FIG. 1, a schematic flow chart of a method for packaging a chip embedded in a substrate according to the present embodiment is shown, and a method for packaging a chip embedded in a substrate, wherein the chip has a first contact surface and a second contact surface, and the following steps are included:

S101, at least one chip embedding portion is disposed on the substrate, the chip embedding portion is a through hole and/or a groove, the number of the chip embedding portion is the same as the number of the required packaged chips, and the depth of the chip embedding portion matches the chip thickness of the required package. ;

5102, embedding the chip in the chip embedding portion;

5103, wiring on the first contact surface and/or the second contact surface of the chip, and corresponding wiring on the substrate, forming a wiring layer, so that the substrate and the chip are electrically connected.

For the chip embedding portion, there are through holes and/or grooves. In different application embodiments, at least one of the chip embedding portions may be a groove or a through hole, or may be a groove or a through hole. The substrate may be a single-sided board, a double-sided board or a multi-layer board in which an inner layer circuit has been processed. In the embodiment, a more intuitive representation process is performed, and a double-panel is taken as an example to describe the process.

A specific application example of the chip-embedded substrate encapsulation method will be described in more detail below, and it can be understood that the modes in the respective steps in the following embodiments can be used in combination.

Referring to Figures 2a to 2g, there are shown process steps for a single chip package, the process of which is as follows:

2a, a substrate having a first metal layer 101, a dielectric layer 100, and a second metal layer 102 is selected, and a substrate is opened from the first metal layer 101 to the dielectric layer 100; The first metal layer 101 and the second metal layer 102 of the substrate are copper-clad layers, that is, the substrate is a copper-clad substrate, and aluminum or other metals may be selected according to actual application requirements.

The dielectric layer 100 is an insulating material and may be epoxy resin (Epoxy Resin), cyanate Ester, glass fiber (Glass Fiber), polyimide (Polyimide), bismaleimide triazine ( Bismaleimide Triazine, BT) or a mixture of insulating materials, or other insulating medium.

The manufacturing process of the groove is controlled by deep milling. The so-called deep milling is a milling machine technology that controls the depth in the Z direction. Due to the limitation of the Z-direction controlled deep milling precision of the milling machine, in order to ensure the integrity of the second metal layer 102 layer. It can also be milled to a safe depth using a milling machine and then burnt through the dielectric layer using laser ablation. The depth of the groove matches the thickness of the chip to be buried. The length and width of the groove are larger than the size of the chip to be buried, so that the groove can accommodate the chip to be buried. The shape of the groove may be a regular rectangular parallelepiped, or a trapezoidal shape, or a stepped shape, which may be designed according to actual process requirements, and is not limited herein. For the more intuitive expression in the drawings, the groove is uniformly represented. The shape of the growing cube.

Figure 2b, a non-conductive bonding material is applied to the bottom surface of the groove to form a bonding layer 103;

The adhesive layer 103 is applied in such a manner that when the chip is in contact with the bottom surface of the groove, the first contact surface of the chip has no pad, and the non-conductive bonding material can be coated by stencil printing or dispensing. Covering, the adhesion between the chip and the substrate bonded to the substrate groove through the adhesive layer has greater adhesion, so that the reliability of the connection is higher.

2c, the first contact surface of the chip 107 is butt-bonded to the adhesive layer 103, so that the chip 107 is buried in the recess;

Through this step, the step of initially fixing the chip 107 to the groove of the substrate is completed.

Figure 2d, the first metal layer 101 and the second contact surface of the chip are coated with a photosensitive material to form a photosensitive material coating layer 108;

Figure 2e, the recesses and the apertures around the chip 109 may also be filled with a photosensitive material or filled with other insulating filler material;

The filling effect between the chip and the substrate can be better by filling the groove with the pores around the chip. Figure 2f, blocking the gap portion of the pad on the second contact surface of the chip;

The photosensitive material coating layer 108 is exposed, developed, and cured to block the gap portion of the pad on the second contact surface of the chip and block the portion of the first metal layer 101 where the copper surface needs to be retained.

Figure 2g, the wiring is disposed on the first contact surface and the second contact surface of the chip, and the corresponding arrangement on the substrate Place the wiring to form a wiring layer.

The wiring may be disposed on the second contact surface of the chip by sputtering or copper plating, electroplating, exposure, development, etching, or the like, and wiring is formed on the first metal layer 101 of the substrate corresponding to the second contact surface to form a wiring layer At the same time, wiring is provided on the adhesive layer 103, and wiring is provided on the second metal layer 102 of the substrate corresponding to the adhesive layer 103 to form a wiring layer. At this point, the production of the double-panel has been completed. If it is necessary to add layers, the lamination technique or the layer-adding method can be used to continue to produce the multilayer wiring.

The following two application examples will describe the case where there are also pads on the first contact surface of the chip. There is also a pad on the first contact surface, and the first contact surface also needs to be electrically connected to the substrate. Therefore, the method of directly applying the non-conductive bonding material to the bottom surface of the groove to form the bonding layer cannot be applied. Bond the chip.

Referring to FIG. 3a to FIG. 3g, there are shown schematic diagrams of process steps of another application example of the method for packaging a chip embedded substrate of an embodiment, including the following steps:

3a, a substrate having a first metal layer 101, a dielectric layer 100, and a second metal layer 102 is selected, and a recess penetrating from the first metal layer 101 to the dielectric layer 100 is formed on the substrate;

The depth of the groove is matched with the thickness of the chip to be buried. When the substrate needs to be embedded with a plurality of chips having different thicknesses, the chip of different thickness is ensured to be coplanar after being encapsulated into the substrate, and the length and width of the groove are Both are larger than the size of the desired embedded chip so that the recess is sufficient to accommodate the chip to be buried.

The first contact surface of the chip has a pad, and the bottom surface of the groove communicates with the second metal layer 102, that is, the groove penetrates the first metal layer 101 and the dielectric layer 100, and reaches the second metal layer 102, which can be more conveniently implemented. An electrical connection of the first contact surface of the chip to the substrate. Of course, when the first contact surface of the chip has a pad, the bottom surface of the groove may not abut the second metal layer 204, and the first contact surface of the chip is electrically connected to the substrate by using a metal via hole.

Figure 3b, the conductive bonding material is formed on the bottom surface of the groove forming a solder joint 104;

In this step, a solder joint 104 may be formed on the bottom surface of the groove by screen printing or dispensing.

Figure 3c, the first contact surface of the chip 107 is butt-bonded to the solder joint 104, so that the chip 107 is fixed to the recess;

Figure 3d, the first metal layer 101 and the second contact surface of the chip 107 coated with a photosensitive material to form a photosensitive material coating layer 108;

Figure 3e, the recesses 109 and the apertures 109 around the chip 107 can also be filled with photosensitive material or other The insulating filling material is filled so that the chip 107 is better fixed to the groove of the substrate; FIG. 3f, the gap portion between the pads on the second contact surface of the chip 107 is blocked;

In this step, the photosensitive material coating layer 108 is exposed, developed, and cured to block the gap portion between the pads on the second contact surface of the chip.

In Fig. 3g, wiring is formed on the first contact surface and/or the second contact surface of the chip by sputtering or copper plating, plating, etching, or the like, and wiring is formed correspondingly on the substrate to form a wiring layer.

In the embodiment, the first contact surface and the second contact surface of the chip 107 have pads, which can be used in the first contact surface and the second contact of the chip by sputtering or copper plating, electroplating, exposure, development, etching, and the like. Wiring is provided on the surface, and a corresponding wiring connected to the wiring on the chip is provided on the substrate to electrically connect the chip to the substrate. At this time, the production of the double-panel has been completed, and if it is necessary to add layers, the conventional lamination technique or the build-up method can be used to continue to fabricate the multilayer wiring.

Referring to FIG. 4a to FIG. 4h, a schematic diagram of a process step of another application example of the method for packaging a chip embedded substrate of the embodiment is shown, which includes the following steps:

4a, a substrate having a first metal layer 101, a dielectric layer 100, and a second metal layer 102 is selected, and a recess from the first metal layer 101 to the dielectric layer 100 is formed on the substrate;

The depth of the groove is matched with the thickness of the chip to be buried. When the substrate needs to be embedded with a plurality of chips of different thicknesses, the chip of different thickness is ensured to be coplanar after being recessed into the groove of the substrate, and the length and width of the groove are Both are larger than the size of the desired embedded chip so that the recess is sufficient to accommodate the chip to be buried.

The first contact surface of the chip has a pad, and the bottom surface of the groove communicates with the second metal layer 102, that is, the groove penetrates the first metal layer 101 and the dielectric layer 100, which can facilitate the subsequent electrical connection between the first contact surface of the chip and the substrate. connection. Of course, when the first contact surface of the chip has a pad, the bottom surface of the groove may not communicate with the second metal layer 204, and then the electrical connection between the first contact surface of the chip and the substrate is realized by using a metal via blind via.

Figure 4b, the corresponding recess 105 is punched in the bottom surface of the groove;

The dimples 105 can be formed on the underside of the recess by a laser drill process or etching technique.

Figure 4c, a solder ball or a conductive bonding material is implanted in the pit 105 to form a solder joint 106;

In this embodiment, the bonding of the subsequent chip 107 and the solder joint 106 is realized by forming the solder joint 106 in the recess 105, and the contact area of the second metal layer 102 and the solder joint 106 is increased, and the bonding of the chip 107 and the solder joint 106 is performed. better result.

4d, the first contact surface of the chip 107 is butt-bonded to the solder joint 106, thereby making the chip 107 Buried into the groove;

Figure 4e, the first metal layer 101 and the second contact surface of the chip are coated with a photosensitive material to form a photosensitive material coating layer 108;

Figure 4f, the recesses and the apertures 109 around the chip may also be filled with a photosensitive material or filled with other insulating filler material;

Figure 4g, blocking the gap portion of the pad on the second contact surface of the chip, and blocking the portion of the first metal layer 101 where the copper surface needs to be retained, by the exposure, development and curing of the photosensitive layer; Figure 4h, Techniques such as sputtering or copper immersion, electroplating, etching, etc., are provided with wiring on the first contact surface and/or the second contact surface of the chip, and corresponding wirings are formed on the substrate to form a wiring layer to electrically connect the chip to the substrate.

In this embodiment, the first contact surface and the second contact surface of the chip have pads, which can be on the first contact surface and the second contact surface of the chip by sputtering or copper plating, electroplating, exposure, development, etching, and the like. A wiring is provided, and a corresponding wiring connected to the wiring on the chip is provided on the substrate to form a wiring layer, and electrical connection between the chip and the substrate is realized. At this point, the production of the double-panel has been completed, and if it is necessary to add layers, the lamination technique or the layer-adding method can be used to continue to fabricate the multilayer wiring.

Referring to FIG. 5, there is shown a process step diagram of another application example of a package embedding method of a chip embedded substrate of an embodiment, for packaging a plurality of chips of different thicknesses, including the following steps:

5 is a cross-sectional view of the substrate 200A-A, the substrate 200 is opened from the first metal layer 203 to the dielectric layer 202 with different depths of the same number of chips as the desired package;

凹槽The groove is carved by the deep milling process. The depth of the groove matches the thickness of the chip to be buried, which ensures the coplanarity of the front side of the chip when multiple chips are buried. The length and width of the groove are larger than The size of the chip needs to be buried so that the recess can accommodate enough of the chip to be buried.

When the first contact surface of the chip has no pad, the bottom surface of the groove communicates with the second metal layer 204 or does not communicate with the second metal layer 204; when the first contact surface of the chip has a pad, the bottom surface of the groove and the second The metal layer 204 is connected to ensure that the first contact surface of the chip is easy to form an electrical connection. Of course, when the first contact surface of the chip has a pad, the bottom surface of the groove may not communicate with the second metal layer 204, but the metal is used instead. The method of guiding the blind vias realizes the electrical connection between the first contact surface of the chip and the substrate.

Since the following steps are the same as the implementation of the application example, the following steps are not given, including:

Connecting the first contact surface of the chip having the first contact surface and the second contact surface to the first metal layer The way corresponding to the buried groove corresponding thereto;

This step is the same as the above application example. According to the actual process requirements, the bottom surface of the groove can be coated with a non-conductive bonding material, a solder joint is formed directly on the bottom surface of the groove, or a corresponding pit is formed on the bottom surface of the groove to form a pit. The way of solder joints bonds the chip to the substrate.

A wiring layer may be disposed on the first contact surface and the second contact surface of the chip by sputtering or copper plating, electroplating, exposure, development, etching, etc., and a corresponding wiring connected to the wiring layer on the chip may be disposed on the substrate The layer is used to electrically connect the chip to the substrate. The wiring layer is composed of sputtered Ti/Cu, deposited Cu, electroplated Cu or other conductive metal.

Embodiment 2

Referring to FIG. 6, there is shown a flow chart of still another embodiment of a method of packaging a chip embedded in a substrate. The chip has a first contact surface and a second contact surface, and includes the following steps:

S601, the substrate is opened at least one through hole, the number of the through holes is the same as the number of required packaged chips, and the through holes penetrate the substrate;

The substrate may be a single panel, a double panel or a multilayer panel.

S602, taking a thick copper foil to etch a convex portion consistent with the position distribution of the through hole;

5603, the substrate and the thick copper foil are laminated and connected through the insulating dielectric layer, the through hole and the convex portion form a groove, and the depth of the groove matches the thickness of the chip to be buried, when the substrate needs to be embedded with a plurality of different thicknesses When the chip is used, it is used to ensure that chips of different thicknesses are packaged into the substrate and remain coplanar;

5604, embedding the chip into the recess;

S605, a wiring is disposed on the first contact surface and/or the second contact surface of the chip, and a wiring is disposed on the substrate, and a wiring layer is formed to electrically connect the substrate and the chip.

The specific application examples of this embodiment will be described in more detail below with reference to Figs. 7a to 7e.

Referring to FIG. 7a to FIG. 7c, a schematic diagram of a process packaging step is shown. The method for packaging a chip embedded in a substrate for packaging a plurality of chips of different thicknesses includes the following steps: FIG. 7a Opening the same number of through holes 301 as the desired package, the through holes penetrating through the first metal layer 303, the dielectric layer 302 and the second metal layer 304; FIG. 7b, taking the thick copper foil 305 to etch and the via position a uniformly distributed convex portion; wherein the height of the convex portion is designed according to the thickness of the chip, and the height of the convex portion is equal to the thickness of the chip Anti-proportional relationship. 7c, the substrate 300 and the thick copper foil 305 are laminated and connected through the insulating dielectric layer 306, and the through hole 301 and the convex portion form a groove; the depth of the groove matches the thickness of the chip to be buried, when the substrate needs to be buried When there are multiple chips with different thicknesses, the chips of different thicknesses are ensured to be coplanar after being encapsulated into the substrate, and the length and width of the grooves are larger than the size of the embedded chip, so that the grooves can be sufficiently accommodated. Buried chip. Connecting a first contact surface of the chip having the first contact surface and the second contact surface to the first metal layer, embedding a recess corresponding to the chip; disposing on the first contact surface and the second contact surface of the chip, and the substrate The corresponding arrangement is formed to form a wiring layer for realizing electrical connection between the substrate and the chip.

The above two steps are the same as the embodiment of the foregoing application example, so there is no illustration. According to the actual process requirements, the bottom surface of the groove can be coated with a non-conductive bonding material, and a solder joint can be directly formed on the bottom surface of the groove or first in the groove. The chip and the substrate are bonded in such a manner that the bottom surface is formed by corresponding pits and then solder joints are formed, and electrical connection between the substrate and the chip is realized as needed. Embodiment 3 FIG. 8 is a schematic flow chart of still another embodiment of a method for packaging a chip embedded in a substrate. The chip has a first contact surface and a second contact surface, and includes the following steps:

5801, the substrate is opened with at least one through hole, and the number of the through holes is the same as the number of required packaged chips;

5802, coating a surface of the second metal layer with a photosensitive material to form a photosensitive material layer;

5803, connecting the second contact surface of the chip to the photosensitive material layer, so that the chip is buried in the through hole;

5804, filling a gap between the chip and the through hole into the bonding material for fixing the chip;

5805, removing the photosensitive material layer;

5806, printing a conductive paste on the first contact surface;

5807, providing wiring on the first contact surface and/or the second contact surface of the chip, and on the substrate Corresponding to the provision of wiring, a wiring layer is formed to electrically connect the substrate and the chip. The following steps are further described in conjunction with FIG. 9a to FIG. 9d, which are schematic diagrams showing specific steps of a specific application example of a method for packaging a chip embedded in a substrate, and a chip embedded in a substrate package provided in this embodiment. The method includes the following steps: In FIG. 9a, the substrate 400 is opened with the same number of through holes 401 as the required package, and the through hole

401 through the first metal layer 403, the dielectric layer 402 and the second metal layer 404;

Figure 9b, a UV film 405 is adhered on the surface of the second metal layer 404. The UV film is a film-like substance having a bonding effect, and loses viscosity after UV light irradiation;

Figure 9c, bonding the second contact surface of the chip 406 to the UV film 405;

The coplanarity of the chips of different thicknesses can be ensured by the adhesion between the coplanar UV film and the second contact surface of the chips of different thicknesses.

9d, the gap between the chip 406 and the through hole 401 is filled with a bonding material to form a filling adhesive layer 407 for fixing the chip 406; the bonding material layer 407 is a photosensitive resin or other bonding material, and is adhered. The junction material is thermally conductive or thermally non-conductive, depending on the electrical connection needs.

After the filling adhesive material layer 407 is fixed to the chip 406, the UV film 405 is removed;

The photosensitive resin is printed on the second contact surface of the chip; the first contact surface and/or the second contact surface of the chip are disposed, and a corresponding wiring layer is formed on the substrate to electrically connect the substrate to the chip.

The same steps in the above process steps as those in the above application examples are not described herein. The package structure in which the chip is buried in the substrate will be described in detail below.

A package structure of a chip embedded in a substrate includes a substrate, a chip and a wiring layer, the substrate is provided with at least one chip embedding portion, the chip has a first contact surface and a second contact surface, and the chip embedding portion is a through hole or a groove, and the chip is buried The depth of the entrance portion is matched with the thickness of the corresponding embedded chip, and the wiring layer includes a wiring disposed on the first contact surface and/or the second contact surface of the chip, and a wiring disposed on the substrate corresponding to the chip for realizing the chip and the substrate Wiring for electrical connections. For the chip embedding portion, the through hole and/or the recess, in different application embodiments, at least one of the chip embedding portions may be a groove or a through hole, or may be a groove and a through hole. The substrate may be a single-panel, a double-panel or a multi-layered board that has been processed with an inner layer. In the embodiment, for a more intuitive expression, the dual-panel is taken as an example to describe the embedded substrate package structure. A specific application example of the chip-embedded substrate package structure will be described in more detail below. It can be understood that the corresponding structures in the following embodiments can be used in combination. Embodiment 4 Referring to FIG. 10, a schematic structural view of an embodiment of a package structure in which a chip is embedded in a substrate is shown. A package structure in which a chip is embedded in a substrate includes: a substrate having a first metal layer 101, a dielectric layer 100, and a second metal layer 102;

The groove is formed by slotting the first metal layer 101 of the substrate to the dielectric layer 100; the depth of the groove is matched with the thickness of the chip to be buried, and the chip is coplanar when the plurality of chips are buried, and the groove is Both the length and the width are larger than the size of the desired embedded chip so that the recess can accommodate the chip to be buried. The chip 107 has a first contact surface and a second contact surface. The first contact surface of the chip is connected to the bottom surface of the recess through the solder joint 103 disposed on the bottom surface of the recess, and the chip is initially buried in the recess, so that the chip and the recess are The fixing effect is better, and the groove 109 and the pores 109 around the chip are filled with the photosensitive material or filled with other insulating filling materials;

The wiring layer is provided with wirings on the first contact surface and the second contact surface of the chip, and corresponding wirings are formed on the substrate such that the substrate and the chip are electrically connected. Next, the build-up line is formed. The insulating dielectric layer 110 is formed of sputtered copper or deposited copper, electroplated copper, or the like, or may be composed of other conductive metals. The structure of the fifth embodiment of the package structure of the chip embedded substrate includes: a substrate; at least one groove formed in the substrate, the depth of the groove is matched with the thickness of the chip to be buried, and the substrate needs to be buried more When chips of different thicknesses are ensured, chips of different thicknesses are packaged into the chip. The groove of the substrate is coplanar, the length and the width of the groove are larger than the size of the desired embedded chip, so that the groove can be enough to accommodate the chip to be buried; at least one chip, the chip has a first contact surface and The second contact surface is embedded in the corresponding recess; the wiring layer is provided with wiring on the first contact surface and/or the second contact surface of the chip, and the corresponding wiring is formed on the substrate, so that the substrate and the chip are electrically connected. The substrate may be a single panel, a double panel or a multi-panel. When the first contact surface of the chip has no pad, the non-conductive bonding material forms a bonding layer on the bottom surface of the groove, and the first contact surface and the groove are formed by the bonding layer. The bottom is connected. When the second contact surface of the chip has a pad, the second contact surface pad is formed with a conductive bonding material to form a solder joint corresponding to the pad, and the first contact surface and the bottom surface of the groove are connected by the solder joint, or in the second The metal layer etches the pit corresponding to the second contact surface pad, and then implants a solder ball or a conductive bonding material on the pit to form a solder joint, and connects the second contact surface and the bottom surface of the recess through the solder joint, and then The wiring layer and the second contact surface solder joint are connected by a metal blind hole. As shown in FIG. 11, the chip-embedded substrate package structure includes: a substrate further comprising an insulating layer 300, a line 301 formed by the second metal layer, a first metal layer laminated insulating medium or an insulating medium 303 coated in other forms. Thereafter, after exposure development and conduction through a process such as sputtering, chemical deposition, electroplating, etching, etc., the line 301 and the line 302 are made of a first metal layer, sputtered Ti/Cu or other metal, chemical copper, Electroplated copper and the like; because the chips to be buried have different thicknesses, the four grooves opened on the substrate have a depth matching the chip to be buried, and the groove corresponds to the buried single-sided conduction chip 306 or double The surface conduction chip 308, the gap between the groove and the chip is filled with the underfill 304. In order to realize the connection between the contact surface of the double-sided conductive chip and the bottom surface of the recess and the line 301, the solder joint 309 and the via blind via 310 may be connected to the line 301, or the solder joint of the chip 308 may be directly connected to the line 301. . The electrical connection between line 301 and line 302 is achieved by providing vias 307. It can be seen from the above package structure that the depth of the groove matches the thickness of the chip to be buried. When the substrate needs to be embedded with a plurality of chips of different thicknesses, the chips of different thicknesses are ensured. The grooves of the substrate are coplanar, and the electrical connection between the single side of the chip and the substrate or the electrical connection of the both sides to the substrate can be conveniently realized.

The package structure of the chip embedded in the substrate is characterized in that: the package structure of the chip embedded in the substrate comprises: a substrate having a same number of through holes as the required packaged chip; the copper foil and the copper foil have a pass a convex portion having a uniform hole position distribution, the height of the convex portion being inversely proportional to the thickness of the chip; an insulating dielectric layer for connecting the substrate and the copper foil, so that the through hole and the convex portion are fitted to form a groove, and the depth of the groove is The thickness of the chip to be embedded is matched. When the substrate needs to be embedded with a plurality of chips of different thicknesses, the chips of different thicknesses are ensured to be coplanar after being recessed into the groove of the substrate, and the length and width of the groove are larger than required. The chip is sized such that the recess is sufficient to accommodate the chip to be buried; at least one chip having a first contact surface and a second contact surface, and the chip is buried by connecting the first contact surface to the bottom surface of the recess a wiring layer, a wiring disposed on the first contact surface and/or the second contact surface of the chip, and a corresponding wiring formed on the substrate, such that the substrate and the chip are electrically connected . The substrate may be a single panel, a double panel or a multi-panel. When the first contact surface of the chip has no pad, the non-conductive bonding material forms a bonding layer on the bottom surface of the groove, and the first contact surface and the groove are formed by the bonding layer. The bottom is connected. When the second contact surface of the chip has a pad, the second contact surface pad is formed with a conductive bonding material to form a solder joint corresponding to the pad, and the first contact surface and the bottom surface of the groove are connected by the solder joint, or in the second The metal layer etches the pit corresponding to the second contact surface pad, and then implants a solder ball or a conductive bonding material on the pit to form a solder joint, and connects the second contact surface and the bottom surface of the recess through the solder joint, and then The wiring layer and the second contact surface solder joint are connected by a metal blind hole. As shown in FIG. 12, the chip-embedded substrate package structure includes: a substrate, further including an insulating layer 300, a line 301 formed by the second metal layer, a first metal layer laminated insulating medium or an insulating medium 303 coated in other forms. , through exposure development and through the sputtering, chemical deposition, electroplating, etching and other processes formed after the conduction line 302, the line 301 and line 302 are composed of a first metal layer, sputtered Ti/Cu or other metal, chemical copper, electroplated copper, etc.; since the chips to be buried have different thicknesses, the four grooves opened on the substrate have and are required The buried chip matching depth matching, the corresponding buried single-sided conducting chip 306 or the double-sided conductive via chip is connected to the line 301 by the contact surface of the groove bottom surface, by providing the conductive bonding material layer 308 and The line 309 formed by the thick copper foil is in communication with the line 301, and the electrical connection between the line 301 and the line 302 is realized by providing the via hole 307, and the wiring layer 301 is connected to the outside by providing the conduction blind hole 310.

It can be seen from the above package structure that the depth of the groove matches the thickness of the chip to be buried. When the substrate needs to be embedded with a plurality of chips of different thicknesses, the chip of different thickness is packaged into the groove of the substrate and is coplanar. Moreover, the electrical connection between the single side of the chip and the substrate or the electrical connection of both sides to the substrate can be conveniently realized.

The chip-embedded substrate encapsulation method and the structure thereof provided by the present invention are described in detail above. For those skilled in the art, according to the idea of the embodiment of the present invention, there are some changes in the specific implementation manner and application range. In conclusion, the contents of this specification are not to be construed as limiting the invention.

Claims

Rights request

A method of packaging a chip embedded in a substrate, wherein the chip has a first contact surface and a second contact surface, and the method comprises the following steps:

Step S2: embedding the chip into the chip embedding portion;

Step S3: a wiring layer is formed on the first contact surface and/or the second contact surface of the chip, and the corresponding wiring on the substrate, so that the substrate and the chip are electrically connected.

2. The method of packaging a chip embedded substrate according to claim 1, wherein the chips to be packaged have different thicknesses.

The method of encapsulating a chip embedded substrate according to claim 1, wherein the specific process of forming the groove in step S1 is:

Taking a thick copper foil to etch a convex portion consistent with the position distribution of the through hole;

Laminating the substrate and the thick copper foil through an insulating dielectric layer, the convex portion being fitted into the through hole to form the groove;

Or opening the groove directly to the substrate.

4. The method of packaging a chip embedded substrate according to claim 1, wherein the specific process of embedding the chip in the recess is:

Applying a non-conductive bonding material to the bottom surface of the groove to form a bonding layer;

The first contact surface of the chip is butt bonded to the bonding layer such that the chip is buried in the recess.

5. The method of packaging a chip embedded substrate according to claim 1, wherein the specific process of embedding the chip in the recess is:

Pointing a conductive bonding material on a bottom surface of the recess, forming a solder joint on a bottom surface of the recess; bonding the first contact surface of the chip to the solder joint, such that the chip is buried in the Groove.

6. The method of packaging a chip embedded substrate according to claim 1, wherein: the specific process of embedding the chip in the recess is:

Pitting a pit on the bottom surface of the groove; Depositing a solder ball or a conductive bonding material at the pit, forming a solder joint in the recess; bonding the first contact surface of the chip to the solder joint, so that the chip is buried The groove.

The method of packaging a chip embedded substrate according to claim 1, wherein the step S2 is specifically:

Coating a photosensitive material on one surface of the substrate to form a photosensitive material layer;

Connecting the second contact surface of the chip to the photosensitive material layer, so that the chip is fixed to the overnight L;

A bonding material for fixing the chip is filled in a gap between the chip and the through hole; and the photosensitive material layer is removed.

8. A package structure in which a chip is embedded in a substrate, wherein the package structure in which the chip is embedded in the substrate comprises a substrate, a chip, and a wiring layer.

The chip package structure according to claim 8, further comprising a copper foil and an insulating dielectric layer, wherein the copper foil has a convex portion conforming to a position distribution of the through hole, and the height of the convex portion is The thickness of the chip is inversely proportional. The insulating dielectric layer is disposed between the substrate and the copper foil to connect the substrate and the copper foil, and the through hole and the convex portion are formed to be formed. Said groove.

10. The chip package structure of claim 8, wherein the at least one chip has a different thickness.

The package structure of the chip embedded substrate according to claim 8, wherein: when the first contact surface of the chip has no pad, the non-conductive bonding material forms a bonding layer on the bottom surface of the groove. And connecting the first contact surface and the bottom surface of the groove by the bonding layer.

The package structure of the chip embedded substrate according to claim 8, wherein: when the second contact surface of the chip has a pad, the second contact surface pad is formed by using a conductive bonding material a solder joint corresponding to the pad, connecting the first contact surface and the bottom surface of the groove through the solder joint, and / or

Etching a pit corresponding to the second contact surface pad in the second metal layer, and then implanting a solder ball or a conductive bonding material on the pit to form a solder joint through the solder joint The first contact surface is connected to the bottom surface of the groove.