CN101136385A - Internally burying type chip packaging manufacture process and circuit board having the same - Google Patents
Internally burying type chip packaging manufacture process and circuit board having the same Download PDFInfo
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- CN101136385A CN101136385A CN 200610112234 CN200610112234A CN101136385A CN 101136385 A CN101136385 A CN 101136385A CN 200610112234 CN200610112234 CN 200610112234 CN 200610112234 A CN200610112234 A CN 200610112234A CN 101136385 A CN101136385 A CN 101136385A
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- line layer
- chip
- dielectric material
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- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 238000000034 method Methods 0.000 title abstract description 9
- 238000004806 packaging method and process Methods 0.000 title description 4
- 239000003989 dielectric material Substances 0.000 claims abstract description 43
- 229910000679 solder Inorganic materials 0.000 claims abstract description 3
- 239000000758 substrate Substances 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 238000009413 insulation Methods 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 238000003825 pressing Methods 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 claims description 4
- 239000007787 solid Substances 0.000 claims description 4
- 229910000906 Bronze Inorganic materials 0.000 claims description 3
- 239000010974 bronze Substances 0.000 claims description 3
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 238000012545 processing Methods 0.000 abstract description 3
- 238000012858 packaging process Methods 0.000 abstract 2
- 239000013078 crystal Substances 0.000 abstract 1
- 238000003475 lamination Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000004080 punching Methods 0.000 description 4
- 238000006116 polymerization reaction Methods 0.000 description 3
- 230000003319 supportive effect Effects 0.000 description 3
- 239000004743 Polypropylene Substances 0.000 description 2
- 230000003064 anti-oxidating effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- 229910000897 Babbitt (metal) Inorganic materials 0.000 description 1
- 229910001074 Lay pewter Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 229910000743 fusible alloy Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920003192 poly(bis maleimide) Polymers 0.000 description 1
- -1 polypropylene Polymers 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
This invention relates to a packaging process for built-in chips and a circuit base board with the built-in chip, in which, the packaging process includes: connecting a chip to a first circuit layer on a loading plate then to be pressed onto a dielectric material by a stitching lamination plate so as to bury the chip in the dielectric material and form a circuit base board with a built-in chip, which includes at least one convex block connected with a joint pad of the first circuit layer by solder. This invention can replace a current method of pore-forming with laser and processing circuit since the cover crystal jointing process can provide better reliability of joint and accuracy of contraposition.
Description
Technical field
The invention relates to a kind of chip encapsulating manufacturing procedure and structure thereof, and particularly relevant for a kind of built-in type chip encapsulating manufacturing procedure and bury the circuit substrate of chip in having.
Background technology
In recent years, along with making rapid progress of electronic technology, coming out one after another of high-tech electronic industry makes electronic product more humane, with better function constantly weed out the old and bring forth the new, and towards light, thin, short, little trend design.In these electronic products, can dispose a circuit substrate usually; this circuit substrate is in order to carry single chip or a plurality of chip; with data processing unit as electronic product; yet chip configuration can cause loaded area to increase on circuit substrate; thereby how chip is built in the circuit substrate, become current key technology.
Fig. 1 please refer to Fig. 1 for the existing profile that buries the circuit substrate of chip in having, and this circuit substrate 10 comprises a substrate 100, a plurality of chip 110, a dielectric layer 120, a line layer 130, anti oxidation layer 140 and welding cover layer 150.Wherein, a plurality of chips 110 are positioned on the substrate 100, and dielectric layer 120 then is formed on the substrate 100 and covers a plurality of chips 110.In addition, the conductive hole 122 that the weld pad 112 of each chip 110 is made by laser is connected with line layer 130, and line layer 130 again with corresponding conductive plunger 132 connections, to form a circuit substrate 10 that buries chip 110 in having.
By existing circuit substrate 10 as can be known, chip 110 adopts configuration arrangement mode at grade, and when increasing the number of chip 110 as if desire, then opposing substrates 100 areas also must increase thereupon.In addition, making conductive hole 122 with laser easily causes the skew of Aligning degree and yield is reduced.
Summary of the invention
Purpose of the present invention is providing a kind of built-in type chip encapsulating manufacturing procedure exactly, and it is by the chip bonding technology, to improve the yield of chip join.
A further object of the present invention provides a kind of circuit substrate with inner embedded component, and it is by the yield of chip package with the raising chip join.
The present invention proposes a kind of built-in type chip encapsulating manufacturing procedure, comprises the following steps: at first, provide a support plate and a sheet metal, and sheet metal is disposed on the support plate; The pattern metal sheet, to form one first line layer on support plate, first line layer comprises at least one joint sheet; Form a scolder on joint sheet; Dispose a chip on support plate, chip has at least one projection, and projection electrically connects by scolder and joint sheet; Cover a dielectric material on line layer, and chip buried-in is in this dielectric material; Provide a laminate and one second line layer, and second line layer is disposed on the laminate; And carry out a pressing step, make that second line layer on the laminate is pressed in the dielectric material.
Described according to embodiments of the invention, above-mentioned dielectric material comprises a film, and film is formed by the gel of semi-solid preparation resin material.In addition, film has an opening corresponding to chip, and film is when being covered on the line layer, and chip is arranged in opening.
Described according to embodiments of the invention, above-mentioned dielectric material is covered in after the line layer, more comprises the heating dielectric material, makes it to solidify.In addition, dielectric material more comprises removing support plate and laminate after solidifying.In addition, after dielectric material solidifies, more comprise the consistent at least hole of formation in dielectric material, and insert a conducting resinl in perforation, and corresponding first line layer and second line layer of connecting in the two ends of perforation.Moreover first line layer disposes one first contact corresponding to an end of perforation, and second line layer disposes one second contact corresponding to the other end of perforation, and first contact and second contact are by the conducting resinl mutual conduction.
Described according to embodiments of the invention, the second above-mentioned line layer comprises a screen, and it is covered on the surface of dielectric material corresponding to chip, to prevent Electromagnetic Interference.
Described according to embodiments of the invention, above-mentioned support plate comprises a metallic plate or an insulation board, and sheet metal comprises a gum copper sheet.In addition, laminate comprises a metallic plate or an insulation board, and second line layer comprises a patterning gum copper layer.
The present invention proposes a kind of circuit substrate with inner embedded component in addition, and it comprises a substrate, an inner embedded component and a screen.Substrate comprises one first line layer, a dielectric layer and one second line layer, and first line layer lays respectively in relative two surfaces of dielectric layer with second line layer, and has a conductive through hole in the dielectric layer, and its conducting is in first line layer and second line layer.In addition, be embedded in the dielectric layer in the inner embedded component, and electrically connect with first line layer.In addition, screen is covered in the surface of dielectric layer corresponding to inner embedded component.
Described according to embodiments of the invention, the first above-mentioned line layer disposes one first contact corresponding to an end of conductive through hole, and second line layer disposes one second contact corresponding to the other end of conductive through hole, and first contact and second contact are by the conductive through hole mutual conduction.
Described according to embodiments of the invention, above-mentioned screen comprises a bronze medal layer.In addition, the screen and second line layer can form in the lump.
Described according to embodiments of the invention, above-mentioned inner embedded component comprises chip, and chip has at least one projection, and the first line layer correspondence has a joint sheet, and itself and projection electrically connect.In addition, inner embedded component comprises electric capacity, resistance or inductance.
The present invention is because of adopting the chip bonding technology of high yield, earlier chip is connected to first line layer on the support plate, again via the pressing laminate on dielectric material so that chip buried-in is in dielectric material, and then replaces the laser punching and the circuit that bury chip in existing and make.Therefore, the present invention can improve the yield of chip join.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the existing profile that buries the circuit substrate of chip in having.
Fig. 2 A～Fig. 2 G illustrates the schematic flow sheet of the built-in type chip encapsulating manufacturing procedure of one embodiment of the invention respectively.
Fig. 3 illustrates the schematic diagram of the chip-packaging structure of one embodiment of the invention.
10,20: circuit substrate 100: substrate
110: chip 112: weld pad
120: dielectric layer 122: conductive hole
130: line layer 132: conductive plunger
140: anti oxidation layer 150: insulating barrier
200: support plate 210: sheet metal
Contact 220 in 216: the first: insulating barrier
222: scolder 230: dry film
240: chip 242: projection
244: the back side 250: dielectric material
252: opening 260: laminate
266: the second contacts of 262: the second line layers
270: dielectric layer 272: perforation
274: conducting resinl 280: screen
300: chip-packaging structure 310: dielectric layer
312: conductive hole 320: the surface lines layer
330: soldered ball
Embodiment
Fig. 2 A～Fig. 2 G illustrates the schematic flow sheet of the built-in type chip encapsulating manufacturing procedure of one embodiment of the invention respectively, wherein Fig. 2 A～Fig. 2 E illustrates chip and is disposed at step on the support plate in the mode of covering brilliant combination, and Fig. 2 F～Fig. 2 G illustrates the step that is shaped in a dielectric material and pressing chip buried.Though present embodiment is an example with the encapsulation procedure of one chip, the present invention also can be used on the encapsulation procedure of multicore sheet, cuts into the encapsulating structure that has one chip or have a plurality of chips afterwards again.
Please refer to Fig. 2 A～Fig. 2 B, a support plate 200 and a sheet metal 210 are provided earlier, and pattern metal sheet 210 is to form first line layer 212.Wherein, support plate 200 for example is metallic plate or the insulation board with intensity and supportive, but also can be soft film or film, in order to bearing metal sheet 210, and sheet metal 210 for example is gum Copper Foil or other conducting strip, and it is attached on the support plate 200, with expose, the step of patterning such as development, etching, so that first line layer 212 has at least one joint sheet 214, and the quantity of joint sheet 214 can decide according to the number of actual I/O signal.In the present embodiment, the dry-etching that can be traditional or the mode of Wet-type etching are carried out patterned etch to sheet metal 210, to form the first required line layer 212.
Then, please refer to Fig. 2 C～Fig. 2 D, form an insulating barrier (insulation layer) 220 on support plate 200, and cover a removable dry film 230, to carry out follow-up electroplating process or printing process.Wherein, insulating barrier 220 can appear the upper surface of the joint sheet 214 of first line layer 212, and dry film 230 is covered in other surface (for example surface of first contact 216) of first line layer 212, amasss in the upper surface of joint sheet 214 so that electroplate scolder 222 Shen.In the present embodiment, electroplating scolder 222 for example is leypewter or other low-melting alloy etc., and its purpose that is formed on the joint sheet 214 is projection 242 and the bond strength between the joint sheet 214 and the precision of strengthening on the chip 240 of contraposition.Certainly, the present invention can also print solder paste form a scolder 222 on joint sheet 214, and its purpose is identical with plating with effect.
Then, please refer to Fig. 2 E, remove dry film 230, and chip 240 is when being disposed on first line layer 212 in the mode of chip bonding, the projection 242 of chip 240 can interconnect by scolder 222 and joint sheet 214, with the media as the electric signal transmission.Because scolder 222 can prevent projection 242 contrapositions skew and increase the intensity that engages, thereby improve the reliability and the yield of chip bonding.In addition,, earlier chip 240 is connected to first line layer 212 on the support plate 200, also can avoids among existing Fig. 1 with laser punching and make the processing procedure of the chip 110 that line layer 130 buries in connecting by the chip bonding technology of high yield.
Then, please refer to Fig. 2 F, cover dielectric material 250 and be pressed on the dielectric material 250, so that be embedded in the dielectric material 250 in the chip 240 with a laminate 260.Wherein, dielectric material 250 for example is the BT resin (Bismaleimide Triazine Resin) or the PP resin insulating material such as (polypropylene) of semi-solid preparation (prepreg), it can react and reach the gel degree and form a film via monomer polymerization (polymerization), and dielectric material 250 optionally added glass cloth (glass fiber) to improve its intensity and supportive before polymerization reaction becomes film.In the present embodiment, when dielectric material 250 was covered on first line layer 212 with the film of semi-solid preparation, film can be pre-formed a suitable opening 252, and it is corresponding to the position at chip 240 places, and was enough to hold chip 240 in opening 252.The purpose of default opening 252 is to avoid in follow-up pressing step, and film is expressed to chip 240 and causes chip 240 to damage.
From the above, when being embedded in the dielectric material 250 in the chip 240, apply pressure to dielectric material 250 equably with laminate 260 again, so that chip 240 and projection 242 thereof intactly are coated in the dielectric material 250.Therefore at this moment, dielectric material 250 is solidified forming not, must carry out heat treated again, makes its molecule produce staggered link (Cross Linking) phenomenon and solidifies.
It should be noted that, laminate 260 is except in order to apply pressure to the dielectric material 250, more can make second line layer 262 in advance on laminate 260, its practice describes in detail at this no longer one by one as making first line layer 212 in Fig. 2 A～Fig. 2 B on a support plate 200.Wherein, laminate 260 for example is metallic plate or the insulation board with intensity and supportive, and second line layer 262 for example is gum copper layer or other metal level of patterning.When laminate 260 was pressed on dielectric material 250, second line layer 262 can be pressed in the dielectric material 250, shown in Fig. 2 F.
Then, please refer to Fig. 2 G, after dielectric material 250 full solidification, support plate 200 and laminate 260 can be by lifting off (lift off) or other the technology that divests is removed, only keep in relative two surfaces of first line layer 212 and the dielectric layer 270 of second line layer 262 after curing, to form a circuit substrate 20 that buries chip 240 in having.Wherein, more can form consistent at least hole 272 by laser punching in the dielectric layer 270, corresponding first line layer 212 and second line layer 262 of connecting in its two ends.In addition, first line layer 212 disposes one first contact 216 corresponding to an end of perforation 272, and second line layer 262 disposes one second contact 266 corresponding to the other end of perforation 272, and first contact 216 and second contact 266 conducting resinl 274 mutual conduction in the perforation 272 are to reach the purpose of signal transmission.
It should be noted that, this circuit substrate 20 is except transmitting the electric signal of chip 240 or other assembly by first and second line layer 212,262, more can comprise a screen 280, it is covered in the surface of the dielectric layer 270 of chip 240 tops, and contacts with the back side 244 maintenance one spacings of chip 240 or with the back side 244 of chip 240.The area of screen 280 is the best with the area more than or equal to chip 240, to stop the electromagnetic wave that is incident in chip 240, arrives the normal operation of chip 240 to avoid Electromagnetic Interference.In the present embodiment, screen 280 can be the metal of a bronze medal layer or other high conductivity, and screen 280 forms also can be via patterning second line layer 262 time in the lump, or independently is formed on the laminate 260 via the mode that attaches, and is pressed in the dielectric layer 270 again.
At last, please refer to the chip-packaging structure 300 of Fig. 3, it illustrates the schematic diagram of making at least one line layer and soldered ball on the circuit substrate 20 of Fig. 2 G, wherein dielectric layer 310 and surface lines layer 320 can be formed on the circuit substrate 20 in regular turn by Layer increasing method, and surface lines layer 320 can electrically connect by second contact 266 of the conductive hole in the dielectric layer 310 312 and second line layer 262.In addition, more configurable a plurality of soldered balls 330 on the surface lines layer 320 are to form the buried chip encapsulation structure 300 of ball lattice arrays (ball grid array).
Bury the chip 240 except interior, present embodiment also can be used in the encapsulation and structure of other inner embedded component, for example passive components such as electric capacity, resistance and inductance are replaced above-mentioned chip 240, can form circuit substrate with inner embedded component, its fabrication steps such as Fig. 2 A～Fig. 2 G are not described in detail in this.
In sum, the present invention is connected to chip first line layer on the support plate earlier because of adopting the chip bonding technology of high yield, again via the pressing laminate on dielectric material, so that chip buried-in is in dielectric material, and then replaces the laser punching and the circuit that bury chip in existing and make.Therefore, the present invention can improve the yield of chip join.In addition, the present invention above chip, preventing electromagnetic interference, thereby makes the chip can normal operation, to reduce the noise that electromagnetic interference was produced by the configuration screen.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the appending claims person of defining.
Claims (18)
1. a built-in type chip encapsulating manufacturing procedure is characterized in that it comprises the following steps:
One support plate and a sheet metal are provided, and this sheet metal is disposed on this support plate;
This sheet metal of patterning, to form one first line layer on this support plate, this first line layer comprises at least one joint sheet;
Form a scolder on this joint sheet;
Dispose a chip on this first line layer, this chip has at least one projection, and this projection electrically connects by this scolder and this joint sheet;
Cover a dielectric material on this line layer, and this chip buried-in is in this dielectric material;
One laminate and one second line layer are provided, and this second line layer is disposed on this laminate; And
Carry out a pressing step, make that this second line layer on this laminate is pressed in this dielectric material.
2. built-in type chip encapsulating manufacturing procedure according to claim 1 it is characterized in that wherein this dielectric material comprises a film, and this film is formed by the gel of semi-solid preparation resin material.
3. built-in type chip encapsulating manufacturing procedure according to claim 2 is characterized in that wherein this film has an opening corresponding to this chip, and this film is when being covered on this first line layer, and this chip is contained in this opening.
4. built-in type chip encapsulating manufacturing procedure according to claim 1 is characterized in that wherein this dielectric material is covered in after this first line layer, more comprises this dielectric material of heating, makes it to solidify.
5. built-in type chip encapsulating manufacturing procedure according to claim 4 is characterized in that more comprising removing this support plate after wherein this dielectric material curing.
6. built-in type chip encapsulating manufacturing procedure according to claim 4 is characterized in that more comprising removing this laminate after wherein this dielectric material curing.
7. built-in type chip encapsulating manufacturing procedure according to claim 4, after it is characterized in that wherein this dielectric material solidifies, comprise that the more consistent at least hole of formation is in this dielectric material, and insert a conducting resinl in this perforation, corresponding this first line layer and this second line layer of connecting in the two ends of this perforation.
8. built-in type chip encapsulating manufacturing procedure according to claim 7, it is characterized in that this first line layer wherein disposes one first contact corresponding to an end of this perforation, and this second line layer disposes one second contact corresponding to the other end of this perforation, and this first contact and this second contact are by this conducting resinl mutual conduction.
9. built-in type chip encapsulating manufacturing procedure according to claim 1 is characterized in that wherein this second line layer comprises a screen, and it is covered on the surface of this dielectric material corresponding to this chip.
10. built-in type chip encapsulating manufacturing procedure according to claim 1 it is characterized in that wherein this support plate comprises a metallic plate or an insulation board, and this sheet metal comprises a gum copper sheet.
11. built-in type chip encapsulating manufacturing procedure according to claim 1 it is characterized in that wherein this laminate comprises a metallic plate or an insulation board, and this second line layer comprises a patterning gum copper layer.
12. built-in type chip encapsulating manufacturing procedure according to claim 1 is characterized in that the mode that wherein forms this scolder comprises zinc-plated or print solder paste.
13. the circuit substrate with inner embedded component is characterized in that it comprises:
One substrate, comprise one first line layer, a dielectric layer and one second line layer, this first line layer is with in this second line layer lays respectively at relative two surfaces of this dielectric layer, and has a conductive through hole in this dielectric layer, and its conducting is in this first line layer and this second line layer;
One inner embedded component, in be embedded in this dielectric layer, and electrically connect with this first line layer; And
One screen is covered in the surface of this dielectric layer corresponding to this inner embedded component.
14. the circuit substrate with inner embedded component according to claim 13, it is characterized in that this first line layer wherein disposes one first contact corresponding to an end of this conductive through hole, and this second line layer disposes one second contact corresponding to the other end of this conductive through hole, and this first contact and this second contact are by this conductive through hole mutual conduction.
15. the circuit substrate with inner embedded component according to claim 13 is characterized in that wherein this screen comprises a bronze medal layer.
16. the circuit substrate with inner embedded component according to claim 13 is characterized in that wherein this screen and this second line layer form in the lump.
17. the circuit substrate with inner embedded component according to claim 13 is characterized in that wherein this inner embedded component comprises chip, this chip has at least one projection, and this first line layer correspondence has a joint sheet, and itself and this projection electrically connects.
18. the circuit substrate with inner embedded component according to claim 13 is characterized in that wherein this inner embedded component comprises electric capacity, resistance or inductance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610112234 CN100514616C (en) | 2006-08-29 | 2006-08-29 | Internally burying type chip packaging manufacture process and circuit board having the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610112234 CN100514616C (en) | 2006-08-29 | 2006-08-29 | Internally burying type chip packaging manufacture process and circuit board having the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101136385A true CN101136385A (en) | 2008-03-05 |
| CN100514616C CN100514616C (en) | 2009-07-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200610112234 Expired - Fee Related CN100514616C (en) | 2006-08-29 | 2006-08-29 | Internally burying type chip packaging manufacture process and circuit board having the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100514616C (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102378502A (en) * | 2010-08-13 | 2012-03-14 | 欣兴电子股份有限公司 | Circuit board and manufacturing method thereof |
| CN102545353A (en) * | 2012-01-11 | 2012-07-04 | 可富科技股份有限公司 | Flip chip technology for flexible film antenna of wireless charger and structure thereof |
| CN102637612A (en) * | 2012-05-03 | 2012-08-15 | 福建华映显示科技有限公司 | Method for fixedly arranging semiconductor chip on circuit substrate and structure of semiconductor chip |
| WO2013037102A1 (en) * | 2011-09-13 | 2013-03-21 | 深南电路有限公司 | Encapsulation method for embedding chip into substrate and structure thereof |
| CN103858227A (en) * | 2011-10-13 | 2014-06-11 | 弗利普芯片国际有限公司 | Wafer level applied RF shields |
| CN104851847A (en) * | 2014-02-14 | 2015-08-19 | 恒劲科技股份有限公司 | Packaging device and manufacturing method therefor |
| CN105789847A (en) * | 2014-12-15 | 2016-07-20 | 财团法人工业技术研究院 | Antenna integrated package structure and fabrication method thereof |
| CN106992170A (en) * | 2015-11-12 | 2017-07-28 | 恩智浦美国有限公司 | The packaging system of multiple planes with embedded electronic device |
| CN107567208A (en) * | 2017-09-07 | 2018-01-09 | 维沃移动通信有限公司 | A kind of printed circuit board (PCB) preparation method and printed circuit board (PCB) |
| WO2018202040A1 (en) * | 2017-05-05 | 2018-11-08 | 华为技术有限公司 | Embedded substrate and manufacturing method therefor |
| CN110459509A (en) * | 2019-07-24 | 2019-11-15 | 浙江荷清柔性电子技术有限公司 | A kind of interconnection packaging method and interconnection package structure of chip |
| CN115295501A (en) * | 2022-08-22 | 2022-11-04 | 讯芯电子科技（中山）有限公司 | Embedded chip package and manufacturing method thereof |
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- 2006-08-29 CN CN 200610112234 patent/CN100514616C/en not_active Expired - Fee Related
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102378502B (en) * | 2010-08-13 | 2013-11-27 | 欣兴电子股份有限公司 | Circuit board and manufacturing method thereof |
| CN102378502A (en) * | 2010-08-13 | 2012-03-14 | 欣兴电子股份有限公司 | Circuit board and manufacturing method thereof |
| WO2013037102A1 (en) * | 2011-09-13 | 2013-03-21 | 深南电路有限公司 | Encapsulation method for embedding chip into substrate and structure thereof |
| CN103858227A (en) * | 2011-10-13 | 2014-06-11 | 弗利普芯片国际有限公司 | Wafer level applied RF shields |
| CN102545353A (en) * | 2012-01-11 | 2012-07-04 | 可富科技股份有限公司 | Flip chip technology for flexible film antenna of wireless charger and structure thereof |
| CN102637612A (en) * | 2012-05-03 | 2012-08-15 | 福建华映显示科技有限公司 | Method for fixedly arranging semiconductor chip on circuit substrate and structure of semiconductor chip |
| CN102637612B (en) * | 2012-05-03 | 2014-07-30 | 福建华映显示科技有限公司 | Method for fixedly arranging semiconductor chip on circuit substrate and structure of semiconductor chip |
| CN104851847B (en) * | 2014-02-14 | 2017-09-08 | 恒劲科技股份有限公司 | Packaging system and preparation method thereof |
| CN104851847A (en) * | 2014-02-14 | 2015-08-19 | 恒劲科技股份有限公司 | Packaging device and manufacturing method therefor |
| CN105789847A (en) * | 2014-12-15 | 2016-07-20 | 财团法人工业技术研究院 | Antenna integrated package structure and fabrication method thereof |
| CN105789847B (en) * | 2014-12-15 | 2019-01-04 | 财团法人工业技术研究院 | Aerial integration formula encapsulating structure and its manufacturing method |
| CN106992170A (en) * | 2015-11-12 | 2017-07-28 | 恩智浦美国有限公司 | The packaging system of multiple planes with embedded electronic device |
| WO2018202040A1 (en) * | 2017-05-05 | 2018-11-08 | 华为技术有限公司 | Embedded substrate and manufacturing method therefor |
| CN107567208A (en) * | 2017-09-07 | 2018-01-09 | 维沃移动通信有限公司 | A kind of printed circuit board (PCB) preparation method and printed circuit board (PCB) |
| CN110459509A (en) * | 2019-07-24 | 2019-11-15 | 浙江荷清柔性电子技术有限公司 | A kind of interconnection packaging method and interconnection package structure of chip |
| CN115295501A (en) * | 2022-08-22 | 2022-11-04 | 讯芯电子科技（中山）有限公司 | Embedded chip package and manufacturing method thereof |
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