CN102270585B - Circuit board structure, package structure and method for manufacturing circuit board - Google Patents
Circuit board structure, package structure and method for manufacturing circuit board Download PDFInfo
- Publication number
- CN102270585B CN102270585B CN201010190915.5A CN201010190915A CN102270585B CN 102270585 B CN102270585 B CN 102270585B CN 201010190915 A CN201010190915 A CN 201010190915A CN 102270585 B CN102270585 B CN 102270585B
- Authority
- CN
- China
- Prior art keywords
- conductive pattern
- pattern
- layer
- sealing
- release film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45565—Single coating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45599—Material
- H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45644—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention discloses a method for manufacturing a circuit board, and a circuit board structure and a package structure manufactured by the method. Firstly, a first substrate and a second substrate are provided, the first substrate comprises a carrier plate coated with a release film, and the second substrate comprises a copper foil coated with a solder resist layer; secondly, the release film and the patterned solder resist layer are laminated so that the first substrate is laminated to the second substrate; then, the copper foil is patterned to form a first pattern and a second pattern on the copper foil, the first pattern is in direct contact with the release film and the second pattern is in direct contact with the patterned solder resist layer; subsequently, a protective layer is formed to cover the first and the second patterns, so as to form a circuit board structure; and finally, a package is formed on the carrier plate to obtain a package structure. In the circuit board structure and package structure provided by the invention, since only the single-sided patterned solder resist layer is needed, the overall structure is more simple, which can simplify the manufacturing method.
Description
Technical field
The invention relates to a kind of method of circuit board, prepared board structure of circuit and encapsulating structure made.Special, the invention relates to a kind ofly by being fitted with the support plate of release film, to support to be coated with the Copper Foil of welding resisting layer, and then make the method for board structure of circuit and encapsulating structure.
Background technology
Circuit board is a kind of important element in electronic installation.Constantly pursue under the trend that size dwindles at electronic installation, develop multiple different carrier (carrier) structure that supports crystal grain, and stretch out and form suitable being electrically connected with other circuit that are positioned at circuit board surrounding with pin (pin).
With regard to current technology, the known board structure of circuit that has one to be called lead frame (lead frame).Fig. 1-4 are depicted as the method for making traditionally lead frame.Please refer to Fig. 1, first a metal substrate 101 is provided.Secondly, please refer to Fig. 2, will provide metal substrate 101 patternings, to form the circuit pattern 110 and crystal grain pad 111 of estimating corresponding crystal grain (not shown).Continue, form via (via hole) 122, pin 120 is connected on metal substrate 101 and by pin 120 and crystal grain pad 111 silver-plated 121.Come again, please refer to Fig. 3, crystal grain 130 is sticked to after on crystal grain pad 111, continue lead packages (wire bonding) and zinc-plated step.Then, please refer to Fig. 4, next will complete pin moulding, and obtain the encapsulating structure 102 of a crystal grain.The data of crystal grain sees through pin 120 to extraneous circuit communication.
But when the handled data quantity of crystal grain increases and when processing speed accelerates, the lead frame shown in above, but because crystal grain peripheral space is limited, and cannot increase more pin 120 accordingly with cooperation demand.Thus, just make the application of conventional wires frame encapsulating structure 102 be restricted.
Figure 5 shows that another supports the carrier structure 201 of crystal grain.In carrier structure 201, circuit pattern 220 lays respectively at the both sides of substrate 210.In addition, 230 of welding resisting layers are optionally positioned at the both sides of substrate 210, suitably protective circuit pattern 220.In addition, expose again the circuit pattern 220 of part.In this carrier structure 201, need to form in the both sides of substrate 210 independently welding resisting layer pattern 231/232.Welding resisting layer pattern 231/232 is conventionally different, could be to deal with the different demands of crystal grain pad (not shown) position and soldered ball (not shown) position.
After supporting the carrier structure 201 of crystal grain shown in Fig. 5 and carrying out encapsulation step, just can obtain the encapsulating structure 202 shown in the 6th figure.In the encapsulating structure 202 shown in the 6th figure, except the substrate 210 shown in the 5th figure, circuit pattern 220, welding resisting layer 230 and welding resisting layer pattern 231/232, also because encapsulation step has afterwards increased crystal grain pad 221, crystal grain 240, wire bonds 250, sealing 260 and soldered ball 270.
Due to above carrier structure, encapsulating structure and make traditionally method the imperfection of lead frame, still wish other novel board structure of circuit, encapsulating structure and preparation method thereof, can structurally more simplify, and can also break through restriction traditionally.
Summary of the invention
So the present invention proposes board structure of circuit, encapsulating structure of a kind of novelty and preparation method thereof.Board structure of circuit proposed by the invention and encapsulating structure, owing to only needing the patterned anti-soldering layer of one side, in overall structure because more simplify, so can make its manufacture method simplify in the lump simultaneously.In addition, board structure of circuit of the present invention and encapsulating structure, can also break through the restriction of pin number deficiency on traditional structure, is enough to coordinate increase and when processing speed accelerates, for the hsrdware requirements of pin number increase when the handled data quantity of crystal grain.
One aspect of the present invention proposes a kind of method of making circuit board.First substrate and second substrate are provided first, respectively.First substrate comprises the support plate that is fitted with release film, and second substrate comprises the Copper Foil that is coated with the first welding resisting layer.Secondly, one side patterning the first welding resisting layer.Come again, by release film and patterning the first welding resisting layer pressing, make first substrate conform to second substrate.Then, patterning Copper Foil, makes Copper Foil form the first pattern and the second pattern, and wherein the first pattern directly contacts release film, and direct contact patternsization the first welding resisting layer of the second pattern.Continue, form the first protective layer, cover respectively the first pattern and the second pattern, obtain a board structure of circuit.
In an embodiment of the present invention, the first pattern is crystal grain pad, and the second pattern is for being subject to the circuit pattern of patterned anti-soldering layer protection.In another embodiment of the present invention, can also form the second welding resisting layer, cover the second pattern with selectivity.In further embodiment of this invention, can also form the packaging body being positioned on support plate.In further embodiment of this invention, can continue to remove release film and support plate, and expose the first pattern and patterned anti-soldering layer, so the encapsulating structure of getting back.
Secondly the present invention proposes a kind of board structure of circuit.Board structure of circuit of the present invention, comprises support plate, release film, patterned anti-soldering layer, the first conductive pattern, the second conductive pattern and protective layer.Release film conforms on support plate.The welding resisting layer of one side patterning is positioned on release film and directly contacts release film.The first conductive pattern is positioned on release film, and directly contacts release film.The second conductive pattern is positioned on release film, the also direct contact patterns chemoprevention layer of contiguous the first conductive pattern.Protective layer covers respectively the first conductive pattern and the second conductive pattern.
The present invention also proposes another kind of board structure of circuit.Board structure of circuit of the present invention, comprises support plate, release film, patterned anti-soldering layer, the first conductive pattern, the second conductive pattern, covers welding resisting layer and protective layer.Release film conforms on support plate.The welding resisting layer of one side patterning is positioned on release film and directly contacts release film.The first conductive pattern is positioned on release film, and directly contacts release film.The second conductive pattern is positioned on release film, the also direct contact patterns chemoprevention layer of contiguous the first conductive pattern.Cover anti-welding series of strata selectivity and cover the second conductive pattern.Protective layer covers respectively the first conductive pattern and the second conductive pattern.
The present invention continues again to propose a kind of encapsulating structure.Encapsulating structure of the present invention, comprises sealing, one side patterned anti-soldering layer, the first conductive pattern, the second conductive pattern, the first protective layer, the second protective layer, crystal grain and wire bonds.Patterned anti-soldering layer is positioned on a surface of sealing.The first conductive pattern is positioned in the similar face of sealing.The second conductive pattern is arranged in sealing, contiguous the first conductive pattern direct contact patterns chemoprevention layer.The first protective layer is arranged in sealing completely, and covers respectively the first conductive pattern and the second conductive pattern.The second protective layer covers the first conductive pattern completely.Crystal grain is arranged on sealing and the first pattern completely.Wire bonds is also arranged in sealing completely, and is optionally electrically connected crystal grain and the first conductive pattern.
The present invention continues to propose a kind of encapsulating structure again.Encapsulating structure of the present invention, comprises sealing, one side patterned anti-soldering layer, the first conductive pattern, the second conductive pattern, covers welding resisting layer, the first protective layer, the second protective layer, crystal grain and wire bonds.Patterned anti-soldering layer is positioned on a surface of sealing.The first conductive pattern is positioned in the similar face of sealing.The second conductive pattern is arranged in sealing, contiguous the first conductive pattern direct contact patterns chemoprevention layer.Cover welding resisting layer and directly cover the second conductive pattern.The first protective layer is arranged in sealing completely, and covers the first conductive pattern.The second protective layer is positioned at outside sealing completely, and covers the first conductive pattern.Crystal grain is arranged on sealing and the first pattern completely.Wire bonds is also arranged in sealing completely, and is optionally electrically connected crystal grain and the first conductive pattern.
Brief description of the drawings
Fig. 1-4 are depicted as the method for making traditionally lead frame.
Figure 5 shows that the carrier structure that supports traditionally crystal grain.
Figure 6 shows that encapsulating structure traditionally.
The method that Fig. 7-10B is depicted as the present invention makes circuit board.
Figure 11 and Figure 11 A are depicted as board structure of circuit proposed by the invention.
Figure 12 and Figure 12 A are depicted as the present invention makes the continuity method of pre-package structure.
Figure 13 and Figure 13 A are depicted as the present invention makes the continuity method of another pre-package structure.
Figure 14 and Figure 14 A are depicted as encapsulating structure proposed by the invention.
Wherein, description of reference numerals is as follows:
101 metal substrate 307 encapsulating structures
102 encapsulating structure 310 first substrates
110 circuit pattern 311 support plates
111 crystal grain pad 312 release films
120 pin 320 second substrates
121 silver-plated 321 Copper Foils
130 crystal grain 322 welding resisting layers
201 carrier structure 322 patterned anti-soldering layer
210 substrate 323 first protective layers
220 circuit pattern 324 second protective layers
221 crystal grain pad 325 first patterns
230 welding resisting layer 325 first conductive patterns
231 welding resisting layer pattern 326 second patterns
232 welding resisting layer pattern 326 second conductive patterns
240 crystal grain 326 circuit patterns
250 wire bonds 327 cover welding resisting layer
260 sealing 328 crystal grain pads
270 soldered ball 330 packaging bodies
301 board structure of circuit 331 crystal grain
303 pre-package structure 332 wire bonds
305 pre-package structure 333 sealings
Embodiment
First aspect present invention proposes a kind of method the first embodiment that makes circuit board.The method that Fig. 7-11 are depicted as the present invention and make circuit board.Please refer to Fig. 7, first substrate 310 and second substrate 320 are provided first respectively.First substrate 310 can first separate making with second substrate 320, and is just pressed into when needed single substrate (not shown).In first substrate 310, include support plate 311, the one side on support plate 311 is fitted with release film 312.320 of second substrates include Copper Foil 321, and the thickness that it can have 10-70 μ m is preferably the thickness of 10-35 μ m.Copper Foil 321 only has one side to be coated with welding resisting layer 322.
Secondly, please refer to Fig. 8, before pressing first substrate 310 and second substrate 320, first patterned anti-soldering layer 322.Can use existing photoetching process or laser opening method ... etc., carry out patterned anti-soldering layer 322.Pattern on welding resisting layer 322 can be in advance through design, to coordinate the needs of subsequent technique.For example, only on the one side of welding resisting layer 322, carry out Patternized technique, and obtain the welding resisting layer 322 of one side patterning.
Then, please refer to Fig. 9, now release film 312 just can carry out pressing with the welding resisting layer 322 through patterning, makes first substrate 310 conform to second substrate 320.Because release film 312 can have plastic cohesive material for one, in an embodiment of the present invention, in the time that first substrate 310 conforms to second substrate 320, can make the welding resisting layer 322 of patterning embed in release film 312.Therefore, Copper Foil 321 can directly contact release film 312.In addition, because the adhesion strength between release film 312 and support plate 311 is stronger, so release film 312 and through the adhesion strength between the welding resisting layer 322 of patterning relatively a little less than.Now, outside the one side of Copper Foil 321 can be exposed to.
Next, please refer to Figure 10, in the first embodiment, due to outside the one side of Copper Foil 321 is still exposed to, for example, so when after patterning Copper Foil 321, will make Copper Foil 321 be formed with pattern, the first pattern 325, crystal grain pad 328 (die pad) and the second pattern 326.Can use for example dry film method or wet film method, carry out patterning Copper Foil 321.The first pattern 325 is different from the function of the second pattern 326.In an embodiment of the present invention, in the first pattern 325, can be electrical connection pad (connecting pad), the circuit pattern 326 that the second pattern 326 can be protected for being subject to patterned anti-soldering layer 322.In other words, the second pattern 326 can corresponding pattern chemoprevention layer 322.So as shown in figure 10, the first pattern 325 is direct contact patterns chemoprevention layer 322 of contact release film 312, the second patterns 326 directly.
In another kind of method the second embodiment that makes circuit board of the present invention, please refer to Figure 10 A, can also form and cover welding resisting layer 327, cover the first pattern 325, crystal grain pad 328 and the second pattern 326 completely.Cover the protective layer that welding resisting layer 327 can be used as the second pattern 326.Next, please refer to Figure 10 B, patterning covers welding resisting layer 327, exposes required element.For example, patterning covers welding resisting layer 327, exposes the first pattern 325 and crystal grain pad 328, and covers the second pattern 326.Cover the protective layer that welding resisting layer 327 can be used as the second pattern 326.
Continue, please refer to Figure 11, in order to protect fragile Copper Foil 321, need to form on the surface of Copper Foil 321 the first protective layer 323.Owing to having function different the first pattern 325 and the second pattern 326 separately on patterning Copper Foil 321, so the first protective layer 323 also can cover respectively the first pattern 325 and the second pattern 326.Can use electric plating method, form the first protective layer 323 on the surface of Copper Foil 321.The first protective layer 323 can be a kind of composite layer, for example the first protective layer 323 can comprise nickel, silver and gold wherein at least one, formation similarly is the protective layer of nickel/gold.
Or, please refer to Figure 11 A, in order to protect fragile Copper Foil 321, need to form on the surface of Copper Foil 321 the first protective layer 323.So the first protective layer 323 can cover the first pattern 325 and crystal grain pad 328.Can use electric plating method, form the first protective layer 323 on the surface of Copper Foil 321.The first protective layer 323 can be a kind of composite layer, for example the first protective layer 323 can comprise nickel, silver and gold wherein at least one, formation similarly is the protective layer of nickel/gold.
After above step, first substrate 310 and the second substrate 320 pressing together just forms a novel board structure of circuit 301.Please refer to Figure 11, be depicted as the first embodiment of board structure of circuit proposed by the invention 301.Figure 11 A is depicted as the second embodiment of board structure of circuit proposed by the invention 301.In board structure of circuit 301 of the present invention, comprise support plate 311, release film 312, patterned anti-soldering layer 322, the first conductive pattern 325, the second conductive pattern 326 and the first protective layer 323.Cover welding resisting layer 327 if board structure of circuit 301 also comprises in addition, as shown in Figure 11 A, be depicted as the second embodiment of board structure of circuit proposed by the invention 301.
As previously mentioned, release film 312 conforms on support plate 311, and adhesion strength is therebetween stronger.322 of patterned anti-soldering layer are positioned on release film 312, and directly contact release film 312.In an embodiment of the present invention, when the welding resisting layer 322 of the patterning in second substrate 320 conforms to the release film 312 in first substrate 310, preferably can embed in release film 312.The first conductive pattern 325 and the second conductive pattern 326 lay respectively on release film 312.The first conductive pattern 325 is contact release film 312 directly.On the other hand, 326 direct contact patterns chemoprevention layers 322 of the second conductive pattern.In other words, the second pattern 326 can corresponding pattern chemoprevention layer 322.Further, the first conductive pattern 325 and the second conductive pattern 326 are usually located adjacent one another, or staggered.The first 323 of protective layers cover respectively the first conductive pattern 325 and the second conductive pattern 326.The first protective layer 323 can comprise nickel, silver with gold wherein at least one, and formation similarly be the composite protection layer of nickel/gold.
In another embodiment of the present invention, the illustrated board structure of circuit 301 of Figure 11 can also be further through a pre-packaged step, and obtains a pre-package structure 303.Figure 12 shows that the present invention makes the first embodiment of the continuity method of pre-package structure.Figure 12 A is depicted as the present invention makes the second embodiment of the continuity method of pre-package structure, and board structure of circuit 301 also comprises in addition and covers welding resisting layer 327.Please refer to Figure 12 and Figure 12 A, the board structure of circuit 301 shown in Figure 11 and Figure 11 A can also further form a packaging body 330 on support plate 311.For example, first crystal grain 331 is bonded on the first pattern 325, that is on crystal grain pad 328.For example, can use the material (not shown) that elargol maybe can dispel the heat that crystal grain 331 is bonded on the first pattern 325.Then, use wire bonds 332, for example copper cash, silver-colored line, gold thread or gold-plated copper wires, depending on the circumstances or the needs of the situation selectivity is electrically connected crystal grain 331 with the first pattern 325 of part.After electrical connection completes, can use sealing 333, for example epoxy resin, seals crystal grain 331 and wire bonds 332, to stop the external world, the pollution of for example aqueous vapor.
As illustrated in Figure 12, sealing 333 except meeting seal crystal grain 331 and wire bonds 332 completely, sealing 333 also directly contact patterns chemoprevention layer 322 and release film 312 conventionally.In Figure 12 A, 333 of sealings can seal completely and cover welding resisting layer 327.Board structure of circuit 301 shown in Figure 11, further forming after a packaging body 330 on support plate 311, can obtain the pre-package structure 303 shown in Figure 12.
In further embodiment of this invention, the pre-package structure 303 shown in Figure 12 can further pass through again another step, and obtains another pre-package structure 305.Figure 13 illustrates the present invention makes the first embodiment of the continuity method of another pre-package structure.The present invention of Figure 13 A illustration makes the second embodiment of the continuity method of another pre-package structure, and board structure of circuit 301 also comprises covering welding resisting layer 327 in addition.Please refer to Figure 13 and Figure 13 A, after the support plate in the pre-package structure 303 shown in Figure 12 and Figure 12 A 311 and release film 312 are removed respectively, can obtain another pre-package structure 305.
Please note, because the adhesion strength between release film 312 and support plate 311 is stronger, release film 312 and through the adhesion strength between the welding resisting layer 322 of patterning relatively a little less than, so can remove very easily support plate 311 and release film 312 in pre-package structure 303, and not affect other parts in pre-package structure 305.Now, patterned anti-soldering layer 322 can optionally be positioned at 325, the first pattern.Encapsulating structure 305, after the support plate 311 and release film 312 that remove in pre-package structure 303, just can come out through welding resisting layer 322 and first pattern 325 of patterning.
In order to protect the fragile Copper Foil of the first pattern 325, in further embodiment of this invention, another pre-package structure 305 shown in Figure 13 can be more further through overprotection step, and obtains encapsulating structure 307.Figure 14 shows that the present invention makes the continuity method of encapsulating structure.Please refer to Figure 14, the pre-package structure 305 shown in Figure 13 can also further form the second protective layer 324 on the first pattern 325, covers the first pattern 325 completely.The second protective layer 324 can comprise wherein at least one (or using OSP (having organizational security weldering film)) of nickel, silver and gold, similarly is the composite protection layer of nickel/gold and form.
After above step, just can obtain a novel encapsulating structure 307.Please refer to Figure 14, be depicted as the first embodiment of encapsulating structure 307 provided by the present invention.Figure 14 A is depicted as the second embodiment of encapsulating structure 307 provided by the present invention, and board structure of circuit 301 also comprises covering welding resisting layer 327 in addition.In encapsulating structure 307 of the present invention, comprise patterned anti-soldering layer 322, the first conductive pattern 325, the second conductive pattern 326, the first protective layer 323, the second protective layer 324, crystal grain 331, wire bonds 332 and sealing 333.
In encapsulating structure proposed by the invention 307, as shown in figure 14, first can observe on the surface that patterned anti-soldering layer 322 is positioned at sealing 333.Patterned anti-soldering layer 322 part contact sealings 333 part come out.Sealing 333 is generally an encapsulant, for example epoxy resin.The first conductive pattern 325 is positioned in the similar face with the sealing 333 at patterned anti-soldering layer 322 places.The first conductive pattern 312 conventionally define for crystal grain 331 crystal grain pad 328.The second conductive pattern 326 is also arranged in sealing 333, and defines a circuit pattern.Further, the second conductive pattern 326 is understood direct contact patterns chemoprevention layer 322, and is subject to the protection of this patterned anti-soldering layer 322.In other words, the second pattern 326 can corresponding pattern chemoprevention layer 322.In addition, the second conductive pattern 326 is contiguous the first conductive pattern 312 also, and the while is direct contact patterns chemoprevention layer 322 again.In Figure 14 A, cover welding resisting layer 327 and directly cover the second conductive pattern 326.
On the one hand, the first protective layer 323 is arranged in sealing 333 completely, and covers respectively the first conductive pattern 325 and the second conductive pattern 326.On the other hand, the second 324 of protective layers are positioned at outside sealing 333 completely, and cover the first conductive pattern 312 completely.The first protective layer 323 and the second protective layer 324 can comprise independently respectively nickel, silver and gold wherein at least one, similarly be the composite protection layer (or OSP (have organizational security weld film)) of nickel/gold and form.Crystal grain 331 is positioned on the first conductive pattern 325, is optionally electrically connected with the first conductive pattern 325 of part again via wire bonds 332.Crystal grain 333 is arranged in sealing 333 simultaneously completely with wire bonds 332, and forms a packaging body.Other features of encapsulating structure 307 of the present invention, can with reference to aforementioned and no longer repeat.
The foregoing is only the preferred embodiments of the present invention, all equalizations of doing according to the claims in the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (15)
1. a method of making circuit board, is characterized in that, comprising:
First substrate and second substrate are provided respectively, and wherein this first substrate comprises the support plate that is fitted with release film, and this second substrate comprises the Copper Foil that is coated with the first welding resisting layer;
This first welding resisting layer of patterning;
By this release film and the first welding resisting layer pressing of this patterning, make this first substrate conform to this second substrate;
This Copper Foil of patterning, makes this Copper Foil form the first pattern, crystal grain pad and the second pattern, and wherein this first pattern directly contacts this release film, and this second pattern directly contacts this patterning the first welding resisting layer; And
Form the first protective layer, cover respectively this first pattern and this second pattern, to form circuit board.
2. the method for making circuit board as claimed in claim 1, is characterized in that, this second pattern is circuit pattern, and is subject to the protection of this patterning the first welding resisting layer.
3. the method for making circuit board as claimed in claim 1, is characterized in that, this second pattern is to should patterning the first welding resisting layer.
4. the method for making circuit board as claimed in claim 2, is characterized in that, more comprises:
Form the second welding resisting layer, cover this second pattern with selectivity.
5. the method for making circuit board as claimed in claim 1, is characterized in that, more comprises:
Formation is positioned at the packaging body on this support plate.
6. the method for making circuit board as claimed in claim 5, is characterized in that, this packaging body comprises:
Crystal grain, is positioned on this crystal grain pad;
Wire bonds, selectivity is electrically connected this crystal grain and this first pattern; And
Sealing, seals this crystal grain with this wire bonds and directly contacts this patterning the first welding resisting layer and this release film.
7. the method for making circuit board as claimed in claim 5, is characterized in that, more comprises:
Remove this release film and this support plate, to expose this first pattern and this patterning the first welding resisting layer simultaneously.
8. a board structure of circuit, is characterized in that, comprising:
Support plate;
Release film, conforms to this support plate;
Patterned anti-soldering layer, is positioned on this release film and completely directly contacts this release film;
Patterned conductive layer, comprise the first conductive pattern and the second conductive pattern, wherein this first conductive pattern is positioned on this release film and direct this release film of contact, and this second conductive pattern is positioned on this release film, contiguous this first conductive pattern also directly contacts this patterned anti-soldering layer; And
Protective layer, covers respectively this first conductive pattern and this second conductive pattern.
9. a board structure of circuit, is characterized in that, comprising:
Support plate;
Release film, conforms to this support plate;
Patterned anti-soldering layer, is positioned on this release film and completely directly contacts this release film;
Patterned conductive layer, comprise the first conductive pattern and the second conductive pattern, wherein this first conductive pattern is positioned on this release film and direct this release film of contact, and this second conductive pattern is positioned on this release film, contiguous this first conductive pattern also directly contacts this patterned anti-soldering layer;
Cover welding resisting layer, cover this second conductive pattern with selectivity; And
Protective layer, covers respectively this first conductive pattern and this second conductive pattern.
10. an encapsulating structure, is characterized in that, comprising:
Sealing;
Patterned anti-soldering layer, is positioned on the surface of this sealing;
Patterned conductive layer, comprises the first conductive pattern and the second conductive pattern, and wherein this first conductive pattern is positioned on this surface of this sealing, and this second conductive pattern is arranged in this sealing and contiguous this first conductive pattern and directly contacts this patterned anti-soldering layer;
Crystal grain pad, is arranged in this sealing;
The first protective layer, is arranged in this sealing completely and covers respectively this first conductive pattern and this second conductive pattern;
The second protective layer, covers this first conductive pattern completely;
Crystal grain, is arranged on this sealing and this crystal grain pad completely; And
Wire bonds, is arranged in this sealing selectivity completely and is electrically connected this crystal grain and this first conductive pattern.
11. encapsulating structures as claimed in claim 10, is characterized in that, this patterned anti-soldering layer part contacts this sealing and part comes out.
12. encapsulating structures as claimed in claim 10, is characterized in that, this second conductive pattern is a circuit pattern, and is subject to the protection of this patterned anti-soldering layer.
13. 1 kinds of encapsulating structures, is characterized in that, comprising:
Sealing;
Patterned anti-soldering layer, is positioned on the surface of this sealing;
Patterned conductive layer, comprises the first conductive pattern and the second conductive pattern, and wherein this first conductive pattern is positioned on this surface of this sealing, and this second conductive pattern is arranged in this sealing and contiguous this first conductive pattern and directly contacts this patterned anti-soldering layer;
Crystal grain pad, is arranged in this sealing;
Cover welding resisting layer, directly cover this second conductive pattern;
The first protective layer, is arranged in this sealing completely and covers this first conductive pattern;
The second protective layer, is positioned at outside this sealing completely and covers this first conductive pattern;
Crystal grain, is arranged on this sealing and this crystal grain pad completely; And
Wire bonds, is arranged in this sealing selectivity completely and is electrically connected this crystal grain and this first conductive pattern.
14. encapsulating structures as claimed in claim 13, is characterized in that, this patterned anti-soldering layer part contacts this sealing and part comes out.
15. encapsulating structures as claimed in claim 13, is characterized in that, this second conductive pattern is a circuit pattern, and is subject to the protection of this patterned anti-soldering layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201010190915.5A CN102270585B (en) | 2010-06-02 | 2010-06-02 | Circuit board structure, package structure and method for manufacturing circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201010190915.5A CN102270585B (en) | 2010-06-02 | 2010-06-02 | Circuit board structure, package structure and method for manufacturing circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102270585A CN102270585A (en) | 2011-12-07 |
CN102270585B true CN102270585B (en) | 2014-06-25 |
Family
ID=45052829
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201010190915.5A Expired - Fee Related CN102270585B (en) | 2010-06-02 | 2010-06-02 | Circuit board structure, package structure and method for manufacturing circuit board |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN102270585B (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103632979B (en) * | 2012-08-27 | 2017-04-19 | 碁鼎科技秦皇岛有限公司 | Chip packaging substrate and structure, and manufacturing methods thereof |
CN103857202B (en) * | 2012-12-07 | 2017-02-08 | 北大方正集团有限公司 | PCB and manufacturing method for copper pillar of printed circuit board |
CN106339116B (en) * | 2015-07-11 | 2023-07-14 | 宸新科技(厦门)有限公司 | Touch panel and manufacturing method thereof |
CN107180843B (en) * | 2017-05-17 | 2020-02-18 | 京东方科技集团股份有限公司 | Packaging panel, device packaging structure and preparation method thereof |
TWI711133B (en) * | 2019-07-26 | 2020-11-21 | 大陸商上海兆芯集成電路有限公司 | Electronic structure and manufacturing method thereof |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2794960B2 (en) * | 1991-02-19 | 1998-09-10 | 松下電器産業株式会社 | Sintered conductor wiring board and its manufacturing method |
US5480503A (en) * | 1993-12-30 | 1996-01-02 | International Business Machines Corporation | Process for producing circuitized layers and multilayer ceramic sub-laminates and composites thereof |
DE102004058879B4 (en) * | 2004-12-06 | 2013-11-07 | Austriamicrosystems Ag | MEMS microphone and method of manufacture |
KR100736636B1 (en) * | 2006-06-16 | 2007-07-06 | 삼성전기주식회사 | Pcb for electro component package and method of manufacturing thereof |
KR100850213B1 (en) * | 2007-05-22 | 2008-08-04 | 삼성전자주식회사 | Semiconductor package having molded balls and method of fabricating the same |
KR100930965B1 (en) * | 2008-01-17 | 2009-12-10 | (주)아큐텍반도체기술 | Method of manufacturing substrate for semiconductor package and metal plating layer manufactured using same |
CN101299413B (en) * | 2008-06-20 | 2011-03-09 | 日月光半导体制造股份有限公司 | Process for manufacturing circuit board |
-
2010
- 2010-06-02 CN CN201010190915.5A patent/CN102270585B/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN102270585A (en) | 2011-12-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103579128B (en) | Chip package base plate, chip-packaging structure and preparation method thereof | |
CN103681365B (en) | Package-on-package structure and preparation method thereof | |
CN100514616C (en) | Internally burying type chip packaging manufacture process and circuit board having the same | |
CN102270585B (en) | Circuit board structure, package structure and method for manufacturing circuit board | |
US8987060B2 (en) | Method for making circuit board | |
CN104299919B (en) | Coreless package structure and method for manufacturing the same | |
CN105489565A (en) | Package structure of embedded device and method for fabricating the same | |
JP4945682B2 (en) | Semiconductor memory device and manufacturing method thereof | |
CN103281858A (en) | Printed circuit board and manufacturing method thereof, and flip-chip packaging member and manufacturing method thereof | |
CN102270584A (en) | Circuit board structure, packaging structure and method for manufacturing circuit board | |
CN104517929A (en) | Package carrier | |
CN202940236U (en) | Package substrate structure | |
CN104576402A (en) | Packaging substrate and manufacturing method thereof | |
CN102751203A (en) | Semiconductor encapsulation structure and manufacture method of semiconductor encapsulation structure | |
CN104769712A (en) | Semiconductor device including embedded controller die and method of making same | |
CN103107145A (en) | Semiconductor package, prefabricated lead frame and manufacturing method thereof | |
KR101148954B1 (en) | Circuit board structure, packaging structure and method for making the same | |
CN101740410B (en) | Manufacturing process for a chip package structure | |
CN103325697B (en) | Manufacturing method of semiconductor packaging structure | |
CN102130085A (en) | Semiconductor package with electrical connection structure and manufacturing method thereof | |
JP2012146765A (en) | Semiconductor device and method of manufacturing semiconductor device | |
CN101316479B (en) | Circuit board and production method thereof | |
KR100604327B1 (en) | Multi-layer TBGA semiconductor package and method therefor | |
CN101661928A (en) | Chip package | |
JP2009302427A5 (en) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140625 Termination date: 20200602 |
|
CF01 | Termination of patent right due to non-payment of annual fee |