CN102270584A - A circuit board structure, the package structure and production of the circuit board - Google Patents

A circuit board structure, the package structure and production of the circuit board Download PDF

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CN102270584A
CN102270584A CN 201010190900 CN201010190900A CN102270584A CN 102270584 A CN102270584 A CN 102270584A CN 201010190900 CN201010190900 CN 201010190900 CN 201010190900 A CN201010190900 A CN 201010190900A CN 102270584 A CN102270584 A CN 102270584A
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CN 201010190900
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颜立盛
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联致科技股份有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139Silver (Ag) as principal constituent
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45565Single coating layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45599Material
    • H01L2224/456Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45644Gold (Au) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

本发明公开了一种电路板结构、封装结构与制作电路板的方法。 The present invention discloses a method of circuit board structure, the package structure and production of the circuit board. 其中该方法包括:首先,提供一基板,其包括一载板、一铜箔与位于载板与铜箔间的一离型膜。 Wherein the method comprises: providing a substrate comprising a release film between a carrier plate, a copper plate and a copper foil with carrier is located. 其次,图案化铜箔,使得铜箔形成一接点图案与一晶粒垫板。 Secondly, the patterned copper foil, a copper foil so that a contact pattern is formed with a die plate. 然后,形成一第一保护层,分别覆盖接点图案与晶粒垫板,以形成一电路板。 Then, a first protective layer is formed, and cover the die pad contact pattern to form a circuit board.

Description

电路板结构、封装结构与制作电路板的方法 A circuit board structure, the package structure and production of the circuit board

技术领域 FIELD

[0001] 本发明是关于一种制作电路板的方法、所制得的电路板结构与封装结构。 [0001] The present invention relates to a method of making a circuit board, the obtained circuit board structure and the package structure. 特别来说,本发明是关于一种通过贴合有离型膜的载板与铜箔,进而制得电路板结构与封装结构的方法。 In particular, the present invention relates to a bonded through there from the carrier film and the copper foil, and thus a circuit board made of a configuration of the package structure obtained.

背景技术 Background technique

[0002] 电路板是电子装置中一种重要的元件。 [0002] electronic device circuit board is an important element. 在电子装置不断追求尺寸缩小的趋势下, 发展出多种不同支撑晶粒的载具(carrier)结构,并以接脚(pin)向外延伸与位于电路板四周的其他电路形成适当的电连接。 In the electronic apparatus continue to pursue downsizing trend, development of a variety of different die support carrier (Carrier) structure, and to pins (pin) extending outwardly form an appropriate electrical connection with other circuit connected to the circuit board around the .

[0003] 就目前的技术而言,已知有一种称为导线架(lead frame)的电路板结构。 [0003] The current technology, it is known a circuit board structure called lead frame (lead frame) of. 图1_4 所示为传统上制作导线架的方法。 The method shown in FIG. 1_4 leadframe is prepared traditionally. 请参考图1,首先提供一金属基板101。 Please refer to FIG. 1, a metal substrate 101 is first provided. 其次,请参考图2,将金属基板101图案化,以形成预计对应芯片(图未示)的电路图案110,与晶粒垫111。 Next, referring to FIG 2, the metal substrate 101 is patterned to form the corresponding expected chip (not shown) of the circuit pattern 110, and the die pad 111. 接着,形成导通孔(via hole) 122、将接脚120连接至金属基板101上、并将接脚120与晶粒垫111镀银121。 Next, a via hole (via hole) 122, the pin 120 is connected to the metal substrate 101, and the die pad 120 and the pin 111 121 silver. 再来,请参考图3,将晶粒130黏至晶粒垫111上后,继续引线封装(wire bonding)与镀锡步骤。 Again, please refer to FIG. 3, the grains stick to the die pad 130 after 111 continues lead package (wire bonding) and tin plating step. 然后,请参考图4,接下来完成接脚成型,而得到一个芯片的封装结构102。 Then, referring to FIG 4, next to complete the forming pin, to give a chip package structure 102. 芯片的资料即透过接脚120向外界的电路连络。 That chip information circuit 120 contact to the outside world through the pin.

[0004] 然而,当芯片所处理的资料量增大及处理速度变快时,以上所示的导线架,却因为芯片周边空间有限,而无法对应地增加更多的接脚120以配合需求。 [0004] However, when the amount of data processed is increased and chip processing speed is increased, the lead frame shown above, but because of the limited space around the chip, can not be increased correspondingly more pins 120 to fit the needs. 如此一来,便使得传统导线架封装结构102的应用受到限制。 Thus, the conventional lead frame so that the application package 102 is limited.

[0005] 图5所示为另外一种支撑芯片的载具结构201。 [0005] Figure 5 shows another chip carrier support structure 201. 在载具结构201中,电路图案220 分别位于基板210的两侧。 In the carrier structure 201, the circuit pattern 220 are located on both sides of the substrate 210. 另外,防焊层230则选择性地位于基板210的两侧,适当地保护电路图案220。 Further, the solder resist layer 230 is selectively positioned on both sides of the substrate 210, 220 suitably protect the circuit patterns. 除此以外,又暴露出部份的电路图案220。 In addition, another part of the circuit pattern 220 is exposed. 在此载具结构201中,需要在基板210的两侧形成独立的防焊层图案231/232。 The carrier structure 201, a separate solder resist layer pattern to be formed on both sides of the substrate 231/232 210. 防焊层图案231/232通常各不相同,才能以应付晶粒垫(图未示)位置与焊球(图未示)位置的不同需求。 231/232 solder resist layer pattern is typically varied in order to cope with the die pad (not shown) and the position of the solder ball (not shown) the position of the different needs.

[0006] 当图5所示支撑芯片的载具结构201在进行过封装步骤后,就可以得到图6所示的封装结构202。 [0006] When the supporting structure of the chip carrier shown in Figure 5 step 201 is performed through the package, the package structure can be obtained as shown in 6202 in FIG. 在图6所示的封装结构202中,除了图5所示的基板210、电路图案220、 防焊层230与防焊层图案231/232,还因为后来的封装步骤增加了晶粒垫221、晶粒M0、接合导线250、膜封材料(encapsulant)260与焊球270。 In the packaging structure 202 shown in Figure 6, except that the substrate 210 shown in FIG. 5, the circuit pattern 220, the solder resist pattern layer 230 and the solder resist layer 231/232, but also because subsequent packaging steps increases die pad 221, grain M0, the bonding wire 250, the membrane sealing material (encapsulant) 260 and the ball 270.

[0007] 晶粒240位于电路图案220中的晶粒垫221上,还同时被防焊层图案231所围绕, 并以接合导线250与电路图案220的其他部份电连接。 [0007] The die 240 of the circuit patterns 220 of the die pad 221, while also being surrounded by the solder resist layer pattern 231, and the bonding wire 250 connected to the other parts of the circuit patterns 220 electrically. 膜封材料沈0即完全包覆晶粒垫221、晶粒对0、接合导线250,与覆盖部份的基板210与防焊层230。 0 i.e. membrane sealing material completely coated grains sink pads 221, dies to 0, bonding wires 250, the cover portion 210 of the substrate 230 and the solder resist layer. 焊球270则被防焊层图案232所围绕。 Solder ball 270 solder resist pattern 232 were surrounded. 在图5所示的载具结构201与图6所示的封装结构202中都可以观察到, 位在基板210两侧独立的防焊层图案231/232,并且延伸至基板210的侧边。 Carrier 201 to the configuration shown in FIG. 5 package structure 202 shown in Figure 6 can be observed with a separate bit in the solder resist layer pattern on both sides of the substrate 210 231/232, and extends to a substrate 210 side.

[0008] 由于以上的载具结构、封装结构与传统上制作导线架的方法并不完善,因此仍然希望有其他新颖的电路板结构、封装结构及其制作方法,能够在结构上更加简化,并且还能突破传统上的限制。 [0008] Since the method of manufacturing the lead frame is not perfect carrier structure on the above, the conventional package structure, therefore still desirable to have other novel circuit board structure, package structure and a manufacturing method can be more simplified in structure, and It can break through the traditional limitations. 发明内容 SUMMARY

[0009] 本发明于是提出一种新颖的电路板结构、封装结构及其制作方法。 [0009] Accordingly the present invention provides a novel circuit board structure, package structure and fabrication method. 本发明所提出的电路板结构与封装结构,可以使用面积数组(area array)的方式设计,在整体结构上可以增加设计空间,所以可以使得封装体积变小。 Circuit board structure and the package structure proposed in the present invention, may be used an area array (area array) designed in a way, the overall structure of the design space can be increased, so that the package size can be reduced. 除此以外,本发明的离型膜(release film),还方便载板与铜箔的分离。 In addition, the release film (release film) of the present invention, the carrier also facilitate the separation plate and the copper foil.

[0010] 本发明提出一种制作电路板的方法。 [0010] The present invention provides a method of making a circuit board. 首先,提供一基板,其包括一载板、一铜箔与位于载板与铜箔间的一离型膜。 First, a substrate is provided which includes a carrier, a copper foil with a carrier board at the copper foil from the film. 其次,图案化铜箔,使得铜箔形成一接点图案与一晶粒垫。 Secondly, the patterned copper foil, a copper foil is formed such that a contact pattern and a die pad. 然后,形成一第一保护层,分别覆盖接点图案与晶粒垫,以形成一电路板。 Then, a first protective layer are formed, respectively covering the die pad and contact pattern to form a circuit board.

[0011] 在本发明一实施例中,可以先将离型膜涂布至铜箔后,再将具有铜箔的离型膜贴合至载板上,以形成基板。 [0011] In an embodiment of the present invention may be a copper foil to the first, then the release film having a release film coating a copper foil bonded to the carrier plate to form the substrate. 在本发明另一实施例中,则可以先将离型膜涂布至载板后,再将具有载板的离型膜贴合至铜箔,以形成基板。 Embodiment, it is possible to first rear carrier, then the carrier sheet having the release film is bonded to a copper foil coated with a release film In another embodiment of the present invention, to form the substrate. 在本发明又一实施例中,还可以形成位于载板上的封装体。 In yet another embodiment of the present invention may also be formed in the carrier plate located on the package. 在本发明再一实施例中,则可以继续移除离型膜与载板,而暴露出接点图案与与晶粒垫,于是又得到一封装结构。 In another embodiment of the present invention, it is possible to continue to remove the release film and the carrier, and to expose the contact pattern with the die pad, and thus obtain a package.

[0012] 本发明其次提出一种电路板结构。 [0012] Secondly, the present invention provides a circuit board structure. 本发明的电路板结构,包括载板、离型膜、接点图案、晶粒垫与保护层。 A circuit board structure of the present invention, comprises a carrier board, a release film, a contact pattern, die pad and the protective layer. 离型膜贴合至载板上,接点图案则位于离型膜上并直接接触离型膜。 Release film bonded to the carrier plate, the contact pattern positioned in direct contact with a release film and a release film. 晶粒垫位于离型膜上,亦直接接触离型膜。 Release film die pad is located is also in direct contact with a release film. 保护层分别覆盖接点图案与晶粒垫。 The protective layer covers the contact pattern with each die pad.

[0013] 本发明又提出一种封装结构。 [0013] The present invention further provides a package structure. 本发明的封装结构,包括载板、离型膜、膜封材料、接点图案、晶粒垫、保护层、晶粒与接合导线。 The package structure according to the present invention, comprising a carrier plate, from the film, sealing film materials, contact pattern, die pad, the protective layer, and the bonding wire die. 离型膜贴合至载板上,膜封材料则覆盖离型膜。 Release film bonded to the carrier plate, the membrane sealing material is covered with a release film. 接点图案与晶粒垫则一齐位于膜封材料中。 The die pad contact pattern together with the sealing material is located in the membrane. 保护层完全位于膜封材料中且覆盖接点图案与晶粒垫。 The protective layer is positioned entirely in the membrane sealing material and covers the contact pattern with the die pad. 晶粒也完全位于膜封材料中并位于晶粒垫上。 Grains also located entirely film material and sealing die pad is located. 接合导线完全位于膜封材料中并选择性电连接晶粒与接点图案。 Bonding wire located entirely in the membrane sealing material, and selectively electrically connected to the die contact pattern.

[0014] 本发明另提出一种封装结构。 [0014] The present invention further provides a package structure. 本发明的封装结构,包括膜封材料、接点图案、晶粒垫、保护层、晶粒与接合导线。 The package structure according to the present invention, comprises a membrane sealing material, contact pattern, die pad, the protective layer, and the bonding wire die. 接点图案与晶粒垫都位于膜封材料中。 And a contact pattern are located die pad membrane sealing material. 保护层完全位于膜封材料中,且覆盖接点图案与晶粒垫。 The protective layer is positioned entirely in the membrane sealing material, and covers the contact pattern with the die pad. 晶粒完全位于膜封材料中与位于晶粒垫上。 Sealing the film grain material located entirely die pad located. 接合导线也完全位于膜封材料中,并选择性电连接晶粒与接点图案。 Bonding wires also located entirely in the membrane sealing material, and selectively electrically connected to the die contact pattern.

[0015] 本发明再提出一种封装结构。 [0015] The present invention further provides a package structure. 本发明的封装结构,包括膜封材料、接点图案、晶粒垫、第一保护层、第二保护层、晶粒与接合导线。 The package structure according to the present invention, comprises a membrane sealing material, contact pattern, die pad, a first protective layer, a second protective layer, and the die bonding wire. 接点图案与晶粒垫都位于膜封材料中。 And a contact pattern are located die pad membrane sealing material. 第一保护层完全位于膜封材料中,且覆盖接点图案与晶粒垫。 A first protective layer is positioned entirely in the membrane sealing material, and covers the contact pattern with the die pad. 第二保护层则位于膜封材料外, 而覆盖接点图案与晶粒垫。 The second protective layer is located on the outer membrane sealing material, to cover the contact pattern with the die pad. 晶粒完全位于膜封材料中与位于晶粒垫上。 Sealing the film grain material located entirely die pad located. 接合导线亦完全位于膜封材料中,并选择性电连接晶粒与接点图案。 Also bonding wire located entirely in the membrane sealing material, and selectively electrically connected to the die contact pattern.

附图说明 BRIEF DESCRIPTION

[0016] 图1-4所示为传统上制作导线架的方法。 A method for the production of the conventional lead frame [0016] Figure 1-4.

[0017] 图5所示为另外一种支撑晶片的载具结构。 [0017] Figure 5 shows another structure for supporting a wafer carrier.

[0018] 图6所示为传统上的封装结构。 [0018] FIG. 6 shows a conventional packaging structure.

[0019] 图7-8所示为本发明制作电路板的方法。 [0019] FIG method of manufacturing a circuit board 7-8 of the present invention.

[0020] 图9所示为本发明所提出的电路板结构。 [0020] Figure 9 shows the proposed structure of the circuit board of the present invention.

[0021] 图10所示为本发明制作预封装结构的延续方法。 [0021] FIG. 10 shows the continuation of the present method of making a pre-packaged structure of the present invention. [0022] 图11所示为本发明制作另 t一预封装结构的延续方法。 [0022] As shown in FIG. 11 the present invention further production method of a prepackaged t continuation structure. [0023] 图12所示为本发明制作封装结构的延续方法。 [0023] As shown in the continuation of the method of making a packaging structure 12 of the present invention, FIG. [0024] 其中,附图标记说明如下: [0025] 301 电路板结构 332 晶粒垫[0026] 303 预封装结构 333 第一保护层[0027] 305 预封装结构 340 封装体[0028] 307 封装结构 341 晶粒[0029] 309 基板 342 接合导线[0030] 310 载板 305 预封装结构[0031] 320 离型膜 343 膜封材料[0032] 330 铜箔 344 第二保护层[0033] 331 接点图案 [0024] wherein reference numerals as follows: [0025] 301 332 die pad of the circuit board structure [0026] Structure 333 303 prepackaged first protective layer [0027] 305 prepackaged package structure 340 [0028] 307 package 341 die [0029] 309 substrate 342 bonding wire [0030] 305 pre-package carrier 310 [0031] 343 film 320 from the film sealing material [0032] The second protective layer 330 of the copper foil 344 [0033] 331 contact pattern

具体实施方式 detailed description

[0034] 本发明第一方面提出一种制作电路板的方法。 [0034] The first aspect of the present invention provides a method for making a circuit board. 图7-8所示为本发明制作电路板的方法。 As shown in FIG. 7-8 method of manufacturing a circuit board of the present invention. 请参考图7,首先提供基板309,其包括载板310、离型膜320与铜箔330。 Please refer to FIG. 7, a substrate 309 is first provided, which includes a carrier plate 310, the release film 320 and the copper foil 330. 离型膜320 位于载板310与铜箔330之间。 The release film 320 is positioned between the carrier plate 310 and the copper foil 330. 载板310可以为任何材料,例如聚对苯二甲酸乙二酯(PET)、 聚碳酸酯(PC)、聚甲基丙烯酸甲酯(PMMA)与无铜基板等等。 Carrier 310 may be of any material, such as polyethylene terephthalate (PET), polycarbonate (PC), polymethyl methacrylate (PMMA) and the like without a copper substrate. 离型膜320可以为一种具有可塑性的粘性材料,并与载板310间产生较强的粘着力。 The release film 320 may have a plasticity as a viscous material, and produce a strong adhesion between the carrier plate 310. 因此离型膜320即藉此粘着力贴合在载板310的一面上。 Thus i.e. whereby the release film 320 is bonded to the carrier adhesion on one side of the plate 310. 基板309可以具有150〜400 μ m的厚度,优选为265 μ m的厚度。 The substrate 309 may have a thickness of 150~400 μ m, preferably a thickness of 265 μ m.

[0035] 基板309中的载板310、离型膜320与铜箔330,可以视情况需要有不同的加工步骤。 [0035] The substrate 309 in carrier 310, release film 320 and the copper foil 330, as the case may require different processing steps. 例如,请参考图7A,在本发明一实施例中,可以先将离型膜320涂布至铜箔330,例如使用网印法与滚轮法其中至少一种,接着再利用离型膜320的粘着力将具有铜箔330的离型膜320贴合至载板310上,以形成基板309。 For example, referring to FIG. 7A, an embodiment of the present invention may be applied first from the film 320 to foil 330, for example, screen printing method and wherein at least one of the rollers, followed by a release film 320 using the adhesion of the release film 320 having a copper foil 330 is bonded onto the carrier plate 310, 309 to form the substrate. 在本发明另一实施例中,请参考图7B,则可以先将离型膜320涂布至载板310后,例如使用网印法与滚轮法其中至少一种,接着再利用离型膜320的粘着力将具有载板310的离型膜320贴合至铜箔330,以形成基板309。 In another embodiment of the present invention, please refer to Figure 7B, the first release film 320 may be applied to the carrier plate 310 after, for example, screen printing method and wherein at least one of the rollers, followed by a release film 320 using adhesion carrier plate having a release film 320 copper foil 310 is bonded to 330, 309 to form the substrate. 无论使用何种方法,最后都会使得离型膜320位于载板310与铜箔330之间。 Whichever method is used, so that the release film will last 320 310 and the copper foil 330 is positioned between the carrier plate.

[0036] 其次,请参考图8,由于铜箔330的一面仍然暴露在外,所以当铜箔330在图案化后,就会使得铜箔330形成有图案,例如接点图案331与晶粒垫(di印ad)332。 [0036] Next, referring to FIG 8, since one side of the copper foil 330 is still exposed, so that when the copper foil 330 after the patterning of the copper foil 330 is formed such that it will have a pattern, such as contact pattern 331 and die pad (DI print ad) 332. 可以使用例如干膜法或是湿膜法,来图案化铜箔330。 May be used, for example, a dry film method or a wet film forming method, the copper foil 330 is patterned. 接点图案331与晶粒垫332的功能不同。 The contact pad patterns 331 and 332 grains of different functions. 例如, 晶粒垫332用来承载一预定的晶粒(图未示)。 For example, a die pad 332 for carrying a predetermined die (not shown). 接点图案331则可以为晶粒(图未示)的电连接垫(connecting pad)。 331 that can electrically contact pattern die (not shown) of the connection pads (connecting pad).

[0037] 继续,请参考图9,为了保护脆弱的铜箔330,需要在铜箔330的表面形成第一保护层333。 [0037] Continue, please refer to FIG. 9, in order to protect the fragile foil 330, a first protective layer 333 is formed on the surface of the copper foil 330 need of. 由于图案化铜箔330上会有功能各自不同的接点图案331与晶粒垫332,所以第一保护层333也会分别覆盖接点图案331与晶粒垫332。 Since there will be features on the patterned copper foil 330 of different respective die pads 331 and the contact pattern 332, the first protective layer 333 will cover the contact pattern 331 and the die pad 332. 可以使用电镀的方法,在铜箔330的表面形成第一保护层333。 Plating method can be used, forming a first protective layer 333 on the surface of the copper foil 330. 第一保护层333可以是一种复合材料层,例如第一保护层333会包括镍、银与金其中至少一种,形成像是镍/金的保护层。 A first protective layer 333 may be a composite layer, such as a first protective layer 333 may include nickel, wherein at least one of silver and gold, such as a protective layer is formed of nickel / gold.

[0038] 经过以上步骤后,压合在一起的载板310、离型膜320与铜箔330就会形成一个新颖的电路板结构301。 [0038] Through the above steps, the pressing together of the carrier plate 310, the release film 320 and the copper foil 330 will form a new circuit board structure 301. 请参考图9,所示为本发明所提出的电路板结构301。 Please refer to FIG. 9, the circuit board of the proposed structure 301 shown in the present invention. 在本发明的电路板结构301中,包括载板310、离型膜320、接点图案331、晶粒垫332与第一保护层333。 A circuit board structure 301 of the present invention, comprising a carrier plate 310, the release film 320, contact pattern 331, die pad 332 and the first protective layer 333. 离型膜320贴合至载板上310,接点图案331与晶粒垫332则分别位于离型膜320上,并直接接触离型膜320。 The release film 320 is bonded to a carrier plate 310, and die pads 331 contact pattern 332 located on the releasing film 320, and in direct contact with a release film 320. 第一保护层333分别覆盖接点图案331与晶粒垫332。 A first protective layer 333 respectively cover the contact pad pattern 331 and die 332.

[0039] 载板310可以为任何材料,例如聚对苯二甲酸乙二酯(PET)、聚碳酸酯(PC)、聚甲基丙烯酸甲酯(PMMA)与无铜基板等等。 [0039] The carrier 310 may be of any material, such as polyethylene terephthalate (PET), polycarbonate (PC), polymethyl methacrylate (PMMA) and the like without a copper substrate. 离型膜320可以为一种具有可塑性的粘性材料,并与载板310间产生较强的粘着力。 The release film 320 may have a plasticity as a viscous material, and produce a strong adhesion between the carrier plate 310. 因此离型膜320即藉此粘着力贴合在载板310的一面上。 Thus i.e. whereby the release film 320 is bonded to the carrier adhesion on one side of the plate 310. 第一保护层333可以是一种复合材料层,例如第一保护层333会包括镍、银与金其中至少一种,形成像是镍/金的保护层。 A first protective layer 333 may be a composite layer, such as a first protective layer 333 may include nickel, wherein at least one of silver and gold, such as a protective layer is formed of nickel / gold.

[0040] 在本发明另一实施例中,图9所示的电路板结构301还可以进一步经过一预封装步骤,而得到一预封装结构303。 Embodiment, the circuit board arrangement 301 shown in FIG. 9 may further step through a pre-packaged, pre-packaged to obtain a structure 303 [0040] In another embodiment of the present invention. 图10所示为本发明制作预封装结构的延续方法。 The method of making a continuation of FIG. 10 structure prepackaged present invention is shown. 请参考图10,图9所示的电路板结构301还可以进一步在离型膜320上形成一封装体340。 Please refer to FIG. 10, a circuit board structure 301 shown in FIG. 9, a package body 340 may also be further formed on the release film 320. 例如,先将晶粒341黏在晶粒垫332上。 For example, a dice die pad 341 stuck on 332. 举例而言,可以使用银胶334或可散热的物质(图未示), 将晶粒341黏在晶粒垫332上。 For example, silver paste may be used or a heat dissipation material 334 (not shown), the die pad 341 on the die 332 in sticky. 然后,使用接合导线342,例如铜线、银线、金线或镀金铜线等等,视情况需要选择性将晶粒341与部份的接点图案331进行电连接。 Then, using the bonding wire 342, for example, copper, silver, gold or gold-plated copper, etc., as necessary to selectively die part 341 with the contact pattern 331 is connected electrically. 在电连接完成后, 即可以使用膜封材料343,例如环氧树脂,将晶粒341与接合导线342密封,以杜绝外界,例如水气的污染。 After the electrical connection is completed, i.e., the membrane sealing material 343 may be used, such as epoxy resin, the die bonding wire 341 and the seal 342 to prevent the outside world, such as pollution of water vapor.

[0041 ] 图9所示的电路板结构301进一步在离型膜320上形成一封装体340后,即可得到图10所示的预封装结构303。 After the circuit board structure 301 is further shown a package body 340 formed on a release film 320 [0041] FIG. 9, to obtain a pre-packaged structure 303 shown in FIG. 10. 预封装结构303包括载板310、离型膜320、接点图案331、晶粒垫332、第一保护层333、晶粒341、接合导线342与膜封材料343。 Prepackaged structure 303 includes a carrier plate 310, the release film 320, contact pattern 331, die pad 332, a first protective layer 333, crystal 341, bonding wires 342 and the membrane 343 sealing material. 离型膜320贴合至载板上310,膜封材料342则覆盖离型膜320。 Release film 320 bonded to the carrier plate 310, the film 342 covers the sealing material 320 from the film. 接点图案331与晶粒垫332则一齐位于膜封材料343中。 Contact pattern 331 together with the die pad 332 is located in the membrane sealing material 343. 第一保护层333完全位于膜封材料343中,且覆盖接点图案331与晶粒垫332。 A first protective layer 333 located entirely in the membrane sealing material 343, and covers the contact pattern 331 and die pad 332. 晶粒341位于晶粒垫332上,亦完全位于膜封材料343中。 Die 341 located on the die pad 332, also located entirely in the membrane sealing material 343. 接合导线342完全位于膜封材料343中,并选择性电连接晶粒341与接点图案331。 Bonding wire 342 is located completely in the membrane sealing material 343, die 341 and selectively electrically connected to the contact pattern 331.

[0042] 在本发明又一实施例中,图10所示的预封装结构303又可以进一步经过另一步骤,而得到另一预封装结构305。 [0042] In a further embodiment of the present invention, the pre-packaging structure 303 shown in FIG. 10 can be further via another step, another pre-packaged and the obtained structure 305. 图11例示本发明制作另一预封装结构的延续方法。 11 illustrates the production of the present invention is a further continuation of the method of pre-packaging structure. 请参考图11,将图10所示的预封装结构303中的载板310与离型膜320分别或同时移除后,即可得到另一预封装结构305。 Please refer to FIG. 11, the pre-packaged structure 303 shown in FIG. 10 in the carrier plate 310 with release film 320 after removal separately or simultaneously, to give a further pre-packaged structure 305. 预封装结构305包括接点图案331、晶粒垫332、第一保护层333、晶粒341、接合导线342与膜封材料343。 The package structure 305 includes a pre-contact pattern 331, die pad 332, a first protective layer 333, crystal 341, bonding wires 342 and the membrane 343 sealing material. 接点图案331、晶粒垫332、第一保护层333、 晶粒341与接合导线342 —齐位于膜封材料343中。 Contact pattern 331, die pad 332, a first protective layer 333, bonding wires 342 and 341 crystal grains - Homogeneous sealing material 343 is located in the membrane. 第一保护层333覆盖接点图案331与晶粒垫332。 A first protective layer 333 covers the contact pattern 331 and the die pad 332. 晶粒341位于晶粒垫332上,接合导线342则选择性电连接晶粒341与接点图案331。 Die 341 located on the die pad 332, bonding wires 342 electrically connect die 341 to selectively contact pattern 331.

[0043] 请注意,由于离型膜320与载板310间的粘着力较强,离型膜320与经过图案化的铜箔330间的粘着力相对较弱,所以可以很轻易地移除预封装结构303中的离型膜320与载板310,又不会影响预封装结构303中的其他部份。 [0043] Note that, since the adhesion between release film 320 and the carrier 310 is strong, and a release film 320 through the adhesion between the copper foil pattern 330 is relatively weak, can be removed easily pre the package structure 303 from the film 320 and the carrier 310, without affecting other parts of the structure 303 in a pre-packaged. 此时,接点图案331与晶粒垫332则一齐留在膜封材料343中。 At this time, contact pattern 331 together with the die pad 332 to remain in sealing material 343 in the film. 封装结构305在移除预封装结构303中的载板310与离型膜320后,接点图案331与晶粒垫332的一侧便会暴露出来。 The package structure 305 in the carrier 303 is removed in the pre-package 310 after the release film 320, the grain side of the contact pattern 331 and the pad 332 will be exposed.

[0044] 为了保护接点图案331与晶粒垫332中的脆弱铜箔,在本发明再一实施例中,图11 所示的另一预封装结构305可以再进一步经过保护步骤,而得到封装结构307。 [0044] In order to protect the contact pattern 331 and the die pad 332 fragile copper foil of the present invention, in a further embodiment, a further pre-packaging structure 305 shown in Figure 11 can be further protected through the step, to obtain a package structure 307. 图12例示本发明制作封装结构的延续方法。 12 illustrates a continuation of the method of fabricating the package structure of the present invention. 请参考图11所例示的预封装结构305,还可以进一步在接点图案331与晶粒垫332上形成第二保护层344,来完全覆盖住接点图案331与晶粒垫332。 Please refer to FIG illustrated pre-package structure 305 may further second protective layer 344 is formed on the contact pattern 331 and the die pad 332 to completely cover the contact pattern 331 and the die pad 332. 第二保护层344可以使用电镀的方法,形成包括镍、银与金其中至少一种、而像是镍/ 金的复合保护层,或为有机保焊剂(OSP)。 The second protective layer 344 may be a plating method, comprising forming a nickel, wherein at least one of silver and gold, and the like nickel / gold composite protective layer, or an organic solderability preservative (OSP).

[0045] 经过以上步骤后,就可以得到一个新颖的封装结构307。 [0045] After the above step, you can get a novel package structure 307. 请参考图12,所示为本发明所提供的封装结构307。 Please refer to FIG. 12, the present invention provides a package structure 307 shown in FIG. 在本发明的封装结构307中,包括接点图案331、晶粒垫332、第一保护层333、晶粒341、接合导线342、膜封材料343与第二保护层344。 In the package structure 307 to the invention, comprising contact pattern 331, die pad 332, a first protective layer 333, die 341, bond wires 342, the membrane sealing material 343 and the second protective layer 344. 接点图案331、晶粒垫332、第一保护层333、晶粒341与接合导线342 —齐位于膜封材料343中。 Contact pattern 331, die pad 332, a first protective layer 333, bonding wires 342 and 341 crystal grains - Homogeneous sealing material 343 is located in the membrane. 第一保护层333覆盖接点图案331与晶粒垫332,第二保护层344则位于该膜封材料外,并覆盖接点图案331与晶粒垫332。 A first protective layer 333 covers the contact pattern 331 and the die pad 332, a second protective layer 344 is located at the outer membrane sealing material, and covers the contact pattern 331 and the die pad 332. 晶粒341位于晶粒垫332上,接合导线342则选择性电连接晶粒341与接点图案331。 Die 341 located on the die pad 332, bonding wires 342 electrically connect die 341 to selectively contact pattern 331. 本发明封装结构307的其他特征,例如封装体,可以参考前述而不再重复。 Other features of the present invention, the package structure 307, such as a package, the reference may not be repeated.

[0046] 以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,皆应属本发明的涵盖范围。 [0046] The above are only preferred embodiments of the present invention, all modifications and alterations made under this invention as claimed in claim, also belong to the scope of the present invention.

Claims (19)

  1. 1. 一种制作电路板的方法,其特征在于包括:提供基板,该基板包括载板、铜箔与位于该载板与该铜箔间的离型膜;图案化该铜箔,使得该铜箔形成接点图案与晶粒垫;以及形成第一保护层,分别覆盖该接点图案与该晶粒垫,以形成电路板。 1. A method of making a circuit board, comprising: providing a substrate comprising a carrier plate, copper foil and the release film is located between the carrier plate and the copper foil; patterning the copper foil so that the copper foil contact pattern and die pad; and forming a first protective layer, respectively covering the contact pattern with the die pad to form a circuit board.
  2. 2.如权利要求1所述的制作电路板的方法,其特征在于该基板的厚度为150〜400微米。 Method of making a circuit board as claimed in claim 2, characterized in that the thickness of the substrate is 150~400 microns.
  3. 3.如权利要求1所述的制作电路板的方法,其特征在于更包括: 将该离型膜涂布至该铜箔;以及将具有该铜箔的该离型膜贴合至该载板,以形成该基板。 3. The method of manufacturing a circuit board according to claim 1, characterized by further comprising: a release film is applied to the copper foil; and the carrier plate having the copper foil bonded to a release film to form the substrate.
  4. 4.如权利要求1所述的制作电路板的方法,其特征在于使用网印法与滚轮法其中至少一种,将该离型膜涂布至该铜箔。 4. The method of making a circuit board as claimed in claim, characterized in that a screen printing method and wherein at least one of the rollers, the release film is applied to the copper foil.
  5. 5.如权利要求1所述的制作电路板的方法,其特征在于更包括: 将该离型膜涂布至该载板;以及将具有该载板的该离型膜贴合至该铜箔,以形成该基板。 5. The method of manufacturing a circuit board according to claim 1, characterized by further comprising: the release film is applied to the carrier plate; and said carrier plate having the release film laminated to the foil to form the substrate.
  6. 6.如权利要求1所述的制作电路板的方法,其特征在于使用网印法与滚轮法其中至少一种,将该离型膜涂布至该载板。 Method of making a circuit board as claimed in claim 6, characterized in that a screen printing method and wherein at least one of the rollers, the release film is applied to the carrier plate.
  7. 7.如权利要求1所述的制作电路板的方法,其特征在于该第一保护层包括镍、银或金。 7. The method of making a circuit board as claimed in claim, wherein the first protective layer comprises nickel, silver or gold.
  8. 8.如权利要求1所述的制作电路板的方法,其特征在于更包括: 形成位于该载板上的封装体。 Method of making a circuit board as claimed in claim 8, characterized by further comprising: forming the body of the package carrier board.
  9. 9.如权利要求8所述的制作电路板的方法,其特征在于该封装体包括: 晶粒,位于该晶粒垫上;接合导线,选择性电连接该晶粒与该接点图案;以及膜封材料,密封该晶粒与该接合导线并直接接触该离型膜。 9. The method of making a circuit board according to claim 8, characterized in that the package comprising: a die, the die pad is located; bonding wire is selectively electrically connecting the die to the contact pattern; and a film sealing material, sealing the bonding wires and to the die in direct contact with the release film.
  10. 10.如权利要求9所述的制作电路板的方法,其特征在于该膜封材料包围该接点图案与该晶粒垫。 10. The method of making a circuit board according to claim 9, characterized in that the membrane surrounds the sealing material and the die pad contact pattern.
  11. 11.如权利要求8所述的制作电路板的方法,其特征在于更包括: 同时移除该离型膜与该载板,以暴露出该接点图案与该晶粒垫。 11. The method of making a circuit board according to claim 8, characterized in that further comprising: simultaneously removing the release film and the carrier plate to expose the contact pattern of the die pad.
  12. 12.如权利要求9所述的制作电路板的方法,其特征在于该晶粒位于该接点图案之间。 12. The method of manufacturing a circuit board according to claim 9, characterized in that the die is positioned between the contact pattern.
  13. 13.如权利要求11所述的制作电路板的方法,其特征在于更包括: 形成第二保护层,以覆盖该接点图案与该晶粒垫。 13. The method of manufacturing a circuit board according to claim 11, characterized by further comprising: forming a second protective layer to cover the contact pattern of the die pad.
  14. 14.如权利要求13所述的制作电路板的方法,其特征在于该第二保护层包括镍、银或^^ ο 14. The method of claim 13 making a circuit board as claimed in claim, wherein the second protective layer comprises nickel, silver, or ^^ ο
  15. 15.如权利要求13所述的制作电路板的方法,其特征在于该第二保护层包括有机保焊剂。 15. The method of manufacturing a circuit board according to claim 13, wherein the second protective layer comprises an organic solderability preservative.
  16. 16. 一种电路板结构,其特征在于包括: 载板;离型膜,贴合至该载板;接点图案,位于该离型膜上并直接接触该离型膜; 晶粒垫,位于该离型膜上;以及保护层,分别覆盖该接点图案与该晶粒垫。 16. A circuit board structure comprising: a carrier plate; off film, bonded to said carrier plate; contact pattern, the release film is located and in direct contact with the release film; die pad located a release film; and a protective layer, respectively covering the die pad with the contact pattern.
  17. 17. 一种封装结构,其特征在于包括: 载板;离型膜,贴合至该载板; 膜封材料,覆盖该离型膜; 接点图案,位于该膜封材料中; 晶粒垫,位于该膜封材料中;保护层,完全位于该膜封材料中且覆盖该接点图案与该晶粒垫;晶粒,完全位于该膜封材料中与该晶粒垫上;以及接合导线,完全位于该膜封材料中并选择性电连接该晶粒与该接点图案。 17. A package structure comprising: a carrier plate; off film, bonded to said carrier plate; membrane sealing material, covering the release film; contact pattern, located in the membrane sealing material; die pad, the membrane sealing material is located; protective layer, located entirely in the membrane and the sealing material covering the contact pattern of the die pad; grains located completely seal the film to the die pad material; and bonding wires, located entirely the sealing film material in the die and selectively electrically connected to the contact pattern.
  18. 18. 一种封装结构,其特征在于包括: 膜封材料;接点图案,位于该膜封材料中; 晶粒垫,位于该膜封材料中;保护层,完全位于该膜封材料中且覆盖该接点图案与该晶粒板;晶粒,完全位于该膜封材料中与该晶粒垫上;以及接合导线,完全位于该膜封材料中并选择性电连接该晶粒与该接点图案。 18. A package structure, comprising: a membrane sealing material; contact pattern, located in the membrane sealing material; die pad on the membrane sealing material; protective layer, located entirely in the membrane and covered with the sealing material a contact pattern of the die plate; grains located completely seal the film to the die pad material; and bonding wires, located completely seal the film material in the die and selectively electrically connected to the contact pattern.
  19. 19. 一种封装结构,其特征在于包括: 膜封材料;接点图案,位于该膜封材料中; 晶粒垫,位于该膜封材料中;第一保护层,完全位于该膜封材料中且覆盖该接点图案与该晶粒垫; 第二保护层,位于该膜封材料外且覆盖该接点图案与该晶粒垫; 晶粒,完全位于该膜封材料中与该晶粒垫上;以及接合导线,完全位于该膜封材料中并选择性电连接该晶粒与该接点图案。 19. A package structure, comprising: a membrane sealing material; contact pattern, located in the membrane sealing material; die pad on the membrane sealing material; a first protective layer, located entirely in the membrane and the sealing material covering the contact pattern of the die pad; a second protective layer located on the outer membrane of the sealing material and covers the contact pattern of the die pad; grains located completely sealing the film material to the die pad; and engaging wire located completely seal the film material in the die and selectively electrically connected to the contact pattern.
CN 201010190900 2010-06-02 2010-06-02 A circuit board structure, the package structure and production of the circuit board CN102270584A (en)

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