CN102270584A - Circuit board structure, packaging structure and method for manufacturing circuit board - Google Patents
Circuit board structure, packaging structure and method for manufacturing circuit board Download PDFInfo
- Publication number
- CN102270584A CN102270584A CN2010101909009A CN201010190900A CN102270584A CN 102270584 A CN102270584 A CN 102270584A CN 2010101909009 A CN2010101909009 A CN 2010101909009A CN 201010190900 A CN201010190900 A CN 201010190900A CN 102270584 A CN102270584 A CN 102270584A
- Authority
- CN
- China
- Prior art keywords
- crystal grain
- contact pattern
- film
- closure material
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45139—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45565—Single coating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45599—Material
- H01L2224/456—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45644—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
The invention discloses a circuit board structure, a packaging structure and method for manufacturing a circuit board. The method comprises the following steps: firstly, providing a substrate comprising a support plate, a copper foil and a release film between the support plate and the copper foil; secondly, patterning the copper foil, thus the copper foil forms a contact patter and a crystalline grain base plate; and finally, forming a first protection layer for covering a contact pattern and the crystalline grain base plate respectively so as to form the circuit board.
Description
Technical field
The invention relates to a kind of method of circuit board manufacturing, prepared board structure of circuit and encapsulating structure.Special, the invention relates to a kind of support plate and Copper Foil, and then make the method for board structure of circuit and encapsulating structure by being fitted with release film.
Background technology
Circuit board is a kind of important element in the electronic installation.Constantly pursue under the trend that size dwindles at electronic installation, develop and multiple different carrier (carrier) structure that supports crystal grain, and stretch out and be positioned at circuit board other circuit all around and form suitable being electrically connected with pin (pin).
With regard to present technology, known have a kind of board structure of circuit that is called lead frame (lead frame).Fig. 1-4 is depicted as the method for making lead frame traditionally.Please refer to Fig. 1, a metal substrate 101 at first is provided.Secondly, please refer to Fig. 2,, estimate the corresponding chip circuit pattern 110 of (figure does not show) to form, with crystal grain pad 111 with metal substrate 101 patternings.Then, form via (via hole) 122, be connected to pin 120 on the metal substrate 101 and with pin 120 and crystal grain pad 111 silver-plated 121.Come again, please refer to Fig. 3, with crystal grain 130 glutinous to the crystal grain pad 111 after, continue lead packages (wire bonding) and zinc-plated step.Then, please refer to Fig. 4, next finish the pin moulding, and obtain the encapsulating structure 102 of a chip.The data of chip promptly sees through the circuit communication of pin 120 to the external world.
Yet, when the handled data quantity of chip increases and processing speed when accelerating, more than shown in lead frame, but because the chip peripheral space is limited, and can't increase more pin 120 accordingly with the cooperation demand.Thus, just make the application of conventional wires frame encapsulating structure 102 be restricted.
Figure 5 shows that the carrier structure 201 of another supporting chip.In carrier structure 201, circuit pattern 220 lays respectively at the both sides of substrate 210.In addition, 230 both sides that optionally are positioned at substrate 210 of welding resisting layer, suitably the protective circuit pattern 220.In addition, expose circuit pattern 220 partly again.In this carrier structure 201, need form independently welding resisting layer pattern 231/232 in the both sides of substrate 210.Welding resisting layer pattern 231/232 has nothing in common with each other usually, could be to deal with the different demands of crystal grain pad (figure do not show) position and soldered ball (scheming not show) position.
After the carrier structure 201 of supporting chip shown in Figure 5 carrying out encapsulation step, just can obtain encapsulating structure shown in Figure 6 202.In encapsulating structure shown in Figure 6 202, except substrate shown in Figure 5 210, circuit pattern 220, welding resisting layer 230 and welding resisting layer pattern 231/232, also because encapsulation step has afterwards increased crystal grain pad 221, crystal grain 240, wire bonds 250, film closure material (encapsulant) 260 and soldered ball 270.
Because above carrier structure, encapsulating structure and make the method and the imperfection of lead frame traditionally, therefore still wish to have other novel board structure of circuit, encapsulating structure and preparation method thereof, can structurally simplify more, and can also break through traditionally restriction.
Summary of the invention
So the present invention proposes board structure of circuit, encapsulating structure of a kind of novelty and preparation method thereof.Board structure of circuit proposed by the invention and encapsulating structure, mode that can usable floor area array (area array) designs, and can increase the design space on overall structure, so can be so that encapsulation volume diminishes.In addition, release film of the present invention (release film) also makes things convenient for separating of support plate and Copper Foil.
The present invention proposes a kind of method of circuit board manufacturing.At first, provide a substrate, it comprise a support plate, a Copper Foil and be positioned at support plate and Copper Foil between a release film.Secondly, the patterning Copper Foil makes Copper Foil form a contact pattern and a crystal grain pad.Then, form one first protective layer, cover contact pattern and crystal grain pad respectively, to form a circuit board.
In an embodiment of the present invention, can earlier release film be applied to Copper Foil after, the release film that will have Copper Foil again conforms on the support plate, to form substrate.In another embodiment of the present invention, then can earlier release film be applied to support plate after, the release film that will have support plate again conforms to Copper Foil, to form substrate.In further embodiment of this invention, can also form the packaging body that is positioned on the support plate.In yet another embodiment of the invention, then can continue to remove release film and support plate, and expose the contact pattern with the crystal grain pad, so the encapsulating structure of getting back.
Secondly the present invention proposes a kind of board structure of circuit.Board structure of circuit of the present invention comprises support plate, release film, contact pattern, crystal grain pad and protective layer.Release film conforms on the support plate, and the contact pattern then is positioned on the release film and directly contacts release film.The crystal grain pad is positioned on the release film, also directly contacts release film.Protective layer covers contact pattern and crystal grain pad respectively.
The present invention proposes a kind of encapsulating structure again.Encapsulating structure of the present invention comprises support plate, release film, film closure material, contact pattern, crystal grain pad, protective layer, crystal grain and wire bonds.Release film conforms on the support plate, and the film closure material then covers release film.Contact pattern and crystal grain pad then are arranged in the film closure material simultaneously.Protective layer is arranged in the film closure material fully and covers contact pattern and crystal grain pad.Crystal grain also is arranged in the film closure material fully and is positioned on the crystal grain pad.Wire bonds is arranged in the film closure material fully and selectivity is electrically connected crystal grain and contact pattern.
The present invention proposes a kind of encapsulating structure in addition.Encapsulating structure of the present invention comprises film closure material, contact pattern, crystal grain pad, protective layer, crystal grain and wire bonds.Contact pattern and crystal grain pad all are arranged in the film closure material.Protective layer is arranged in the film closure material fully, and covers contact pattern and crystal grain pad.Crystal grain is arranged in the film closure material fully and is positioned on the crystal grain pad.Wire bonds also is arranged in the film closure material fully, and selectivity is electrically connected crystal grain and contact pattern.
The present invention reintroduces a kind of encapsulating structure.Encapsulating structure of the present invention comprises film closure material, contact pattern, crystal grain pad, first protective layer, second protective layer, crystal grain and wire bonds.Contact pattern and crystal grain pad all are arranged in the film closure material.First protective layer is arranged in the film closure material fully, and covers contact pattern and crystal grain pad.Second protective layer then is positioned at outside the film closure material, and covers contact pattern and crystal grain pad.Crystal grain is arranged in the film closure material fully and is positioned on the crystal grain pad.Wire bonds also is arranged in the film closure material fully, and selectivity is electrically connected crystal grain and contact pattern.
Description of drawings
Fig. 1-4 is depicted as the method for making lead frame traditionally.
Figure 5 shows that the carrier structure of another supporting wafers.
Figure 6 shows that encapsulating structure traditionally.
Fig. 7-8 is depicted as the method for circuit board manufacturing of the present invention.
Figure 9 shows that board structure of circuit proposed by the invention.
Figure 10 shows that the present invention makes the continuity method of pre-packaged structure.
Figure 11 shows that the present invention makes the continuity method of another pre-packaged structure.
Figure 12 shows that the present invention makes the continuity method of encapsulating structure.
Wherein, description of reference numerals is as follows:
301 board structure of circuit, 332 crystal grain pads
303 pre-packaged structure 333 first protective layers
305 pre-packaged structure 340 packaging bodies
307 encapsulating structures, 341 crystal grain
309 substrates, 342 wire bonds
310 support plates, 305 pre-packaged structures
320 release films, 343 film closure materials
330 Copper Foils, 344 second protective layers
331 contact patterns
Embodiment
First aspect present invention proposes a kind of method of circuit board manufacturing.Fig. 7-8 is depicted as the method for circuit board manufacturing of the present invention.Please refer to Fig. 7, substrate 309 at first is provided, it comprises support plate 310, release film 320 and Copper Foil 330.Release film 320 is between support plate 310 and Copper Foil 330.Support plate 310 can be any material, for example polyethylene terephthalate (PET), Merlon (PC), polymethyl methacrylate (PMMA) and no copper base or the like.Release film 320 can have plastic cohesive material and and 310 stronger adhesion strengths of generation of support plate for a kind of.Therefore release film 320 promptly by this adhesion strength be fitted on the one side of support plate 310.Substrate 309 can have the thickness of 150～400 μ m, is preferably the thickness of 265 μ m.
Secondly, please refer to Fig. 8 because outside the one side of Copper Foil 330 still is exposed to, so when Copper Foil 330 behind patterning, will make Copper Foil 330 be formed with pattern, for example contact pattern 331 and crystal grain pad (diepad) 332.Can use for example dry film method or wet film method, come patterning Copper Foil 330.Contact pattern 331 is different with the function of crystal grain pad 332.For example, crystal grain pad 332 is used for carrying a predetermined crystal grain (figure does not show).331 in contact pattern can be the crystal grain electrical connection pad (connecting pad) of (figure does not show).
Continue, please refer to Fig. 9,, need form first protective layer 333 on the surface of Copper Foil 330 in order to protect fragile Copper Foil 330.Owing to have different separately contact pattern of function 331 and crystal grain pad 332 on the patterning Copper Foil 330, first protective layer 333 also can cover contact pattern 331 and crystal grain pad 332 respectively.Can use electric plating method, form first protective layer 333 on the surface of Copper Foil 330.First protective layer 333 can be a kind of composite layer, and for example first protective layer 333 can comprise that nickel, silver and gold are wherein at least a, and formation similarly is the protective layer of nickel/gold.
Through after the above step, the support plate 310 that presses together, release film 320 and Copper Foil 330 will form the board structure of circuit 301 of a novelty.Please refer to Fig. 9, be depicted as board structure of circuit proposed by the invention 301.In board structure of circuit 301 of the present invention, comprise support plate 310, release film 320, contact pattern 331, crystal grain pad 332 and first protective layer 333.Release film 320 conforms on the support plate 310, and contact pattern 331 lays respectively on the release film 320 with 332 on crystal grain pad, and directly contacts release film 320.First protective layer 333 covers contact pattern 331 and crystal grain pad 332 respectively.
In another embodiment of the present invention, board structure of circuit 301 shown in Figure 9 can also be further through a pre-packaged step, and obtains a pre-packaged structure 303.Figure 10 shows that the present invention makes the continuity method of pre-packaged structure.Please refer to Figure 10, board structure of circuit 301 shown in Figure 9 can also further form a packaging body 340 on release film 320.For example, earlier crystal grain 341 is sticked on crystal grain pad 332.For example, the material (figure does not show) that can use elargol 334 maybe can dispel the heat sticks crystal grain 341 on crystal grain pad 332.Then, use wire bonds 342, for example copper cash, silver-colored line, gold thread or gold-plated copper cash or the like, depending on the circumstances or the needs of the situation selectivity is electrically connected the contact pattern 331 of crystal grain 341 with part.After electrical connection is finished, promptly can use film closure material 343, for example epoxy resin seals crystal grain 341 and wire bonds 342, to stop the external world, for example pollution of aqueous vapor.
Board structure of circuit 301 shown in Figure 9 further after forming a packaging body 340 on the release film 320, can obtain pre-packaged structure 303 shown in Figure 10.Pre-packaged structure 303 comprises support plate 310, release film 320, contact pattern 331, crystal grain pad 332, first protective layer 333, crystal grain 341, wire bonds 342 and film closure material 343.Release film 320 conforms on the support plate 310, and 342 of film closure materials cover release film 320.Contact pattern 331 is arranged in film closure material 343 simultaneously with 332 on crystal grain pad.First protective layer 333 is arranged in film closure material 343 fully, and covers contact pattern 331 and crystal grain pad 332.Crystal grain 341 is positioned on the crystal grain pad 332, also is arranged in film closure material 343 fully.Wire bonds 342 is arranged in film closure material 343 fully, and selectivity is electrically connected crystal grain 341 and contact pattern 331.
In further embodiment of this invention, pre-packaged structure 303 shown in Figure 10 can further be passed through another step again, and obtains another pre-packaged structure 305.The present invention of Figure 11 illustration makes the continuity method of another pre-packaged structure.Please refer to Figure 11, after support plate in the pre-packaged structure 303 shown in Figure 10 310 and release film 320 are removed respectively or simultaneously, can obtain another pre-packaged structure 305.Pre-packaged structure 305 comprises contact pattern 331, crystal grain pad 332, first protective layer 333, crystal grain 341, wire bonds 342 and film closure material 343.Contact pattern 331, crystal grain pad 332, first protective layer 333, crystal grain 341 are arranged in film closure material 343 simultaneously with wire bonds 342.First protective layer 333 covers contact pattern 331 and crystal grain pad 332.Crystal grain 341 is positioned on the crystal grain pad 332, and 342 selectivity of wire bonds are electrically connected crystal grain 341 and contact pattern 331.
Please note, because the adhesion strength that release film 320 and support plate are 310 is stronger, release film 320 with through the adhesion strength of 330 of the Copper Foils of patterning relative a little less than, so can remove release film 320 and support plate 310 in the pre-packaged structure 303 easily, can not influence other parts in the pre-packaged structure 303 again.At this moment, contact pattern 331 is stayed in the film closure material 343 simultaneously with 332 on crystal grain pad.Behind the support plate 310 and release film 320 of encapsulating structure 305 in removing pre-packaged structure 303, contact pattern 331 just can come out with a side of crystal grain pad 332.
In order to protect the fragile Copper Foil in contact pattern 331 and the crystal grain pad 332, in yet another embodiment of the invention, the pre-packaged structure 305 of shown in Figure 11 another can be more further through the overprotection step, and obtains encapsulating structure 307.The present invention of Figure 12 illustration makes the continuity method of encapsulating structure.Please refer to the illustrated pre-packaged structure 305 of Figure 11, can also further on contact pattern 331 and crystal grain pad 332, form second protective layer 344, cover contact pattern 331 and crystal grain pad 332 fully.Second protective layer 344 can use electric plating method, forms to comprise nickel, silver with golden wherein at least a and similarly be the composite protection layer of nickel/gold, or is organic solderability preservative (OSP).
Through after the above step, just can obtain the encapsulating structure 307 of a novelty.Please refer to Figure 12, be depicted as encapsulating structure 307 provided by the present invention.In encapsulating structure 307 of the present invention, comprise contact pattern 331, crystal grain pad 332, first protective layer 333, crystal grain 341, wire bonds 342, film closure material 343 and second protective layer 344.Contact pattern 331, crystal grain pad 332, first protective layer 333, crystal grain 341 are arranged in film closure material 343 simultaneously with wire bonds 342.First protective layer 333 covers contact pattern 331 and is positioned at outside this film closure material with 344 of crystal grain pad 332, the second protective layers, and covers contact pattern 331 and crystal grain pad 332.Crystal grain 341 is positioned on the crystal grain pad 332, and 342 selectivity of wire bonds are electrically connected crystal grain 341 and contact pattern 331.Other features of encapsulating structure 307 of the present invention, packaging body for example can be with reference to aforementioned and no longer repeat.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (19)
1. the method for a circuit board manufacturing is characterized in that comprising:
Substrate is provided, this substrate comprise support plate, Copper Foil and be positioned at this support plate and this Copper Foil between release film;
This Copper Foil of patterning makes this Copper Foil form contact pattern and crystal grain pad; And
Form first protective layer, cover this contact pattern and this crystal grain pad respectively, to form circuit board.
2. the method for circuit board manufacturing as claimed in claim 1, the thickness that it is characterized in that this substrate is 150～400 microns.
3. the method for circuit board manufacturing as claimed in claim 1 is characterized in that more comprising:
This release film is applied to this Copper Foil; And
This release film that will have this Copper Foil conforms to this support plate, to form this substrate.
4. the method for circuit board manufacturing as claimed in claim 1 is characterized in that using wire mark method and roller method wherein at least a, and this release film is applied to this Copper Foil.
5. the method for circuit board manufacturing as claimed in claim 1 is characterized in that more comprising:
This release film is applied to this support plate; And
This release film that will have this support plate conforms to this Copper Foil, to form this substrate.
6. the method for circuit board manufacturing as claimed in claim 1 is characterized in that using wire mark method and roller method wherein at least a, and this release film is applied to this support plate.
7. the method for circuit board manufacturing as claimed in claim 1 is characterized in that this first protective layer comprises nickel, silver or golden.
8. the method for circuit board manufacturing as claimed in claim 1 is characterized in that more comprising:
Formation is positioned at the packaging body on this support plate.
9. the method for circuit board manufacturing as claimed in claim 8 is characterized in that this packaging body comprises:
Crystal grain is positioned on this crystal grain pad;
Wire bonds, selectivity are electrically connected this crystal grain and this contact pattern; And
The film closure material seals this crystal grain and also directly contacts this release film with this wire bonds.
10. the method for circuit board manufacturing as claimed in claim 9 is characterized in that this film closure material surrounds this contact pattern and this crystal grain pad.
11. the method for circuit board manufacturing as claimed in claim 8 is characterized in that more comprising:
Remove this release film and this support plate simultaneously, to expose this contact pattern and this crystal grain pad.
12. the method for circuit board manufacturing as claimed in claim 9 is characterized in that this crystal grain is between this contact pattern.
13. the method for circuit board manufacturing as claimed in claim 11 is characterized in that more comprising:
Form second protective layer, to cover this contact pattern and this crystal grain pad.
14. the method for circuit board manufacturing as claimed in claim 13 is characterized in that this second protective layer comprises nickel, silver or golden.
15. the method for circuit board manufacturing as claimed in claim 13 is characterized in that this second protective layer comprises organic solderability preservative.
16. a board structure of circuit is characterized in that comprising:
Support plate;
Release film conforms to this support plate;
The contact pattern is positioned on this release film and direct this release film of contact;
The crystal grain pad is positioned on this release film; And
Protective layer covers this contact pattern and this crystal grain pad respectively.
17. an encapsulating structure is characterized in that comprising:
Support plate;
Release film conforms to this support plate;
The film closure material covers this release film;
The contact pattern is arranged in this film closure material;
The crystal grain pad is arranged in this film closure material;
Protective layer is arranged in this film closure material fully and covers this contact pattern and this crystal grain pad;
Crystal grain is arranged on this film closure material and this crystal grain pad fully; And
Wire bonds is arranged in this film closure material and selectivity fully and is electrically connected this crystal grain and this contact pattern.
18. an encapsulating structure is characterized in that comprising:
The film closure material;
The contact pattern is arranged in this film closure material;
The crystal grain pad is arranged in this film closure material;
Protective layer is arranged in this film closure material fully and covers this contact pattern and this crystal grain plate;
Crystal grain is arranged on this film closure material and this crystal grain pad fully; And
Wire bonds is arranged in this film closure material and selectivity fully and is electrically connected this crystal grain and this contact pattern.
19. an encapsulating structure is characterized in that comprising:
The film closure material;
The contact pattern is arranged in this film closure material;
The crystal grain pad is arranged in this film closure material;
First protective layer is arranged in this film closure material fully and covers this contact pattern and this crystal grain pad;
Second protective layer, it is outer and cover this contact pattern and this crystal grain pad to be positioned at this film closure material;
Crystal grain is arranged on this film closure material and this crystal grain pad fully; And
Wire bonds is arranged in this film closure material and selectivity fully and is electrically connected this crystal grain and this contact pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101909009A CN102270584A (en) | 2010-06-02 | 2010-06-02 | Circuit board structure, packaging structure and method for manufacturing circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101909009A CN102270584A (en) | 2010-06-02 | 2010-06-02 | Circuit board structure, packaging structure and method for manufacturing circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102270584A true CN102270584A (en) | 2011-12-07 |
Family
ID=45052828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101909009A Pending CN102270584A (en) | 2010-06-02 | 2010-06-02 | Circuit board structure, packaging structure and method for manufacturing circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102270584A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103240770A (en) * | 2012-02-09 | 2013-08-14 | 旭德科技股份有限公司 | Edge separation equipment and operation method thereof |
| CN103484902A (en) * | 2012-04-04 | 2014-01-01 | 罗门哈斯电子材料有限公司 | Metal plating for ph sensitive applications |
| CN103632979A (en) * | 2012-08-27 | 2014-03-12 | 宏启胜精密电子(秦皇岛)有限公司 | Chip packaging substrate and structure, and manufacturing methods thereof |
| TWI467714B (en) * | 2012-06-18 | 2015-01-01 | 矽品精密工業股份有限公司 | Semiconductor package and method of forming the same |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020168798A1 (en) * | 1996-10-31 | 2002-11-14 | Glenn Thomas P. | Method of making near chip size integrated circuit package |
| CN1424756A (en) * | 2001-12-13 | 2003-06-18 | 松下电器产业株式会社 | Metal wiring substrate, semiconductor device and manufacture thereof |
| US20040000062A1 (en) * | 2002-06-28 | 2004-01-01 | Johnson Controls Technology Company | Compass display for a vehicle |
| JP2007311713A (en) * | 2006-05-22 | 2007-11-29 | Hitachi Cable Ltd | Substrate for electronic apparatus, its manufacturing method, electronic apparatus, and its manufacturing method |
| US20090041270A1 (en) * | 2004-12-06 | 2009-02-12 | Austriamicrosystems Ag | Mems Microphone And Method For Producing Said Microphone |
| CN101488463A (en) * | 2008-01-17 | 2009-07-22 | 阿克泰克萨特株式会社 | Production method of substrate for semiconductor parcage, and metal plating produced by the same |
-
2010
- 2010-06-02 CN CN2010101909009A patent/CN102270584A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020168798A1 (en) * | 1996-10-31 | 2002-11-14 | Glenn Thomas P. | Method of making near chip size integrated circuit package |
| CN1424756A (en) * | 2001-12-13 | 2003-06-18 | 松下电器产业株式会社 | Metal wiring substrate, semiconductor device and manufacture thereof |
| US20040000062A1 (en) * | 2002-06-28 | 2004-01-01 | Johnson Controls Technology Company | Compass display for a vehicle |
| US20090041270A1 (en) * | 2004-12-06 | 2009-02-12 | Austriamicrosystems Ag | Mems Microphone And Method For Producing Said Microphone |
| JP2007311713A (en) * | 2006-05-22 | 2007-11-29 | Hitachi Cable Ltd | Substrate for electronic apparatus, its manufacturing method, electronic apparatus, and its manufacturing method |
| CN101488463A (en) * | 2008-01-17 | 2009-07-22 | 阿克泰克萨特株式会社 | Production method of substrate for semiconductor parcage, and metal plating produced by the same |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103240770A (en) * | 2012-02-09 | 2013-08-14 | 旭德科技股份有限公司 | Edge separation equipment and operation method thereof |
| CN103240770B (en) * | 2012-02-09 | 2015-09-16 | 旭德科技股份有限公司 | Edge separation equipment and operation method thereof |
| CN103484902A (en) * | 2012-04-04 | 2014-01-01 | 罗门哈斯电子材料有限公司 | Metal plating for ph sensitive applications |
| TWI467714B (en) * | 2012-06-18 | 2015-01-01 | 矽品精密工業股份有限公司 | Semiconductor package and method of forming the same |
| CN103632979A (en) * | 2012-08-27 | 2014-03-12 | 宏启胜精密电子(秦皇岛)有限公司 | Chip packaging substrate and structure, and manufacturing methods thereof |
| CN103632979B (en) * | 2012-08-27 | 2017-04-19 | 碁鼎科技秦皇岛有限公司 | Chip packaging substrate and structure, and manufacturing methods thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8004068B2 (en) | Shielded multi-layer package structures | |
| US20160148861A1 (en) | First-packaged and later-etched three-dimensional flip-chip system-in-package structure and processing method therefor | |
| US8492181B2 (en) | Embedded wafer level optical package structure and manufacturing method | |
| CN106206485A (en) | Imageing sensor module and preparation method thereof | |
| US9099450B2 (en) | Package structure and method for manufacturing same | |
| KR101085185B1 (en) | Circuit board structure, packaging structure and method for making the same | |
| TW200822336A (en) | Stacked type chip package, chip package and process thereof | |
| TW200913194A (en) | Semiconductor package and manufacturing method thereof | |
| CN102270585B (en) | Circuit board structure, package structure and method for manufacturing circuit board | |
| CN102270584A (en) | Circuit board structure, packaging structure and method for manufacturing circuit board | |
| US9024452B2 (en) | Semiconductor package comprising an interposer and method of manufacturing the same | |
| TW201705426A (en) | Resin-encapsulated semiconductor device and method of manufacturing the same | |
| CN100370589C (en) | Novel integrated circuit or discrete components ultra-thin non-pin packing technology and packing arrangement | |
| CN206558504U (en) | Imaging sensor module | |
| CN206163474U (en) | Image sensor module | |
| KR20020028474A (en) | Electrical connection method between chips and substrate in multi chip package | |
| CN202940236U (en) | Package substrate structure | |
| CN103208467A (en) | Package module with embedded package and method for manufacturing the same | |
| CN102751203A (en) | Semiconductor encapsulation structure and manufacture method of semiconductor encapsulation structure | |
| US8410598B2 (en) | Semiconductor package and method of manufacturing the same | |
| JP2007134618A5 (en) | ||
| KR101148954B1 (en) | Circuit board structure, packaging structure and method for making the same | |
| CN101740410B (en) | Manufacturing process for a chip package structure | |
| TWI250597B (en) | Method for manufacturing multi-chip package having encapsulated bond-wires between stack chips | |
| JP7273209B2 (en) | Method for manufacturing electronic modules for chip cards |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20111207 |