CN1971862A - Chip buried in semiconductor encapsulation base plate structure and its manufacturing method - Google Patents
Chip buried in semiconductor encapsulation base plate structure and its manufacturing method Download PDFInfo
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- CN1971862A CN1971862A CNA2005101233940A CN200510123394A CN1971862A CN 1971862 A CN1971862 A CN 1971862A CN A2005101233940 A CNA2005101233940 A CN A2005101233940A CN 200510123394 A CN200510123394 A CN 200510123394A CN 1971862 A CN1971862 A CN 1971862A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Manufacturing & Machinery (AREA)
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
This invention relates to one chip imbed semiconductor sealing baseboard and its process method, wherein, the structure comprises one metal layer, one insulation layer with open, one supportive board with open and at least one semiconductor chip, one insulation layer and at least one circuit layer. This invention integrates chip and its supportive board process and semiconductor sealing technique to provide large elasticity and to simplify the semiconductor procedure interface.
Description
Technical field
The invention relates to a kind of chip buried in semiconductor encapsulation base plate structure and method for making thereof, particularly about a kind of chip buried in semiconductor encapsulation base plate structure and manufacture method thereof that is integrated with heat sink, semiconductor chip and line construction simultaneously.
Background technology
Since IBM Corporation introduces chip package (Flip Chip Package) technology in early days in nineteen sixty, compare with routing (Wire Bond) technology, the characteristics of Flip Chip are that the electric connection between semiconductor chip and substrate is by solder bump but not general gold thread.The advantage of this Flip Chip is that this technology can improve packaging density to reduce the size of potted element, and simultaneously, this kind Flip Chip need not use the long metal wire of length, can improve electrical performance.In view of this, industry is used high temperature scolding tin on ceramic substrate, and (Control-Collapse Chip Connection C4) has for many years the chip interconnection technique of promptly so-called control disintegration.In recent years, because high density, at a high speed and the increase of semiconductor element demand cheaply, simultaneously in response to the diminishing trend of the volume of electronic product, to cover crystal cell and be arranged on organic circuit board (for example printed circuit board (PCB) or substrate) cheaply, and be filled in chip below with epoxy resin primer (Underfill resin), thermal stress to produce because of thermal dilation difference between the structure that reduces silicon and organic circuit board has presented volatile growth.
In existing Flip Chip, dispose electrical electronic pads (Electrode pads) on the surface of semiconductor integrated circuit (IC) chip, organic circuit board also has corresponding contact pad, between this chip and circuit board solder bump or other conductive adhesive material can be set suitably.This chip is to be arranged on this circuit board in the ventricumbent mode of electrical contact, and wherein, this solder bump or conductive adhesive material provide electrical I/O (I/O) and the mechanical connection between this chip and circuit board.
See also Fig. 1, it is a kind of existing crystal cell that covers.As shown in FIG., on the electronic pads 12 of chip 13, be formed with a plurality of metal couplings 11, and on the contact pad 15 of organic circuit board 16, be formed with a plurality of pre-solder bumps of making by scolder 14, be enough to make under the reflow temperature condition of these pre-solder bump 14 fusions, connecing 17 by pre-solder bump 14 reflows can be formed scolding tin to corresponding metal coupling 11.In addition, can be further in operation in the slit of 16 of this chip 13 and this circuit boards, insert primer material 18, suppress the thermal expansion difference of 16 of this chip 13 and this circuit boards and reduce the stress of this scolding tin knot.
Yet, use a large amount of tin lead (Sn-Pb) materials to electrically connect in the operation of above-mentioned packaging part, this Sn-Pb material cost is higher, so make the cost of manufacture increase and contain the problem that the Pb material can produce the environmental protection aspect; And the lead electrical connection path in the above-mentioned packaging part is long, makes the piece electrical performance effectively to bring into play.
For addressing the above problem, industry proposes a kind of semiconductor packaging of neomorph, be called " the bumpless formula increases layer " encapsulation technology, this BBUL encapsulation technology is not used solder bump (solder bumps) technology, but copper connection (copper connections) mode of using instead at a high speed connects each layer in chip and the encapsulating structure.
Though increasing layer encapsulation, this bumpless formula can improve the problem that chip is electrically conducted, yet, increase in layer encapsulation process because semi-conducting material is different with the thermal coefficient of expansion of taking between baseboard material in the bumpless formula, may cause the be full of cracks of wiring in the operation, therefore must additionally carry out the filler operation, fill the sealing resin to take at chip and its between the space between ground, this filler operation not only increases process, and because of process quality stability wayward, be easy to generate problem such as the glue that overflows and pollute chip, have a strong impact on the reliability of operation, moreover this sealing resin is the material different with the insulating barrier of follow-up storehouse circuit, not only expend operation and be easy to produce the problem of peeling off, in addition, when filler, be limited by the gap length between chip and ground, lead and the sealing resin is difficult for effectively being filled in this minim gap and residual air is arranged, in follow-up thermal cycle operation and reliability test process of carrying out the storehouse circuit, puffed rice phenomenon (Popcorn) very easily takes place, it is poor to cause the bumpless formula to increase layer packaging part quality stability, wayward, thereby can't be used widely.
Moreover, flourish along with electronic industry, electronic product also marches toward multi-functional, high performance R﹠D direction gradually.For satisfying the package requirements of semiconductor package part high integration (Integration) and microminiaturized (Miniaturization), the heat that semiconductor chip produces when operation will obviously increase, as the untimely effective loss of heat that semiconductor chip is produced, can seriously shorten the performance and the life-span of semiconductor chip; In addition, general semiconductor package part lacks effective screening effect (Shielding), will make it be subjected to external electromagnetic and interference of noise easily, has a strong impact on its operation function.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of chip buried in semiconductor encapsulation base plate structure and method for making thereof, the manufacturing of while integral chip support plate and the operation of semiconductor packaging, for client provides bigger demand elasticity, can simplify semiconductor industry operation and integration of interface problem simultaneously.
Another object of the present invention is to provide a kind of chip buried in semiconductor encapsulation base plate structure and method for making thereof, effectively the heat of loss semiconductor chip generation when operation.
A further object of the present invention is to provide a kind of chip buried in semiconductor encapsulation base plate structure and method for making thereof, avoid existing chip and its to take in filler operation in the encapsulation process between ground and cause excessive glue, effective problem such as filling, effectively promote the quality of production and product reliability.
A further object of the present invention is to provide a kind of chip buried in semiconductor encapsulation base plate structure and method for making thereof, as fixing semiconductor chip and as the material of patterned circuit operation, can save material, reduction manufacturing cost by insulating barrier.
For reaching above-mentioned and other purpose, the invention provides a kind of method for making of chip buried in semiconductor encapsulation base plate structure, the method for making of this chip buried in semiconductor encapsulation base plate structure comprises: at the layer on surface of metal insulating barrier of adhering, and this insulating barrier is formed with at least one opening, exposes outside the metal level that is covered under it; At least one semiconductor chip with a plurality of electronic padses is connect on the metal level of putting in exposing outside this insulating barrier opening; One support plate connect put on this insulating barrier, and this support plate runs through opening to should the insulating barrier opening part being formed with, this semiconductor chip is taken in wherein; Another insulating barrier of pressing on this semiconductor chip and this support plate, and make these insulating layer materials be filled in gap between this semiconductor chip and support plate; And carry out the patterned circuit operation, on the insulating barrier that covers this semiconductor chip and support plate, form line layer, and in this insulating barrier, form conductive structure, make this line layer be electrically connected to the electronic pads of this semiconductor chip by this conductive structure.
Via above-mentioned operation, chip buried in semiconductor encapsulation base plate structure of the present invention comprises: a metal level; One is provided with the insulating barrier of opening, is formed on this metal level; One is provided with the support plate of opening, connect and put on this insulating barrier, and this support plate aperture position is corresponding to this insulating barrier aperture position; At least one semiconductor chip with a plurality of electronic padses, connect put on this metal level and be accommodated in this insulating barrier and the support plate opening in; Another insulating barrier is pressed together on this support plate and the semiconductor chip, and makes this insulating layer material be filled in the gap of chip and support plate formation; And at least one line layer, be formed on this surface of insulating layer, and this line layer can be electrically connected to the electronic pads of this semiconductor chip by many conductive structures.
The present invention can be by integrating this metal level, semiconductor chip and line construction, simultaneously in conjunction with the manufacturing of chip bearing member and the operation of semiconductor packaging, for client provides big demand elasticity and simplifies semiconductor industry operation and interface coordination problem, and the present invention connects semiconductor chip to put on metal level, can be chip good heat radiation and ELECTROMAGNETIC OBSCURANT effect (Shielding) is provided, moreover, the present invention does not use tin lead (Sn-Pb) material to electrically connect in a large number, can save material cost and avoid environmental issue to produce, and be directly on chip, to form copper wire to provide and be electrically conducted and extend among the present invention, shorten electrical connection path and make the piece electrical performance effectively to bring into play.Be on this metal level, to connect earlier to put not completely crued insulating barrier and a semiconductor chip among the present invention simultaneously, connect thereon again and put the hot pressing that adds that a default opening is taken in the support plate of chip and carried out another insulating barrier, make the employed insulating layer material of this priority can be filled in gap between this chip and support plate, effectively semiconductor chip is anchored in the support plate opening, this insulating barrier also can act as the follow-up required material of circuit operation that carries out simultaneously simultaneously, save material, reduce manufacturing cost, avoid the sealing operation excessive glue pollution chip etc. in the existing semiconductor packages operation to have a strong impact on the operation reliability problems simultaneously, and the generation puffed rice phenomenon (Popcorn) in follow-up thermal cycle operation of carrying out the storehouse circuit that is caused when avoiding the sealing resin to be difficult for effectively being filled in chip and support plate gap etc. have a strong impact on the problem of process stability.
Description of drawings
Fig. 1 is the existing cross section view that covers geode grid array (FCBGA) semiconductor package part;
Fig. 2 A to Fig. 2 J is the generalized section of chip buried in semiconductor encapsulation base plate structure method for making of the present invention.
Embodiment
Embodiment
See also Fig. 2 A to Fig. 2 J figure, it is the generalized section of chip buried in semiconductor encapsulation base plate structure method for making of the present invention.
Shown in Fig. 2 A, at first provide a metal level 20, and at a surface adhering one insulating barrier 21 of this metal level, and this insulating barrier 21 is formed with at least one opening 210, expose outside the part metals layer 20 that covers under it.This metal level 20 can for example be to be made by Copper Foil.The material of this insulating barrier 21 can be selected from PI (Polyimide), PTFE (polytetrafluoroethylene-polytetrafluoroethylene), ABF, Bismaleimide Triazine (BT, Bismaleimide triazine), FR5 resin or organic resin be mixed with composite material of Filler etc., and this insulating barrier 21 connects and puts on this metal level 20 not baking hardening of fashion.
Shown in Fig. 2 B,, connect on the metal level of putting in exposing outside this insulating barrier opening 210 20 by a thermal conductivity adhesion coating 23 with the non-start face 22b of semiconductor chip 22 at least.The start face 22a of this semiconductor chip 22 has a plurality of electronic padses 220.Wherein this semiconductor chip 22 is can be by the heat radiation approach (Thermally conductive path) of this thermal conductivity adhesion coating 23 with these metal level 20 formations, directly this semiconductor chip 22 of loss moves the heat that is produced, and can provide ELECTROMAGNETIC OBSCURANT (Shielding) effect by this metal level 20.
Shown in Fig. 2 C, connect on these insulating barrier 21 surfaces and to put a support plate 24, and 24 pairs of this support plates should form the opening 240 that runs through its upper and lower surface in insulating barrier opening 210 places, this semiconductor chip 22 is taken in wherein, the opening 240 of this support plate 24 is preferably insulating barrier 21 openings 210 that place on this metal level 20 greater than connecing, this support plate 24 connect put in 21 layers of this insulation, so that effectively be filled in the gap of 24 of this chip 22 and support plates in follow-up insulating barrier 21 parts by this.Another insulating barrier 21a is provided simultaneously, the material of this insulating barrier 21a is to be selected from PI (Polyimide), PTFE (polytetrafluoroethylene-polytetrafluoroethylene), ABF, Bismaleimide Triazine (BT, Bismaleimide triazine), FR5 resin or organic resin be mixed with the composite material of Filler, its material can be equal to or be different from and before connects the insulating barrier of putting on this metal level 20 21.This support plate 24 can be a metallic plate, insulation board or circuit board.This metallic plate can be a metallic copper material; This insulation board can for example be that epoxy resin (Epoxy resin), polyimides (Polyimide), cyanate ester (Cyanate ester), glass fibre (Glass fiber), Bismaleimide Triazine (BT, Bismaleimide triazine) or materials such as combined fiberglass and epoxy resin constitute; This circuit board can be the circuit board with line layer of finishing pre-treatment.
Shown in Fig. 2 D, then, heat pressing working procedure, this insulating barrier 21a is pressed together on this support plate 24 and this semiconductor chip 22 upper surfaces, the insulating barrier 21a that is pressed together on this support plate 24 and the chip 22 is flowed be filled in the gap of 24 of this semiconductor chip 22 and support plates, so as to forming the coated insulation layer 21b of complete this chip of covering.
Shown in Fig. 2 E, form a plurality of perforates 211 (for example utilizing laser drill or modes such as exposure, development) on the surface of this coated insulation layer 21b, manifest the electronic pads 220 of this chip 22.
Shown in Fig. 2 F, this coated insulation layer 21b with and expose outside and form a conductive layer 25 on the electronic pads 220 on these perforate 211 surfaces, and on this conductive layer 25, form a resistance layer 26, and make this resistance layer 26 be formed with a plurality of openings 260, expose outside the partially conductive layer 25 that covers under it, and the opening 260 of this resistance layer 26 of part is the perforates 211 corresponding to this coated insulation layer 21b.This conductive layer 25 can be made of metal or conducting polymer composite mainly as the follow-up required current conduction path of electroplated metal layer of carrying out.
Shown in Fig. 2 G, then, carry out electroplating work procedure, be formed with line layer 271 and conductive structure 272 on the conductive layer 25 in exposing outside this resistance layer opening 260, make this line layer 271 on this insulating barrier 21b can be by being formed on the conductive structure 272 among this insulating barrier 21b, be electrically connected to the electronic pads 220 of this chip 22, just provide this semiconductor chip 22 can outwards do electrical extension whereby.Wherein, it should be noted, if this support plate 24 can act as an earthing member when being metal material, or this support plate 24 is when being preset with the circuit board of circuit, when carrying out above-mentioned patterned circuit operation, can provide line layer 271 to be electrically connected to this support plate 24 simultaneously, make semiconductor device have better electrical functionality by many conductive structures (not marking).Wherein this conductive structure 272 can be conductive blind hole or conductive projection etc.
Shown in Fig. 2 H, the partially conductive layer 25 that then removes this resistance layer 26 and covered.
Shown in Fig. 2 I, then, the also sustainable layer operation that increase of carrying out circuit forms circuit layer reinforced structure 28, and makes this circuit layer reinforced structure 28 can be electrically connected to the electronic pads 220 of this chip 22 on this semiconductor chip 22 and support plate 24.
Shown in Fig. 2 J, can form welding resisting layer 29 at the outer fringe surface of this circuit layer reinforced structure 28 afterwards, and make this welding resisting layer 29 be formed with a plurality of openings, expose outside this circuit layer reinforced structure 28 outer fringe surface parts, on these circuit layer reinforced structure 28 outer fringe surfaces, be formed with a plurality of conductive components 30, for example soldered ball or conductive pole are electrically conducted for this conductor package substrate construction and external electronic.
Mainly draw together by the chip buried in semiconductor encapsulation base plate structure that the above-mentioned operation of the present invention makes: a metal level 20; One is provided with the insulating barrier 21 of opening 210, is formed on this metal level 20; One is provided with the support plate 24 of opening 240, connect and put on this insulating barrier 21, and these support plate 24 openings 240 positions is corresponding to these insulating barrier 21 openings 210 positions; At least one semiconductor chip 22 with many strip electrodes pad 220, connect put on this metal level 20 and be accommodated in this insulating barrier and support plate opening 210,240 in; Another insulating barrier 21a is pressed together on this support plate 24 and the semiconductor chip 22, and makes this insulating layer material 21a be filled in chip 22 and support plate 24 formed clearance electrode pad openings; And at least one line layer 271, be formed on this insulating barrier 21a, and this line layer 271 can be by many conductive structures 272 that are formed among this coated insulation layer 21a, be electrically connected to the electronic pads 220 of this semiconductor chip 22, and can form circuit layer reinforced structure 28, and, this chip 22 is electrically conducted with external electronic by a plurality of conductive components 30.
Therefore, chip buried in semiconductor encapsulation base plate structure of the present invention and method for making thereof can be by integrating this metal level, semiconductor chip and line construction, simultaneously in conjunction with the manufacturing of chip bearing member and the operation of semiconductor packaging, for client provides big demand elasticity and simplifies semiconductor process and interface coordination problem, and the present invention connects semiconductor chip to put on metal level, for chip provides good heat radiation and ELECTROMAGNETIC OBSCURANT effect (Shielding), moreover, the present invention does not use tin lead (Sn-Pb) material to electrically connect in a large number, so can save material cost and avoid environmental issue to produce, and be directly on chip, to form copper wire to provide and be electrically conducted and extend among the present invention, shorten electrical connection path and made the piece electrical performance be able to effective performance.The present invention simultaneously connects earlier to put uncured first insulating barrier and a semiconductor chip on this metal level, connect thereon again and put a default opening with the support plate of taking in chip and the hot pressing that adds that carries out second insulating barrier, this first and second insulating layer material can effectively be filled in the gap between this chip and support plate opening, effectively semiconductor chip is anchored in the support plate opening, this insulating barrier also can act as the follow-up required material of circuit operation that carries out simultaneously simultaneously, can save material and reduce manufacturing cost, avoid simultaneously causing in the sealing operation in the existing semiconductor packages operation and overflow glue and pollute chip etc. and have a strong impact on the operation reliability problems, and when having avoided the sealing resin to be difficult for effectively being filled in chip and support plate gap, the generation puffed rice phenomenon (Popcorn) in follow-up thermal cycle operation of carrying out the storehouse circuit that is caused etc. has a strong impact on the problem of process stability.
Claims (19)
1. the method for making of a chip buried in semiconductor encapsulation base plate structure is characterized in that, the method for making of this chip buried in semiconductor encapsulation base plate structure comprises:
At the layer on surface of metal insulating barrier of adhering, and this insulating barrier is formed with at least one opening, exposes outside the metal level that is covered under it;
At least one semiconductor chip with a plurality of electronic padses is connect on the metal level of putting in exposing outside this insulating barrier opening;
One support plate connect put on this insulating barrier, and this support plate runs through opening to should the insulating barrier opening part being formed with, this semiconductor chip is taken in wherein;
Another insulating barrier of pressing on this semiconductor chip and this support plate, and make these insulating layer materials be filled in gap between this semiconductor chip and support plate; And
Carry out the patterned circuit operation, on the insulating barrier that covers this semiconductor chip and support plate, form line layer, and in this insulating barrier, form conductive structure, make this line layer be electrically connected to the electronic pads of this semiconductor chip by this conductive structure.
2. the method for making of chip buried in semiconductor encapsulation base plate structure as claimed in claim 1 is characterized in that, the method for making of this chip buried in semiconductor encapsulation base plate structure comprises that also carrying out circuit increases a layer operation, forms the circuit layer reinforced structure on this line layer and insulating barrier.
3. the method for making of chip buried in semiconductor encapsulation base plate structure as claimed in claim 2, it is characterized in that, the method for making of this chip buried in semiconductor encapsulation base plate structure also is included in this circuit layer reinforced structure outer fringe surface conductive component is set, and is electrically conducted for this chip and external electronic.
4. the method for making of chip buried in semiconductor encapsulation base plate structure as claimed in claim 1 is characterized in that, this patterned circuit operation comprises:
In this insulating barrier, form perforate, expose outside the electronic pads of this chip;
At this insulating barrier and expose outside and form a conductive layer on the electronic pads of this open surfaces;
On this conductive layer, form resistance layer, and make this resistance layer form a plurality of openings, expose outside the partially conductive layer that covers under it;
Carry out electroplating work procedure, form line layer and conductive structure on the conductive layer in exposing outside this resistance layer opening, make this line layer on this insulating barrier can be by being formed on the electronic pads that conductive structure in this insulating barrier is electrically connected to this chip; And
The conductive layer that removes this resistance layer and covered.
5. the method for making of chip buried in semiconductor encapsulation base plate structure as claimed in claim 4 is characterized in that, this conductive layer is made of metal or conducting polymer composite.
6. the method for making of chip buried in semiconductor encapsulation base plate structure as claimed in claim 1 is characterized in that, this conductive structure is conductive blind hole or conductive projection.
7. the method for making of chip buried in semiconductor encapsulation base plate structure as claimed in claim 1 is characterized in that, this insulating barrier connects puts the incomplete baking hardening of fashion on this metal level.
8. the method for making of chip buried in semiconductor encapsulation base plate structure as claimed in claim 1 is characterized in that, this metal level is a Copper Foil.
9. the method for making of chip buried in semiconductor encapsulation base plate structure as claimed in claim 1 is characterized in that, this semiconductor chip is to connect by a heat conduction adhesion coating to put on this metal level.
10. the method for making of chip buried in semiconductor encapsulation base plate structure as claimed in claim 1 is characterized in that, this support plate is in circuit board, insulation board or the metallic plate.
11. the method for making of chip buried in semiconductor encapsulation base plate structure as claimed in claim 1 is characterized in that, this line layer can be electrically conducted support plate by conductive structure.
12. a chip buried in semiconductor encapsulation base plate structure is characterized in that, this chip buried in semiconductor encapsulation base plate structure comprises:
One metal level;
One is provided with the insulating barrier of opening, is formed on this metal level;
One is provided with the support plate of opening, connect and put on this insulating barrier, and this support plate aperture position is corresponding to this insulating barrier aperture position;
At least one semiconductor chip with a plurality of electronic padses, connect put on this metal level and be accommodated in this insulating barrier and the support plate opening in;
Another insulating barrier is pressed together on this support plate and the semiconductor chip, and makes this insulating layer material be filled in the gap of chip and support plate formation; And
At least one line layer is formed on this surface of insulating layer, and this line layer can be electrically connected to the electronic pads of this semiconductor chip by many conductive structures.
13. chip buried in semiconductor encapsulation base plate structure as claimed in claim 12 is characterized in that, this chip buried in semiconductor encapsulation base plate structure also comprises at least one circuit layer reinforced structure that is formed on this insulating barrier and the line layer.
14. chip buried in semiconductor encapsulation base plate structure as claimed in claim 13 is characterized in that, this chip buried in semiconductor encapsulation base plate structure also comprises a plurality of conductive components that are formed on the outer surface of this circuit layer reinforced structure.
15. chip buried in semiconductor encapsulation base plate structure as claimed in claim 12 is characterized in that, this metal level is a Copper Foil.
16. chip buried in semiconductor encapsulation base plate structure as claimed in claim 12 is characterized in that, this semiconductor chip is to connect by a thermal conductivity adhesion coating to put on this metal level and be accommodated in the opening of this support plate.
17. chip buried in semiconductor encapsulation base plate structure as claimed in claim 12 is characterized in that, this support plate is in circuit board, insulation board or the metal.
18. chip buried in semiconductor encapsulation base plate structure as claimed in claim 12 is characterized in that, this conductive structure is conductive blind hole or conductive projection.
19. chip buried in semiconductor encapsulation base plate structure as claimed in claim 12 is characterized in that, this line layer can be electrically conducted support plate by conductive structure.
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| CN200510123394A CN100576476C (en) | 2005-11-25 | 2005-11-25 | Chip buried in semiconductor encapsulation base plate structure and method for making thereof |
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| CN200510123394A CN100576476C (en) | 2005-11-25 | 2005-11-25 | Chip buried in semiconductor encapsulation base plate structure and method for making thereof |
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| CN1971862A true CN1971862A (en) | 2007-05-30 |
| CN100576476C CN100576476C (en) | 2009-12-30 |
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