CN111681966B - Ultrathin welding stack packaging method - Google Patents
Ultrathin welding stack packaging method Download PDFInfo
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- CN111681966B CN111681966B CN202010590382.3A CN202010590382A CN111681966B CN 111681966 B CN111681966 B CN 111681966B CN 202010590382 A CN202010590382 A CN 202010590382A CN 111681966 B CN111681966 B CN 111681966B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the layer connector during or after the bonding process
Abstract
The invention discloses an ultrathin welding stack packaging method, which comprises the following steps: a, manufacturing a groove on the surface of a silicon adapter plate, embedding chips with different thicknesses and different types in the groove, enabling a PAD (PAD application area) interconnection surface of each chip to be downward, and pouring glue on the back surface of the adapter plate to fill gaps between the chips and the groove; b, thinning one surface of a groove of the adapter plate to enable the thickness of the chip to be consistent, thinning the other surface of the adapter plate, etching silicon on the other surface to enable the PAD to be exposed through the groove, and obtaining RDL interconnected with the PAD through an electroplating process; stacking a plurality of layers of thinned adapter plates through a pasting process, exposing the interconnection RDL pads of each layer through a dry etching process, depositing a passivation layer, opening metal at the bottoms of the pads, performing seed layer deposition, and electroplating metal to obtain interconnection RDLs; and D, implanting solder balls on the surface of the RDL to obtain a multi-layer stacked ultrathin packaging structure.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an ultrathin welding, stacking and packaging method.
Background
With the development of three-dimensional packaging technology, the multilayer stack packaging technology is widely applied, from a flash Memory chip process at the beginning to a Dynamic Random Access Memory (DRAM) at the later stage, so that a CMOS Image Sensor (CMOS Image Sensor) at the later stage is also made by adopting a BSI STACKED process, and the product has greatly improved volume, weight and performance.
However, the multilayer stacked chips need to be stacked by using the wafers with the same size, the yield is difficult to control, the technical difficulty of multilayer stacking needs to be considered during chip design, the difficulty is high for both a design company and a wafer manufacturing company, and the thickness of the stacked wafers is large, so that the requirement that the terminals are thinner and thinner at present is not met.
Disclosure of Invention
The invention aims to provide an ultrathin welding stack packaging method.
In order to solve the technical problems, the invention adopts the following technical scheme:
an ultra-thin solder stack package method, comprising the steps of:
a, manufacturing a groove on the surface of a silicon adapter plate, embedding chips with different thicknesses and different types in the groove, enabling a PAD (PAD application area) interconnection surface of each chip to be downward, and pouring glue on the back surface of the adapter plate to fill gaps between the chips and the groove;
b, thinning one surface of a groove of the adapter plate to enable the thickness of the chip to be consistent, thinning the other surface of the adapter plate, etching silicon on the other surface to enable the PAD to be exposed through the groove, and obtaining RDL interconnected with the PAD through an electroplating process;
stacking a plurality of layers of thinned adapter plates through a pasting process, exposing the interconnection RDL pads of each layer through a dry etching process, depositing a passivation layer, opening metal at the bottoms of the pads, performing seed layer deposition, and electroplating metal to obtain interconnection RDLs;
and D, implanting solder balls on the surface of the RDL to obtain a multi-layer stacked ultrathin packaging structure.
Preferably, the step a specifically includes:
etching a cavity on the silicon adapter plate by photoetching and etching processes, and performing wet etching on the cavity with a special appearance; the depth of the cavity ranges from 100nm to 700um, and the shapes include square, round, oval and triangular, and the side of the cavity is vertical to the wall or is provided with a slope;
chips with different thicknesses are embedded into the groove in an adhesive mode, the PAD interconnection surface of the chip faces downwards, and the colloid is filled into the groove to fill the gaps between the chip and the groove.
Preferably, the chip is a qualified chip.
Preferably, the step B specifically includes:
thinning one surface of the groove of the adapter plate to enable the thickness of the chip to be consistent, then thinning the other surface of the adapter plate, and manufacturing a groove on the other surface to enable the PAD of the chip to be exposed;
and depositing a passivation layer on one surface of the wafer with the groove, etching the passivation layer to expose the PAD, and manufacturing the RDL through photoetching and electroplating processes to lead out the electrical property of the PAD in the groove.
Preferably, in step C, the number of stacked interposer layers is greater than 3.
The invention has the following beneficial effects: the chips which are tested are rearranged and embedded into the adapter plate dug with the cavity, so that the yield problem of the chips is avoided, the adapter plate module is integrally thinned, and the purpose of reducing the thickness of the multilayer stacking module is achieved.
Drawings
Fig. 1a is a schematic structural diagram of a cavity etched in a silicon interposer by an ultra-thin solder stack packaging method according to an embodiment of the present invention;
fig. 1b is a schematic structural diagram of a thinned interposer of the ultra-thin solder stack package method according to the embodiment of the present invention;
fig. 1c is a schematic diagram of a stacked structure of an interposer in an ultra-thin solder stack package method according to an embodiment of the invention;
FIG. 1d is a schematic structural diagram of an interconnection RDL obtained by electroplating metal in the ultra-thin solder stack package method according to the embodiment of the present invention;
fig. 1e shows an ultra-thin package structure with multiple stacked layers obtained by implanting solder balls on the surface of the RDL in the ultra-thin solder stack packaging method according to the embodiment of the invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the accompanying drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.
Moreover, repeated reference numerals or designations may be used in various embodiments. These iterations are merely for simplicity and clarity of describing the present invention, and are not intended to represent any correlation between the various embodiments and/or structures discussed.
Reference numerals in the various embodiments of the invention with respect to steps are merely for convenience of description and are not necessarily associated in a substantially sequential manner. Different steps in each embodiment can be combined in different sequences, so that the purpose of the invention is achieved.
The embodiment of the invention provides an ultrathin welding stack packaging method, which comprises the following steps:
a, manufacturing a groove on the surface of a silicon adapter plate, embedding chips with different thicknesses and different types in the groove, enabling a PAD (PAD application area) interconnection surface of each chip to be downward, and pouring glue on the back surface of the adapter plate to fill gaps between the chips and the groove;
as shown in fig. 1a, a cavity is etched in a silicon interposer 101 by photolithography and etching processes, and a wet etching method may be used for the cavity with a special morphology; the depth range of the cavity is between 100nm and 700um, the shape of the cavity can be square, round, oval, triangular and the like, and the side wall of the cavity can be vertical or inclined;
the chips 102 with different thicknesses are embedded into the grooves in a gluing mode 103, the PAD interconnection surfaces of the chips face downwards, the grooves are filled with glue 104, gaps between the chips and the grooves are filled, and the chips are qualified through testing.
B, thinning one surface of a groove of the adapter plate to enable the thickness of the chip to be consistent, thinning the other surface of the adapter plate, etching silicon on the other surface to enable the PAD to be exposed through the groove, and obtaining RDL interconnected with the PAD through an electroplating process;
as shown in fig. 1b, thinning one surface of the groove of the adapter plate to make the thickness of the chip consistent, then thinning the other surface of the adapter plate, and making a groove on the other surface to expose PAD of the chip;
and depositing a passivation layer on one surface of the wafer with the groove, etching the passivation layer to expose the PAD, and manufacturing the RDL105 through photoetching and electroplating processes to lead out the electrical property of the PAD in the groove.
Stacking a plurality of thinned adapter plates through a pasting process, exposing the interconnection RDL pads of all layers through a dry etching process, depositing a passivation layer, opening metal at the bottoms of the pads, depositing a seed layer, and electroplating metal to obtain interconnection RDLs;
as shown in fig. 1c, an adhesive layer 106 is disposed through a pasting process to stack a plurality of thinned interposer layers, wherein the number of stacked layers is greater than 3;
as shown in fig. 1d, each layer of interconnected RDL bonding pad is exposed through a dry etching process, a passivation layer is deposited, metal at the bottom of the bonding pad is opened, seed layer deposition is performed, and metal is electroplated to obtain an interconnected RDL 108.
D: planting solder balls on the surface of the RDL to obtain a multi-layer stacked ultrathin packaging structure;
as shown in fig. 1e, solder balls 109 are implanted on the surface of the RDL to obtain an ultra-thin package structure with multi-layer stacking.
According to the ultrathin welding stacking method, the chips which are tested are rearranged and embedded into the adapter plate with the dug cavity, so that the yield problem of the chips is avoided, the adapter plate module is integrally thinned, and the purpose of reducing the thickness of the multilayer stacking module is achieved.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present specification describes embodiments, not every embodiment includes only a single embodiment, and such description is for clarity purposes only, and it is to be understood that all embodiments may be combined as appropriate by one of ordinary skill in the art to form other embodiments as will be apparent to those of skill in the art from the description herein.
Claims (3)
1. An ultra-thin solder stack package method, comprising the steps of:
a, manufacturing a groove on the surface of a silicon adapter plate, embedding chips with different thicknesses and different types in the groove, enabling a PAD (PAD application area) interconnection surface of each chip to be downward, and pouring glue on the back surface of the adapter plate to fill gaps between the chips and the groove; the chip is qualified through testing;
b, thinning one surface of a groove of the adapter plate to enable the thickness of the chip to be consistent, then thinning the other surface of the adapter plate, etching silicon on the other surface to enable the PAD to be exposed through the groove, and obtaining an RDL interconnected with the PAD through an electroplating process;
stacking a plurality of layers of thinned adapter plates through a pasting process, exposing the interconnection RDL pads of each layer through a dry etching process, depositing a passivation layer, opening metal at the bottoms of the pads, performing seed layer deposition, and electroplating metal to obtain interconnection RDLs;
d, implanting solder balls on the surface of the RDL to obtain a multi-layer stacked ultrathin packaging structure;
the step A specifically comprises the following steps:
etching a cavity on the silicon adapter plate by photoetching and etching processes, and performing wet etching on the cavity with a special appearance; the depth of the cavity ranges from 100nm to 700um, and the shapes include square, round, oval and triangular, and the side of the cavity is vertical to the wall or is provided with a slope;
the chips with different thicknesses are embedded into the groove in an adhesive mode, the PAD interconnection surface of the chip faces downwards, and the groove is filled with the colloid so that gaps between the chip and the groove are filled.
2. The ultra-thin solder stack package method of claim 1, wherein the step B specifically includes:
thinning one surface of the groove of the adapter plate to enable the thickness of the chip to be consistent, then thinning the other surface of the adapter plate, and manufacturing a groove on the other surface to expose PAD of the chip;
and depositing a passivation layer on one surface of the wafer with the groove, etching the passivation layer to expose the PAD, and manufacturing the RDL through photoetching and electroplating processes to lead out the electrical property of the PAD in the groove.
3. The ultra-thin solder stack package method of claim 1, wherein in step C, the number of interposer stack layers is greater than 3.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2020101288774 | 2020-02-28 | ||
| CN202010128877 | 2020-02-28 |
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| CN111681966A CN111681966A (en) | 2020-09-18 |
| CN111681966B true CN111681966B (en) | 2022-07-22 |
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| CN113066780B (en) * | 2021-03-23 | 2023-07-25 | 浙江集迈科微电子有限公司 | Interposer stacking module, multi-layer module and stacking process |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1893053A (en) * | 2005-07-08 | 2007-01-10 | 三星电子株式会社 | Chip-embedded interposer structure and fabrication method thereof, wafer level stack structure and resultant package structure |
| WO2013037102A1 (en) * | 2011-09-13 | 2013-03-21 | 深南电路有限公司 | Encapsulation method for embedding chip into substrate and structure thereof |
| CN105845643A (en) * | 2016-06-12 | 2016-08-10 | 华天科技（昆山）电子有限公司 | Packaging structure for chip embedded into silicon substrate and manufacturing method of packaging structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100565795C (en) * | 2006-01-26 | 2009-12-02 | 财团法人工业技术研究院 | The manufacture method of store charge element |
| CN100539126C (en) * | 2007-05-18 | 2009-09-09 | 日月光半导体制造股份有限公司 | Chip stack structure and the chip architecture that can be made into chip stack structure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1893053A (en) * | 2005-07-08 | 2007-01-10 | 三星电子株式会社 | Chip-embedded interposer structure and fabrication method thereof, wafer level stack structure and resultant package structure |
| WO2013037102A1 (en) * | 2011-09-13 | 2013-03-21 | 深南电路有限公司 | Encapsulation method for embedding chip into substrate and structure thereof |
| CN105845643A (en) * | 2016-06-12 | 2016-08-10 | 华天科技（昆山）电子有限公司 | Packaging structure for chip embedded into silicon substrate and manufacturing method of packaging structure |
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