CN113066780B - Interposer stacking module, multi-layer module and stacking process - Google Patents

Interposer stacking module, multi-layer module and stacking process Download PDF

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CN113066780B
CN113066780B CN202110307903.4A CN202110307903A CN113066780B CN 113066780 B CN113066780 B CN 113066780B CN 202110307903 A CN202110307903 A CN 202110307903A CN 113066780 B CN113066780 B CN 113066780B
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adapter plate
base
base wafer
cavity
wafer
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CN113066780A (en
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冯光建
黄雷
高群
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Zhejiang Jimaike Microelectronics Co Ltd
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Zhejiang Jimaike Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

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Abstract

The invention provides an adapter plate stacking module which comprises a base adapter plate and a cap adapter plate; the first surface of the base adapter plate is provided with an RDL and a bonding pad; a cavity is formed in the second surface of the base adapter plate, RDL and a bonding pad are arranged on the second surface of the base adapter plate, and the bonding pad is arranged at the bottom of the cavity of the base adapter plate; the chip is arranged in the cavity of the base adapter plate; the working surface of the chip is electrically connected with the RDL on the second surface of the base adapter plate; the RDL on the second surface of the base adapter plate is connected with a bonding pad arranged on the side surface of the base adapter plate; the first surface of the cap adapter plate is provided with a cavity corresponding to the cavity of the base adapter plate, and the side surface of the cap adapter plate is provided with a bonding pad; the cap adapter plate and the base adapter plate are in alignment bonding stacking; the side bonding pad of the cap adapter plate is connected with the side bonding pad of the base adapter plate through a conductive wire. The structure and the process can manufacture the adapter plate with larger thickness and bear the chip with larger thickness.

Description

Interposer stacking module, multi-layer module and stacking process
Technical Field
The invention relates to the technical field of semiconductors, in particular to a stacking mode of adapter plates.
Background
Millimeter wave radio frequency technology has rapidly developed in the semiconductor industry, and for wireless transmitting and receiving systems, it is not possible to integrate the same chip (SOC) at present, so that different chips including radio frequency units, filters, power amplifiers, etc. need to be integrated into a separate system to realize the functions of transmitting and receiving signals.
However, the rf module often needs to attach components with different materials and different thicknesses to an interposer, and some components need to be re-wired and interconnected, and some components need to be interconnected by using solder balls at the bottom, so that the space of the components is increased. And the radio frequency module is sealed with the upper cover plate, and the chip with larger thickness needs to be manufactured with a deeper cavity on the upper cover plate, so that the thickness of the upper cover plate is increased, if the upper cover plate is also required to be connected with the top of the upper cover plate through TSVs, the upper cover plate cannot be too thick due to limited manufacturing process capacity of the TSVs, and the cavity of the upper cover plate and the TSVs cannot be too deep, so that the chip usability of the whole module is affected.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides an adapter plate stacking module, a multi-layer module and a stacking process, which can manufacture an adapter plate with larger thickness and bear chips with larger thickness. In order to achieve the technical purpose, the invention adopts the following technical scheme:
in a first aspect, an embodiment of the present invention provides an interposer stack module, including a base interposer and a cap interposer;
the first surface of the base adapter plate is provided with an RDL and a bonding pad; the second surface of the base adapter plate is provided with a cavity, the second surface of the base adapter plate is provided with an RDL and a bonding pad, and the bottom of the cavity of the base adapter plate is provided with the bonding pad; the chip is arranged in the cavity of the base adapter plate, and the back surface of the chip is connected with a grounding line in the RDL of the first surface of the base adapter plate through a bonding pad at the bottom of the cavity and a TSV conductive column in the base adapter plate; the working surface of the chip is electrically connected with the RDL on the second surface of the base adapter plate; the RDL on the second surface of the base adapter plate is connected with a bonding pad arranged on the side surface of the base adapter plate;
the first surface of the cap adapter plate is provided with a cavity corresponding to the cavity of the base adapter plate, and the side surface of the cap adapter plate is provided with a bonding pad;
the cap adapter plate and the base adapter plate are in alignment bonding stacking; the side bonding pad of the cap adapter plate is connected with the side bonding pad of the base adapter plate through a conductive wire.
Further, the bonding pads on the side surface of the base adapter plate extend downwards from the second surface of the base adapter plate; pads on the sides of the cap interposer extend downward from the second surface thereof.
Further, a filler is arranged around the chip in the cavity of the base adapter plate.
In a second aspect, embodiments of the present invention provide an interposer stack multilayer module, comprising two or more interposer stack modules as described above;
each adapter plate stacking module is stacked up and down to form an adapter plate stacking multi-layer module; and the side pads of the base adapter plate in the upper module and the side pads of the cover cap adapter plate in the lower module are connected through conductive wires between the two adjacent adapter plate stacking modules.
In a third aspect, an embodiment of the present invention further provides an interposer stacking process, including the steps of:
step S1, manufacturing a TSV conductive column on the first surface of a base wafer, and manufacturing an RDL and a bonding pad which are connected with one end of the TSV conductive column on the first surface of the base wafer;
step S2, a carrier is temporarily bonded on the first surface of the base wafer, the second surface of the base wafer is thinned, and then a groove conductive column for forming a side surface bonding pad is manufactured;
step S3, etching a cavity in a region corresponding to the TSV conductive column on the second surface of the base wafer, and then depositing a metal bonding pad connected with the other end of the TSV conductive column at the bottom of the cavity;
s4, mounting a chip on the bottom of the cavity of the base wafer, wherein the back surface of the chip is connected with a grounding circuit in the RDL of the first surface of the base wafer through a bonding pad at the bottom of the cavity of the base wafer and a TSV conductive column in the base wafer; filling filler in the gap between the chip and the cavity; manufacturing an RDL and a bonding pad on the second surface of the base wafer, so that the working surface of the chip is electrically connected with the RDL on the second surface of the base wafer;
step S5, manufacturing a cavity corresponding to the cavity of the base wafer on the first surface of the cap wafer, and then manufacturing a groove conductive column for forming a side surface bonding pad on the second surface of the cap wafer;
s6, cutting the base wafer and the cap wafer respectively to form a base adapter plate and a cap adapter plate, cutting the groove conductive column of the base wafer to form a side surface bonding pad of the base adapter plate, and cutting the groove conductive column of the cap wafer to form a side surface bonding pad of the cap adapter plate;
s7, aligning, bonding and stacking the cap adapter plate and the base adapter plate to form an adapter plate stacking module;
step S8, two or more adapter plate stacking modules are stacked up and down to form an adapter plate stacking multi-layer module; and then, manufacturing conductive wires on the side surfaces of the multi-layer modules, so that the side surface bonding pads of the cover cap adapter plates of the single adapter plate stacking module are connected with the side surface bonding pads of the base adapter plates through the conductive wires, and the side surface bonding pads of the base adapter plates in the previous module are connected with the side surface bonding pads of the cover cap adapter plates in the next module through the conductive wires between the upper and lower adjacent adapter plate stacking modules.
Further, the step S1 specifically includes:
manufacturing a first TSV hole on the first surface of the base wafer through photoetching and etching processes;
then, a passivation layer is manufactured on the first surface of the base wafer, and then a seed layer is manufactured on the passivation layer;
electroplating copper on the first surface of the base wafer to enable copper metal to be filled in the first TSV hole, and enabling copper to be more compact at the temperature of 200-500 ℃ to form TSV conductive columns in the base wafer;
copper CMP process removes copper from the first surface of the base wafer, leaving copper filled in the first TSV hole;
depositing a seed layer on the first surface of the base wafer, manufacturing an RDL and a bonding pad on the first surface of the base wafer through photoetching and electroplating processes, and then removing the photoresist and the seed layer;
the step S2 specifically comprises the following steps:
temporarily bonding the slide glass with the first surface of the base wafer through a temporary bonding process, and thinning the second surface of the base wafer by taking the slide glass as a support; then making a side bonding pad groove on the second surface of the thinned base wafer through photoetching and dry etching processes;
then, a passivation layer is manufactured on the second surface of the base wafer, a seed layer is manufactured on the passivation layer, copper is electroplated, copper metal is fully filled in the grooves of the side welding disk, copper is densified at the temperature of 200-500 ℃ to be more compact, and groove conductive columns in the base wafer are formed;
the copper CMP process removes copper from the second surface of the base wafer, leaving copper filled in the side pad grooves.
Further, the step S3 specifically includes:
continuing to etch the cavity on the second surface of the base wafer through photoetching and dry etching processes, wherein the area where the cavity is located corresponds to the TSV conductive column in the base wafer;
dry etching the cavity of the base wafer to expose the other end of the TSV conductive column of the base wafer and the remaining wafer material above the TSV conductive column; depositing a passivation layer on the second surface of the base wafer, and exposing the metal at the other end of the TSV conductive column through photoetching and dry etching; depositing a seed layer, and then depositing a metal bonding pad at the bottom of the cavity of the base wafer; the photoresist and seed layer are then removed.
Further, in step S8, the manufacturing of the conductive wire on the side of the multi-layer module specifically includes:
planting solder balls on the bonding pads on the side surfaces of the multi-layer module stacked by the adapter plate, and then punching metal wires below the solder balls; reflow then causes the solder balls to fuse with the underlying wires to form conductive lines.
Or, in step S8, the manufacturing the conductive wire on the side of the multi-layer module specifically includes:
solder balls are planted on the bonding pads on the side surfaces of the multi-layer module stacked by the adapter plate, and two adjacent solder balls are connected together through fusion by reflow soldering to form a conductive wire.
The invention has the advantages that: the bottom of the cavity is interconnected by using TSVs with smaller depth in the base adapter plate, then the inner chips of the cavity are electrically led out through the RDL at the top of the base adapter plate, the adapter plates are communicated up and down without manufacturing deep TSVs, and the adapter plates are interconnected by using solder balls or a wire bonding mode; therefore, the adapter plate with larger thickness can be manufactured, and the chip with larger thickness is borne, and because the conducting wires on the side face of the adapter plate are interconnected, the trouble that the TSV cannot be too deep is avoided.
Drawings
Fig. 1a is a schematic view illustrating a first TSV hole formed in a first surface of a base wafer according to an embodiment of the present invention.
Fig. 1b is a schematic diagram of an RDL and a pad connected to one end of a TSV conductive post fabricated on a first surface of a base wafer according to an embodiment of the present invention.
Fig. 1c is a schematic diagram illustrating a side pad groove fabricated on a second surface of a base wafer according to an embodiment of the present invention.
FIG. 1d is a schematic diagram of a conductive pillar forming a recess in a base wafer according to an embodiment of the present invention.
FIG. 1e is a schematic illustration of etching a cavity in a second surface of a base wafer and fabricating a metal pad at the bottom of the cavity in an embodiment of the present invention.
Fig. 1f is a schematic diagram of die attach at the bottom of a cavity of a base wafer and RDL and bonding pads fabricated on a second surface of the base wafer according to an embodiment of the present invention.
Fig. 1g is a schematic diagram of alignment bonding stacking of a cap wafer and a cap interposer and a base interposer after dicing in an embodiment of the present invention.
Fig. 1h is a schematic diagram of stacking two interposer stacking modules up and down in an embodiment of the present invention.
Fig. 1i is a schematic diagram illustrating a solder ball implanted on a side of a stacked multi-layer module of an interposer in an embodiment of the present invention.
Fig. 1j is a schematic diagram of a side routing of a stacked multi-layer module of an interposer in an embodiment of the present invention.
Fig. 1k is a schematic diagram showing the fusion of solder balls and wires under the solder balls by reflow soldering on the side of the interposer stack multilayer module in an embodiment of the invention.
Fig. 1l is a schematic diagram illustrating a method for implanting larger solder balls on a side of a stacked multi-layer module of an interposer in an embodiment of the invention.
Fig. 1m is a schematic diagram illustrating a case where two solder balls adjacent to each other are connected by fusion by reflow soldering on the side surface of the interposer stack multi-layer module in an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In an embodiment of the present invention, a lower surface of the wafer or the interposer is defined as a first surface, and an upper surface of the wafer or the interposer is defined as a second surface; RDL refers to a rewiring layer;
the first embodiment of the invention provides an adapter plate stacking module, as shown in fig. 1g, comprising a base adapter plate and a cap adapter plate;
the first surface of the base adapter plate is provided with an RDL and a bonding pad; the second surface of the base adapter plate is provided with a cavity, the second surface of the base adapter plate is provided with an RDL and a bonding pad, and the bottom of the cavity of the base adapter plate is provided with the bonding pad; the chip is arranged in the cavity of the base adapter plate, and the back surface of the chip is connected with a grounding line in the RDL of the first surface of the base adapter plate through a bonding pad at the bottom of the cavity and a TSV conductive column in the base adapter plate; the working surface of the chip is electrically connected with the RDL on the second surface of the base adapter plate; the RDL on the second surface of the base adapter plate is connected with a bonding pad arranged on the side surface of the base adapter plate;
the first surface of the cap adapter plate is provided with a cavity corresponding to the cavity of the base adapter plate, and the side surface of the cap adapter plate is provided with a bonding pad;
the cap adapter plate and the base adapter plate are in alignment bonding stacking; the side bonding pad of the cap adapter plate is connected with the side bonding pad of the base adapter plate through a conductive wire.
Further, the bonding pads on the side surface of the base adapter plate extend downwards from the second surface of the base adapter plate; pads on the sides of the cap interposer extend downward from the second surface thereof. Further, a filler is arranged around the chip in the cavity of the base adapter plate.
The second embodiment of the present invention provides an interposer stack multi-layer module, including two or more interposer stack modules as described above;
each adapter plate stacking module is stacked up and down to form an adapter plate stacking multi-layer module; and the side pads of the base adapter plate in the upper module and the side pads of the cover cap adapter plate in the lower module are connected through conductive wires between the two adjacent adapter plate stacking modules.
The third embodiment of the invention provides an interposer stacking process, which comprises the following steps:
step S1, manufacturing a TSV conductive column on the first surface of a base wafer, and manufacturing an RDL and a bonding pad which are connected with one end of the TSV conductive column on the first surface of the base wafer; in particular, the method comprises the steps of,
as shown in fig. 1a, a first TSV hole 102 is fabricated on a first surface of a base wafer 101 by a photolithography and etching process;
then, a passivation layer is manufactured on the first surface of the base wafer 101, for example, silicon oxide or silicon nitride can be deposited, or the passivation layer is formed by direct thermal oxidation, the thickness of the passivation layer ranges from 10nm to 100 mu m, then, a seed layer is manufactured on the passivation layer through physical sputtering, magnetron sputtering or evaporation process, the seed layer can be one layer or multiple layers, and the metal material of the seed layer can be titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like;
as shown in fig. 1b, copper is electroplated on the first surface of the base wafer 101, so that the first TSV hole 102 is filled with copper metal, and the copper is densified at a temperature of 200 to 500 ℃ to be more dense, thereby forming a TSV conductive post in the base wafer;
copper CMP removes copper from the first surface of the base wafer 101, leaving copper filled in the first TSV hole 102;
depositing a seed layer on the first surface of the base wafer 101, and manufacturing an RDL and a bonding pad 103 on the first surface of the base wafer 101 through photoetching and electroplating processes; then removing the photoresist and the seed layer;
step S2, a carrier is temporarily bonded on the first surface of the base wafer, the second surface of the base wafer is thinned, and then a groove conductive column for forming a side surface bonding pad is manufactured; in particular, the method comprises the steps of,
as shown in fig. 1c, the carrier is temporarily bonded to the first surface of the base wafer 101 by a temporary bonding process, and the second surface of the base wafer is thinned with the carrier as a support; then making a side pad groove 104 on the second surface of the thinned base wafer through photoetching and dry etching processes;
as shown in fig. 1d, a passivation layer is then formed on the second surface of the base wafer 101, a seed layer is formed on the passivation layer, copper is electroplated to fill the side pad grooves 104 with copper metal, and densification is performed at a temperature of 200 to 500 ℃ to densify the copper and form the grooved conductive pillars 105 in the base wafer; it should be noted that, fig. 1d and the following figures are all structures after dicing the wafer, but the base wafer is not diced in this step;
copper CMP process removes copper from the second surface of the base wafer 101, leaving copper filled in the side pad grooves 104;
step S3, etching a cavity in a region corresponding to the TSV conductive column on the second surface of the base wafer, and then depositing a metal bonding pad connected with the other end of the TSV conductive column at the bottom of the cavity; in particular, the method comprises the steps of,
as shown in fig. 1e, the cavity 106 is etched on the second surface of the base wafer 101 through photolithography and dry etching processes, and the area where the cavity 106 is located corresponds to the TSV conductive post in the base wafer;
dry etching the cavity 106 of the base wafer to expose the other end of the TSV conductive post of the base wafer and the remaining wafer material above it; depositing a passivation layer on the second surface of the base wafer (naturally including the bottom of the cavity 106), and exposing the metal at the other end of the TSV conductive column through photoetching and dry etching; depositing a seed layer, and then depositing a metal pad 107 at the bottom of the cavity of the base wafer; then removing the photoresist and the seed layer;
s4, mounting a chip on the bottom of the cavity of the base wafer, wherein the back surface of the chip is connected with a grounding circuit in the RDL of the first surface of the base wafer through a bonding pad at the bottom of the cavity of the base wafer and a TSV conductive column in the base wafer; filling filler in the gap between the chip and the cavity; manufacturing an RDL and a bonding pad on the second surface of the base wafer, so that the working surface of the chip is electrically connected with the RDL on the second surface of the base wafer; in particular, the method comprises the steps of,
as shown in fig. 1f, a chip 108 is mounted on the bottom of the cavity of the base wafer 101, and the back surface of the chip 108 is connected with a ground line in the RDL of the first surface of the base wafer through a bottom bonding pad of the cavity of the base wafer and a TSV conductive post in the base wafer; filling the gap between the chip 108 and the cavity with a filler 109; continuously manufacturing an RDL and a bonding pad on the second surface of the base wafer, so that the working surface of the chip is electrically connected with the RDL on the second surface of the base wafer;
step S5, manufacturing a cavity corresponding to the cavity of the base wafer on the first surface of the cap wafer, and then manufacturing a groove conductive column for forming a side surface bonding pad on the second surface of the cap wafer;
referring to the process on the base wafer, as shown in fig. 1g, a cavity corresponding to the cavity of the base wafer may be fabricated on a first surface of the cap wafer 110, and then a recessed conductive post for forming a side pad may be fabricated on a second surface of the cap wafer;
s6, cutting the base wafer and the cap wafer respectively to form a base adapter plate and a cap adapter plate, cutting the groove conductive column of the base wafer to form a side surface bonding pad of the base adapter plate, and cutting the groove conductive column of the cap wafer to form a side surface bonding pad of the cap adapter plate;
s7, aligning, bonding and stacking the cap adapter plate and the base adapter plate to form an adapter plate stacking module;
as shown in fig. 1g, the cover cap adapter plate and the base adapter plate can be connected into an adapter plate stacking module through a welding or bonding process;
step S8, two or more adapter plate stacking modules are stacked up and down to form an adapter plate stacking multi-layer module; then, making conductive wires on the side surfaces of the multi-layer modules, so that the side surface bonding pads of the cover cap adapter plates of the single adapter plate stacking module are connected with the side surface bonding pads of the base adapter plates through the conductive wires, and the side surface bonding pads of the base adapter plates in the previous module are connected with the side surface bonding pads of the cover cap adapter plates in the next module through the conductive wires between the upper and lower adjacent adapter plate stacking modules;
in one embodiment, as shown in figures 1 h-1 k,
stacking a plurality of adapter plate stacking modules up and down to form an adapter plate stacking multi-layer module; then, planting solder balls 111 on the bonding pads on the side surfaces of the multi-layer module stacked by the adapter plate, and then, punching metal wires 112 below the solder balls 111; then reflow soldering fuses the solder balls with the underlying wires to form conductive lines 113; the size of the solder balls 111 can adjust the parameters such as resistivity, strength and the like of the finally formed conductive wires 113;
in another embodiment, as shown in FIGS. 1h, 1 l-1 m,
stacking a plurality of adapter plate stacking modules up and down to form an adapter plate stacking multi-layer module; then, solder balls 114 are planted on the bonding pads on the side surfaces of the multi-layer module stacked by the adapter plate, and two adjacent solder balls 114 are connected together through fusion by reflow soldering to form a conductive wire 113; the size of the solder balls 114 may be determined by parameters such as resistivity, strength, etc. of the finally formed conductive lines 113; the solder balls 114 in this embodiment are larger than the solder balls 111 in the previous embodiment;
and finally, the interconnection of the whole adapter plate stacked multilayer module is realized through the conductive wires on the side surfaces of the adapter plate stacked multilayer module.
Finally, it should be noted that the above-mentioned embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention, and all such modifications and equivalents are intended to be encompassed in the scope of the claims of the present invention.

Claims (9)

1. An adapter plate stacking module comprises a base adapter plate and a cap adapter plate, and is characterized in that,
the first surface of the base adapter plate is provided with an RDL and a bonding pad; the second surface of the base adapter plate is provided with a cavity, the second surface of the base adapter plate is provided with an RDL and a bonding pad, and the bottom of the cavity of the base adapter plate is provided with the bonding pad; the chip is arranged in the cavity of the base adapter plate, and the back surface of the chip is connected with a grounding line in the RDL of the first surface of the base adapter plate through a bonding pad at the bottom of the cavity and a TSV conductive column in the base adapter plate; the working surface of the chip is electrically connected with the RDL on the second surface of the base adapter plate; the RDL on the second surface of the base adapter plate is connected with a bonding pad arranged on the side surface of the base adapter plate;
the first surface of the cap adapter plate is provided with a cavity corresponding to the cavity of the base adapter plate, and the side surface of the cap adapter plate is provided with a bonding pad;
the cap adapter plate and the base adapter plate are in alignment bonding stacking; the side bonding pad of the cap adapter plate is connected with the side bonding pad of the base adapter plate through a conductive wire.
2. The interposer stack module of claim 1, wherein,
the bonding pads on the side surface of the base adapter plate extend downwards from the second surface of the base adapter plate; pads on the sides of the cap interposer extend downward from the second surface thereof.
3. The interposer stack module of claim 1, wherein,
and a filler is arranged around the chip in the cavity of the base adapter plate.
4. A interposer stack multilayer module comprising two or more interposer stack modules of claim 1, 2 or 3;
each adapter plate stacking module is stacked up and down to form an adapter plate stacking multi-layer module; and the side pads of the base adapter plate in the upper module and the side pads of the cover cap adapter plate in the lower module are connected through conductive wires between the two adjacent adapter plate stacking modules.
5. An interposer stacking process, comprising the steps of:
step S1, manufacturing a TSV conductive column on the first surface of a base wafer, and manufacturing an RDL and a bonding pad which are connected with one end of the TSV conductive column on the first surface of the base wafer;
step S2, a carrier is temporarily bonded on the first surface of the base wafer, the second surface of the base wafer is thinned, and then a groove conductive column for forming a side surface bonding pad is manufactured;
step S3, etching a cavity in a region corresponding to the TSV conductive column on the second surface of the base wafer, and then depositing a metal bonding pad connected with the other end of the TSV conductive column at the bottom of the cavity;
s4, mounting a chip on the bottom of the cavity of the base wafer, wherein the back surface of the chip is connected with a grounding circuit in the RDL of the first surface of the base wafer through a bonding pad at the bottom of the cavity of the base wafer and a TSV conductive column in the base wafer; filling filler in the gap between the chip and the cavity; manufacturing an RDL and a bonding pad on the second surface of the base wafer, so that the working surface of the chip is electrically connected with the RDL on the second surface of the base wafer;
step S5, manufacturing a cavity corresponding to the cavity of the base wafer on the first surface of the cap wafer, and then manufacturing a groove conductive column for forming a side surface bonding pad on the second surface of the cap wafer;
s6, cutting the base wafer and the cap wafer respectively to form a base adapter plate and a cap adapter plate, cutting the groove conductive column of the base wafer to form a side surface bonding pad of the base adapter plate, and cutting the groove conductive column of the cap wafer to form a side surface bonding pad of the cap adapter plate;
s7, aligning, bonding and stacking the cap adapter plate and the base adapter plate to form an adapter plate stacking module;
step S8, two or more adapter plate stacking modules are stacked up and down to form an adapter plate stacking multi-layer module; and then, manufacturing conductive wires on the side surfaces of the multi-layer modules, so that the side surface bonding pads of the cover cap adapter plates of the single adapter plate stacking module are connected with the side surface bonding pads of the base adapter plates through the conductive wires, and the side surface bonding pads of the base adapter plates in the previous module are connected with the side surface bonding pads of the cover cap adapter plates in the next module through the conductive wires between the upper and lower adjacent adapter plate stacking modules.
6. The interposer stacking process of claim 5, wherein,
the step S1 specifically comprises the following steps:
manufacturing a first TSV hole on the first surface of the base wafer through photoetching and etching processes;
then, a passivation layer is manufactured on the first surface of the base wafer, and then a seed layer is manufactured on the passivation layer;
electroplating copper on the first surface of the base wafer to enable copper metal to be filled in the first TSV hole, and enabling copper to be more compact at the temperature of 200-500 ℃ to form TSV conductive columns in the base wafer;
copper CMP process removes copper from the first surface of the base wafer, leaving copper filled in the first TSV hole;
depositing a seed layer on the first surface of the base wafer, manufacturing an RDL and a bonding pad on the first surface of the base wafer through photoetching and electroplating processes, and then removing the photoresist and the seed layer;
the step S2 specifically comprises the following steps:
temporarily bonding the slide glass with the first surface of the base wafer through a temporary bonding process, and thinning the second surface of the base wafer by taking the slide glass as a support; then making a side bonding pad groove on the second surface of the thinned base wafer through photoetching and dry etching processes;
then, a passivation layer is manufactured on the second surface of the base wafer, a seed layer is manufactured on the passivation layer, copper is electroplated, copper metal is fully filled in the grooves of the side welding disk, copper is densified at the temperature of 200-500 ℃ to be more compact, and groove conductive columns in the base wafer are formed;
the copper CMP process removes copper from the second surface of the base wafer, leaving copper filled in the side pad grooves.
7. The interposer stacking process of claim 5, wherein,
the step S3 specifically comprises the following steps:
continuing to etch the cavity on the second surface of the base wafer through photoetching and dry etching processes, wherein the area where the cavity is located corresponds to the TSV conductive column in the base wafer;
dry etching the cavity of the base wafer to expose the other end of the TSV conductive column of the base wafer and the remaining wafer material above the TSV conductive column; depositing a passivation layer on the second surface of the base wafer, and exposing the metal at the other end of the TSV conductive column through photoetching and dry etching; depositing a seed layer, and then depositing a metal bonding pad at the bottom of the cavity of the base wafer; the photoresist and seed layer are then removed.
8. The interposer stacking process of claim 5, wherein,
in step S8, the manufacturing of the conductive wire on the side of the multilayer module specifically includes:
planting solder balls on the bonding pads on the side surfaces of the multi-layer module stacked by the adapter plate, and then punching metal wires below the solder balls; reflow then causes the solder balls to fuse with the underlying wires to form conductive lines.
9. The interposer stacking process of claim 5, wherein,
in step S8, the manufacturing of the conductive wire on the side of the multilayer module specifically includes:
solder balls are planted on the bonding pads on the side surfaces of the multi-layer module stacked by the adapter plate, and two adjacent solder balls are connected together through fusion by reflow soldering to form a conductive wire.
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