JP4611943B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4611943B2 JP4611943B2 JP2006192881A JP2006192881A JP4611943B2 JP 4611943 B2 JP4611943 B2 JP 4611943B2 JP 2006192881 A JP2006192881 A JP 2006192881A JP 2006192881 A JP2006192881 A JP 2006192881A JP 4611943 B2 JP4611943 B2 JP 4611943B2
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- JP
- Japan
- Prior art keywords
- insulating film
- film
- interlayer insulating
- redistribution layer
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Description
図1に示すように、半導体装置1は、半導体基板100と絶縁膜101と電極パッド102とパッシベーション膜103と第1層間絶縁膜110と第1下地金属層104と第1再配線層11と第2層間絶縁膜120と第2下地金属層191と第2再配線層192と封止樹脂190と電極ポスト198と球状電極199とを有する。
次に、以上のような構成を有する半導体装置1の製造方法を、図面と共に詳細に説明する。図2(a)から図7は、本実施例による半導体装置1の製造方法を示すプロセス図である。
図8に示すように、半導体装置2は、実施例1による半導体装置1と同様の構成において、第1再配線層11が第1再配線層21に置き換えられた構成を有する。その他の構成は、実施例1と同様であるため、ここでは詳細な説明を省略する。
次に、以上のような構成を有する半導体装置2の製造方法を、図面と共に詳細に説明する。図9(a)から図9(c)は、本実施例による半導体装置2の製造方法を示すプロセス図である。なお、半導体基板100を準備する工程から第1層間絶縁膜110上及び開口110a内に第1下地金属膜104Aを形成するまでの工程(図2(a)から図2(c)参照)、及び、第1再配線層21(実施例1における第1再配線層11に相当)下以外の第1下地金属膜104Aをエッチング除去する工程から電極ポスト198上面に球状電極199を形成するまでの工程(図4(a)から図7及び図1参照)は、実施例1と同様であるため、ここではこれを引用して説明する。
図10に示すように、半導体装置3は、実施例1による半導体装置1と同様の構成において、第1再配線層11が第1再配線層31に置き換えられた構成を有する。その他の構成は、実施例1と同様であるため、ここでは詳細な説明を省略する。
次に、以上のような構成を有する半導体装置3の製造方法を、図面と共に詳細に説明する。図11(a)及び図11(b)は、本実施例による半導体装置3の製造方法を示すプロセス図である。なお、半導体基板100を準備する工程から第1層間絶縁膜110上及び開口110a内に第1下地金属膜104Aを形成するまでの工程(図2(a)から図2(c)参照)、及び、第1再配線層31(実施例1における第1再配線層11に相当)下以外の第1下地金属膜104Aをエッチング除去する工程から電極ポスト198上面に球状電極199を形成するまでの工程(図4(a)から図7及び図1参照)は、実施例1と同様であるため、ここではこれを引用して説明する。
図12に示すように、半導体装置4は、実施例1による半導体装置1と同様の構成において、第1再配線層11が第1再配線層41に置き換えられた構成を有する。その他の構成は、実施例1と同様であるため、ここでは詳細な説明を省略する。
次に、以上のような構成を有する半導体装置4の製造方法を、図面と共に詳細に説明する。図13(a)及び図13(b)は、本実施例による半導体装置4の製造方法を示すプロセス図である。なお、半導体基板100を準備する工程から第1層間絶縁膜110上及び開口110a内に第1下地金属膜104Aを形成するまでの工程(図2(a)から図2(c)参照)、及び、第1再配線層41(実施例1における第1再配線層11に相当)下以外の第1下地金属膜104Aをエッチング除去する工程から電極ポスト198上面に球状電極199を形成するまでの工程(図4(a)から図7及び図1参照)は、実施例1と同様であるため、ここではこれを引用して説明する。
図14に示すように、本実施例による半導体装置5は、最上層である第2層間絶縁膜120上に形成された第2再配線層51が、実施例1による第1再配線層11と同様の構成を有する。なお、他の構成は、実施例1(ただし、実施例2から4を除外するものではない)と同様であるため、ここでは詳細な説明を省略する。
また、本実施例による半導体装置5の製造方法は、実施例1で示した半導体装置1の製造方法において、図5(a)を用いて説明した第2再配線層192の形成工程を、図3(a)から図3(c)を用いて説明した第1再配線層11の形成工程と同様の形成工程に置き換えることで実現することが可能である。このため、ここでは詳細な説明を省略する。
図15に示すように、本実施例による半導体装置6は、最上層である第2層間絶縁膜120上に形成された第2再配線層61が、実施例2による第1再配線層21と同様の構成を有する。なお、他の構成は、実施例2(ただし、実施例1、3及び4を除外するものではない)と同様であるため、ここでは詳細な説明を省略する。
また、本実施例による半導体装置6の製造方法は、実施例1で示した半導体装置1の製造方法において、図5(a)を用いて説明した第2再配線層192の形成工程を、図9
(a)から図9(c)を用いて説明した第1再配線層21の形成工程と同様の形成工程に置き換えることで実現することが可能である。このため、ここでは詳細な説明を省略する。
図16に示すように、本実施例による半導体装置7は、最上層である第2層間絶縁膜120上に形成された第2再配線層71が、実施例3による第1再配線層31と同様の構成を有する。なお、他の構成は、実施例3(ただし、実施例1、2及び4を除外するものではない)と同様であるため、ここでは詳細な説明を省略する。
また、本実施例による半導体装置7の製造方法は、実施例1で示した半導体装置1の製造方法において、図5(a)を用いて説明した第2再配線層192の形成工程を、図11(a)及び図11(b)を用いて説明した第1再配線層31の形成工程と同様の形成工程に置き換えることで実現することが可能である。このため、ここでは詳細な説明を省略する。
図17に示すように、本実施例による半導体装置8は、最上層である第2層間絶縁膜120上に形成された第2再配線層81が、実施例4による第1再配線層41と同様の構成を有する。なお、他の構成は、実施例4(ただし、実施例1から3を除外するものではない)と同様であるため、ここでは詳細な説明を省略する。
また、本実施例による半導体装置8の製造方法は、実施例1で示した半導体装置1の製造方法において、図5(a)を用いて説明した第2再配線層192の形成工程を、図13(a)及び図13(b)を用いて説明した第1再配線層41の形成工程と同様の形成工程に置き換えることで実現することが可能である。このため、ここでは詳細な説明を省略する。
11、21、31、31A、41、41A、51、61、71、81 第1再配線層
11a、21a 段差
12、22 第1金属膜
13、23 第2金属膜
14、24 第3金属膜
31a,41a エッジ部
100 半導体基板
101 絶縁膜
102 電極パッド
103 パッシベーション膜
104、104A 第1下地金属膜
110 第1層間絶縁膜
110a 開口
120 第2層間絶縁膜
120a 開口
190、190A 封止樹脂
191、191A 第2下地金属膜
192 第2再配線層
198 電極ポスト
199 球状電極
200 所定電極
R11、R12、R13、R14、R15、R21、R21a、R21b、R31、R32、R41 フォトレジスト膜
Claims (7)
- 半導体基板と、
前記半導体基板上に形成され、第1開口を有する第1絶縁膜と、
前記第1絶縁膜上の一部から前記第1開口内にかけて形成され、最上面の大きさが前記第1絶縁膜と接する面の外周に囲まれた領域の大きさよりも小さい第1再配線層と、
前記第1再配線層上及び前記第1絶縁膜上に形成された第2絶縁膜と
を有し、
前記第1再配線層はCuからなり、前記第1再配線層は、前記第1再配線層の外縁部が階段状となるように複数積層されて構成されていることを特徴とする半導体装置。 - 前記第1再配線層は、前記第1絶縁膜上の一部から前記第1開口内にかけて形成された第1導電体膜と、当該第1導電体膜上に形成され、当該第1導電体膜の上面よりも小さい上面を有する第2導電体膜とから構成されていることを特徴とする請求項1記載の半導体装置。
- 前記第2導電体膜は、2層以上の多層膜で構成され、
前記第2導電体膜における各層は、上面の大きさが直下に位置する層の上面の大きさよりも小さいことを特徴とする請求項2記載の半導体装置。 - 前記第1再配線層は、前記第1絶縁膜上の一部から前記第1開口内にかけて形成された第1導電体膜と、当該第1導電体膜を覆い、外縁部に階段状の段差を有する第2導電体膜とから構成されていることを特徴とする請求項1記載の半導体装置。
- 前記第2導電体膜は、2層以上の多層膜で構成され、
前記第2導電体膜における各層は、直下に位置する層を覆い、且つ、外縁部に階段状の段差を有することを特徴とする請求項4記載の半導体装置。 - 前記第1再配線層と前記第1絶縁膜との間に形成された金属膜をさらに有し、
前記第1再配線層は、前記金属膜をシード層として析出された金属めっき膜であることを特徴とする請求項1から5の何れか1項に記載の半導体装置。 - 前記第2絶縁膜は、前記第1再配線層の一部を露出させる第2開口を有し、
前記第2絶縁膜上及び前記第2開口内に形成され、最上面の大きさが前記第2絶縁膜と接する面の外周に囲まれた領域の大きさよりも小さい第2再配線層と、
前記第2再配線層上及び前記第2絶縁膜上に形成された封止樹脂と
をさらに有することを特徴とする請求項1から6の何れか1項に記載の半導体装置。
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US20220165694A1 (en) * | 2020-11-26 | 2022-05-26 | Mediatek Inc. | Semiconductor structure |
WO2023026984A1 (ja) * | 2021-08-26 | 2023-03-02 | ローム株式会社 | 電子部品 |
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US5268072A (en) * | 1992-08-31 | 1993-12-07 | International Business Machines Corporation | Etching processes for avoiding edge stress in semiconductor chip solder bumps |
US5376584A (en) * | 1992-12-31 | 1994-12-27 | International Business Machines Corporation | Process of making pad structure for solder ball limiting metallurgy having reduced edge stress |
KR100306842B1 (ko) * | 1999-09-30 | 2001-11-02 | 윤종용 | 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법 |
JP2002050647A (ja) * | 2000-08-01 | 2002-02-15 | Sharp Corp | 半導体装置及びその製造方法 |
JP2003045877A (ja) * | 2001-08-01 | 2003-02-14 | Sharp Corp | 半導体装置およびその製造方法 |
JP3813482B2 (ja) | 2001-10-11 | 2006-08-23 | 株式会社フジクラ | 半導体パッケージの製造方法 |
US6749760B2 (en) * | 2001-10-26 | 2004-06-15 | Intel Corporation | Etchant formulation for selectively removing thin films in the presence of copper, tin, and lead |
JP2003234429A (ja) | 2002-02-07 | 2003-08-22 | Hitachi Ltd | 半導体装置の製造方法 |
US6881999B2 (en) * | 2002-03-21 | 2005-04-19 | Samsung Electronics Co., Ltd. | Semiconductor device with analog capacitor and method of fabricating the same |
TWI317548B (en) * | 2003-05-27 | 2009-11-21 | Megica Corp | Chip structure and method for fabricating the same |
TWI229930B (en) * | 2003-06-09 | 2005-03-21 | Advanced Semiconductor Eng | Chip structure |
TWI230450B (en) * | 2003-06-30 | 2005-04-01 | Advanced Semiconductor Eng | Under bump metallurgy structure |
TWI229436B (en) * | 2003-07-10 | 2005-03-11 | Advanced Semiconductor Eng | Wafer structure and bumping process |
US7470997B2 (en) * | 2003-07-23 | 2008-12-30 | Megica Corporation | Wirebond pad for semiconductor chip or wafer |
US7244671B2 (en) * | 2003-07-25 | 2007-07-17 | Unitive International Limited | Methods of forming conductive structures including titanium-tungsten base layers and related structures |
JP4327657B2 (ja) * | 2004-05-20 | 2009-09-09 | Necエレクトロニクス株式会社 | 半導体装置 |
JP4327656B2 (ja) * | 2004-05-20 | 2009-09-09 | Necエレクトロニクス株式会社 | 半導体装置 |
KR100630698B1 (ko) * | 2004-08-17 | 2006-10-02 | 삼성전자주식회사 | 솔더볼 접착 신뢰도를 높이는 반도체 패키지 및 그 제조방법 |
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US7847407B2 (en) | 2010-12-07 |
US20080023836A1 (en) | 2008-01-31 |
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US8274154B2 (en) | 2012-09-25 |
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