JP7150632B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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JP7150632B2
JP7150632B2 JP2019023766A JP2019023766A JP7150632B2 JP 7150632 B2 JP7150632 B2 JP 7150632B2 JP 2019023766 A JP2019023766 A JP 2019023766A JP 2019023766 A JP2019023766 A JP 2019023766A JP 7150632 B2 JP7150632 B2 JP 7150632B2
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semiconductor
protective adhesive
wiring layer
semiconductor device
insulating film
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JP2020136316A (ja
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真也 志摩
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Kioxia Corp
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Kioxia Corp
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Priority to JP2019023766A priority Critical patent/JP7150632B2/ja
Priority to TW108130609A priority patent/TWI732279B/zh
Priority to US16/553,789 priority patent/US11107788B2/en
Priority to CN201910807005.8A priority patent/CN111564372B/zh
Publication of JP2020136316A publication Critical patent/JP2020136316A/ja
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Description

本実施形態は、半導体装置の製造方法に関する。
多層再配線構造（ＲＤＬ（Redistribution Layer））を有する半導体チップは、配線密度差によって表面に凹凸が生じる。この表面の凹凸が大きくなると、半導体チップを他の半導体チップ上に積層する際に、樹脂フィルムまたは樹脂ペーストが半導体チップ間の隙間を埋めることできず、ボイドが発生しやすい。これは、半導体パッケージの信頼性および歩留まりを低下させる。
米国特許公開第２０１５／０２００１６６号公報 米国特許第６８８８２０９号公報 特許第５９４９１９３号公報 特開２０１１－１５１２８９号公報
半導体チップ間に樹脂を充分に充填することができ、信頼性の高い半導体装置を製造する。
本実施形態による半導体装置の製造方法は、基板の第１面に半導体素子を形成する。半導体素子の上方に第１絶縁膜を形成する。第１絶縁膜上に第１配線層を形成する。第１配線層上に第２絶縁膜を形成する。第２絶縁膜上に第２配線層を形成する。第２配線層上に第１電極を形成する。第１電極および第２配線層を被覆する保護接着剤を塗布する。保護接着剤上に支持基板を接着する。第１面に対して反対側の基板の第２面を研磨する。支持基板を保護接着剤から取り外す。第１電極が露出されるまで保護接着剤を研削する。
本実施形態による半導体装置の製造方法の一例を示す断面図。 図１に続く、半導体装置の製造方法を示す断面図。 図２に続く、半導体装置の製造方法を示す断面図。 図３に続く、半導体装置の製造方法を示す断面図。
以下、図面を参照して本発明に係る実施形態を説明する。本実施形態は、本発明を限定するものではない。以下の実施形態において、半導体基板の上下方向は、半導体素子が設けられる面を上とした場合の相対方向を示し、重力加速度に従った上下方向と異なる場合がある。図面は模式的または概念的なものであり、各部分の比率などは、必ずしも現実のものと同一とは限らない。明細書と図面において、既出の図面に関して前述したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
（半導体装置の製造方法）
図１（Ａ）から図４は、本実施形態による半導体装置の製造方法の一例を示す断面図である。まず、半導体基板１０の第１面Ｆ１上に半導体素子（図示せず）を形成する。半導体基板は、例えば、シリコン基板等でよい。半導体素子は、例えば、メモリセルアレイ、トランジスタ、ダイオード、抵抗素子、キャパシタ等でよい。半導体装置は、例えば、ＮＡＮＤ型フラッシュメモリ等の半導体チップ、あるいは、複数の半導体チップをフリップチップ接続した半導体パッケージでよい。
次に、半導体基板１０および半導体素子の上方に、配線２０が形成される。配線２０は、半導体素子の少なくとも一部にコンタクトプラグ（図示せず）を介して電気的に接続されている。配線２０は、例えば、アルミニウム等の導電性金属で形成されている。
次に、パッシべーション膜３０を配線２０上に形成する。パッシべーション膜３０には、例えば、ＳｉＯ２等の絶縁材料を用いている。次に、リソグラフィ技術およびエッチング技術を用いてパッシべーション膜３０を加工し、配線２０の表面の一部を露出させる。
次に、半導体素子の上方に配線２０およびパッシべーション膜３０を被覆する第１絶縁膜としての層間絶縁膜４０を形成する。層間絶縁膜４０には、例えば、ポリイミド等の絶縁膜を用いている。次に、リソグラフィ技術およびエッチング技術を用いて、層間絶縁膜４０を加工する。これにより、配線２０の表面の一部を露出させる。層間絶縁膜４０が感光性ポリイミドである場合、リソグラフィ工程においてフォトレジストは不要となる。
次に、層間絶縁膜４０上に第１配線層５０を形成する。第１配線層５０は、所謂、ＲＤＬ（Redistribution Layer）である。第１配線層５０には、例えば、アルミニウム、銅、タングステン等の導電性金属を用いている。次に、リソグラフィ技術およびエッチング技術を用いて、第１配線層５０を加工する。
次に、第１配線層５０および層間絶縁膜４０上に第２絶縁膜としての層間絶縁膜６０を形成する。層間絶縁膜６０には、例えば、ポリイミド等の絶縁膜を用いている。層間絶縁膜６０の材料は、層間絶縁膜４０の材料と同じでもよい。次に、リソグラフィ技術およびエッチング技術を用いて、層間絶縁膜６０を加工する。これにより、第１配線層５０の表面の一部を露出させる。層間絶縁膜６０が感光性ポリイミドである場合、リソグラフィ工程においてフォトレジストは不要となる。
次に、層間絶縁膜６０上に第２配線層７０を形成する。第２配線層７０は、第１配線層５０と同様にＲＤＬである。第２配線層７０には、例えば、アルミニウム、銅、タングステン等の導電性金属を用いている。第２配線層７０の材料は、第１配線層５０の材料と同様でよい。次に、リソグラフィ技術およびエッチング技術を用いて、第２配線層７０を加工する。
次に、第２配線層７０上に第１電極としてのバンプ８０を形成する。第２配線層７０上にバンプ８０の材料を堆積し、リソグラフィ技術およびエッチング技術を用いてバンプ８０の材料を加工する。これにより、バンプ８０が第２配線層７０上に形成される。バンプ８０の材料には、例えば、銅、ニッケル、金、スズ、タングステン等の導電性金属を用いている。これにより、図１（Ａ）に示す構造が得られる。
次に、図１（Ｂ）に示すように、バンプ８０、第２配線層７０および層間絶縁膜６０を被覆するように保護接着剤９０を塗布する。保護接着剤９０は、バンプ８０の上面の上方まで形成され、バンプ８０全体を埋め込む。このとき、保護接着剤９０の上面は、バンプ８０の上面よりも上方にある。保護接着剤９０は、バンプ８０、第２配線層７０および層間絶縁膜６０を保護するとともに、支持基板１１０を接着する接着剤としての機能を兼ね備える。保護接着剤９０には、例えば、ポリイミド等の絶縁材料を用いる。保護接着剤９０は、リソグラフィ技術を用いて加工する必要がない。むしろ感光基は不要なガスの発生原因となるため、非感光性材料であることが望ましい。このように、本実施形態では、層間絶縁膜４０、６０は、感光性を有するポリイミドであり、保護接着剤９０は、感光性を有しないポリイミドが望ましい。
ここで、保護接着剤９０は、スピン等によって塗布され、あるいは、シート状で貼付される。これにより、保護接着剤９０は、凹凸のあるバンプ８０、第２配線層７０および層間絶縁膜６０の表面を略平坦な状態で被覆する。保護接着剤９０の表面が略平坦であることによって、支持基板１１０を保護接着剤９０に隙間無く容易に貼合わせることができる。
次に、保護接着剤９０の上に、剥離層１００を形成する。剥離層１００には、例えば、シリコーンのような柔軟性のある樹脂材料を用いる。剥離層１００は、保護接着剤９０に貼合わせた支持基板１１０を剥がし易くするために、保護接着剤９０と支持基板１１０との間に設けられている。
次に、剥離層１００上に支持基板１１０を貼付する。支持基板１１０は、剛性を有する材料であり、例えば、シリコン基板等でよい。これにより、図１（Ｂ）に示す構造が得られる。
次に、支持基板１１０を保持して回転させ、第１面Ｆ１に対して反対側の半導体基板１０の第２面Ｆ２を研磨する。これにより、図２（Ａ）に示すように、半導体基板１０が薄化される。
次に、半導体基板１０を貫通して半導体素子の少なくとも一部に繋がるビアを形成し、そのビア内に導電性金属を埋め込む。これにより、図２（Ｂ）に示すように、半導体素子の少なくとも一部に接続される第２電極としての貫通電極（ＴＳＶ（Through-Silicon Via）１２０が形成される。貫通電極１２０は、貫通部分１２１と、接続部分１２２とを有する。貫通部分１２１には、例えば、銅を用いている。接続部分１２２には、例えば、はんだ（Ｓｎ）を用いている。尚、本実施形態において、貫通電極１２０は、半導体基板１０の薄化後に形成されている。しかし、貫通電極１２０は、半導体基板１０の薄化前に形成されてもよい。例えば、貫通電極１２０は、半導体素子の形成前、あるいは、半導体素子の形成途中に半導体基板１０内に形成してもよい。
次に、図３（Ａ）に示すように、支持基板１１０を剥離層１００から剥がし、保護接着剤９０から取り外す。
次に、図３（Ｂ）に示すように、バンプ８０の上面が露出されるまで保護接着剤９０を研削する。このとき、保護接着剤９０は、物理的に研削（切削）される。これにより、保護接着剤９０およびバンプ８０は、略面一となる。あるいは、研磨装置等により、保護接着剤９０を研磨してもよい。保護接着剤９０を研削、研磨するとき、バンプ８０の上部を同時に研削、研磨してバンプ８０と、保護接着剤９０とを略面一としてもよい。ここでいう面一とは、バンプ８０の上面と保護接着剤９０とが略平坦面を形成していることである。
その後、半導体基板１０をダイシングして、半導体基板１０を半導体チップへ個片化する。半導体チップは、フリップチップボンディングにより、他の半導体チップに積層される。そのとき、接続部分１２２は、他の半導体チップのバンプ８０に接続される。これにより、半導体素子は、他の半導体チップの半導体素子と電気的に接続され得る。あるいは、半導体チップは、実装基板（図示せず）に搭載されてもよい。この場合、接続部分１２２は、実装基板の電極に接続される。
図４は、フリップチップボンディングされた複数の半導体チップの構成の一例を示す断面図である。図４では、半導体チップ１ａ、１ｂは、本実施形態による製造方法で製造された半導体チップである。尚、便宜的に、半導体チップ１ａの構成要素には、参照番号の後にａを付している。半導体チップ１ｂの構成要素には、参照番号の後にｂを付している。
第１半導体装置としての半導体チップ１ａ上に、第２半導体装置としての半導体チップ１ｂを積層する。半導体チップ１ｂの第２面Ｆ２ａ側にある貫通電極１２０ｂが半導体チップ１ａの第１面Ｆ１ａ側にあるバンプ８０ａ上に配置されるようにする。次に、熱処理を実行することにより、半導体チップ１ｂの接続部分１２２ｂがリフローし、半導体チップ１ａのバンプ８０ａに接続される。
次に、半導体チップ１ａと半導体チップ１ｂとの間に樹脂２００を充填または貼付する。樹脂２００は、樹脂ペーストまたは樹脂フィルムである。樹脂２００は、半導体チップ１ａの保護接着剤９０ａの上面に塗布または貼付され、その上に半導体チップ１ｂの半導体基板１０ｂの第２面Ｆ２ｂを載せる。あるいは、樹脂２００は、半導体チップ１ｂの第２面Ｆ２ｂに塗布または貼付され、その下に半導体チップ１ｂの保護接着剤９０ａの上面を載せる。そして、熱処理することによって、貫通電極１２０ｂの接続部分１２２ｂがバンプ８０ａに接続されるとともに、樹脂２００が半導体チップ１ａ、１ｂ間に充填される。
半導体チップ１ａ、１ｂがさらに他の半導体チップ上に設けられている場合には、樹脂２００は、それらの半導体チップ間にも充填される。
さらに、フリップチップ接続された複数の半導体チップは、図示しない封止樹脂によって被覆される。これにより、複数の半導体チップが保護され、半導体パッケージが完成する。
本実施形態によれば、保護接着剤９０は、バンプ８０、第２配線層７０および層間絶縁膜６０を被覆して保護するとともに、支持基板１１０を接着する接着剤としての機能を兼ね備える。従って、第２配線層７０および層間絶縁膜６０を保護する層間絶縁膜とは別途に、接着剤を設ける必要ない。
通常、複数の再配線層（ＲＤＬ）を有する場合、最上層の層間絶縁膜の表面の凹凸はその下にある配線によって大きくなり、その凹凸を埋めるように接着剤が塗布される。この接着剤により、支持基板１１０を半導体基板１０に対して貼り付けることができる。しかし、この場合、層間絶縁膜の他、接着剤が必要となる。
これに対し、本実施形態によれば、保護接着剤９０が最上層の層間絶縁膜および支持基板１１０の接着剤を兼ねる。従って、保護接着剤９０と別に、接着剤を設ける必要ない。保護接着剤９０は、バンプ８０、第２配線層７０および層間絶縁膜６０を被覆した後、バンプ８０の表面を露出させるように研削される。これにより、保護接着剤９０の表面は平坦化される。保護接着剤９０の表面が略平坦であることによって、支持基板１１０の貼り付けおよび剥離が容易となり、かつ、支持基板１１０の剥離後に保護接着剤９０の表面が略平坦であるので、他の半導体チップをフリップチップ接続するときに、半導体チップ間の樹脂２００がボイドなく充填され得る。即ち、本実施形態によれば、複数の半導体チップのフリップチップ接続を容易にすることができ、かつ、半導体チップ間にボイドが発生することを抑制できる。
また、保護接着剤９０は、パターニングの必要が無く、全体として研削されるに過ぎない。従って、保護接着剤９０は、非感光性の絶縁材料でよい。むしろ、感光基は熱処理時に不要なガスの発生の原因となる。これに対し、感光基を有しない保護接着剤９０は、熱処理時に不要なガスの発生を抑制することができる。
また、貫通電極１２０の貫通部分１２１およびバンプ８０（例えば、銅）の融点は、貫通電極１２０の接続部分１２２（例えば、はんだ）の融点よりも低い。これにより、図４に示すように、複数の半導体チップ１ａ、１ｂを積層し、熱処理することによって、貫通部分１２１およびバンプ８０を溶融させることなく接続部分１２２を溶融させて、接続部分１２２をバンプ８０に接続することができる。複数の貫通電極１２０および複数のバンプ８０が半導体チップに設けられている場合、１回の熱処理により、複数の接続部分１２２をそれに対応する複数のバンプ８０にそれぞれ接続することができる。これにより、複数の半導体チップをフリップチップ接続することができる。
（半導体装置の構成）
本実施形態により製造された半導体装置は、図３（Ｂ）に示すように、半導体基板１０と、配線２０と、パッシべーション膜３０と、層間絶縁膜４０、６０と、第１配線層５０と、第２配線層７０と、バンプ８０と、保護接着剤９０と、貫通電極１２０とを備えている。
半導体基板１０の第１面Ｆ１上に、配線２０が設けられている。パッシべーション膜３０は配線２０を被覆するように設けられている。層間絶縁膜４０は、パッシべーション膜３０上に設けられている。配線２０の表面の一部はパッシべーション膜３０および層間絶縁膜４０から露出されている。第１配線層５０は、層間絶縁膜４０上に設けられており、配線２０の露出部分に接続されている。
第２層間絶縁膜６０は、第１配線層５０上に設けられており、第１配線層５０の一部を露出している。第２配線層７０は、層間絶縁膜６０上に設けられており、第１配線層５０の露出部分に接続されている。第１および第２配線層５０、７０は、再配線層（ＲＤＬ）として設けられている。このように、本実施形態は、複数の再配線層からなる多層再配線構造を有する。
バンプ８０は、第２配線層７０上に設けられている。保護接着剤９０は、第２配線層７０および層間絶縁膜６０を被覆するように、バンプ８０の周囲に設けられている。保護接着剤９０は、第２配線層７０および層間絶縁膜６０を被覆しつつ、バンプ８０の上面を露出させている。また、保護接着剤９０は、配線層５０、７０および層間絶縁膜４０、６０の凹凸を吸収して略平坦な表面を半導体装置に提供することができる。これにより、複数の半導体チップをフリップチップ接続したときに、半導体チップ間に樹脂を容易に充填させることができ、半導体チップ間においてボイドの発生を抑制することができる。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれると同様に、特許請求の範囲に記載された発明とその均等の範囲に含まれるものである。
１０ 半導体基板、２０ 配線、３０ パッシべーション膜、４０、６０ 層間絶縁膜、５０ 第１配線層、７０ 第２配線層、８０ バンプ、９０ 保護接着剤、１２０ 貫通電極

Claims (6)

  1. 基板の第１面に半導体素子を形成し、
    前記半導体素子の上方に第１絶縁膜を形成し、
    前記第１絶縁膜上に第１配線層を形成し、
    前記第１配線層上に第２絶縁膜を形成し、
    前記第２絶縁膜上に第２配線層を形成し、
    前記第２配線層上に第１電極を形成し、
    前記第１電極および前記第２配線層を被覆する保護接着剤を塗布し、
    前記保護接着剤上に支持基板を接着し、
    前記第１面に対して反対側の前記基板の第２面を研磨し、
    前記支持基板を前記保護接着剤から取り外し、
    前記第１電極が露出されるまで前記保護接着剤を研削することを具備する半導体装置の製造方法。
  2. 前記第２面の研磨後、前記基板を貫通して前記半導体素子に接続される第２電極を形成することをさらに具備する請求項１に記載の半導体装置の製造方法。
  3. 前記第１および前記第２絶縁膜は、感光性を有する絶縁材料であり、
    前記保護接着剤は、感光性を有しない絶縁材料である、請求項１または請求項２に記載の半導体装置の製造方法。
  4. 前記第１および前記第２絶縁膜は、感光性を有するポリイミドであり、
    前記保護接着剤は、感光性を有しないポリイミドである、請求項１または請求項２に記載の半導体装置の製造方法。
  5. 前記保護接着剤の研削後、前記保護接着剤および前記第１電極は、略面一となっている、請求項１から請求項４のいずれか一項に記載の半導体装置の製造方法。
  6. 請求項１から請求項５のいずれか一項に記載の複数の前記半導体装置を積層し、
    該複数の半導体装置のうち第１半導体装置の前記第１電極に、第２半導体装置の前記第２電極を接続し、
    前記第１半導体装置と前記第２半導体装置との間に樹脂を充填することをさらに具備する半導体パッケージの製造方法。
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