CN112490198A - 包括导电凸块的半导体封装件 - Google Patents

包括导电凸块的半导体封装件 Download PDF

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Publication number
CN112490198A
CN112490198A CN202010835756.3A CN202010835756A CN112490198A CN 112490198 A CN112490198 A CN 112490198A CN 202010835756 A CN202010835756 A CN 202010835756A CN 112490198 A CN112490198 A CN 112490198A
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semiconductor chip
substrate
semiconductor
support layer
conductive bumps
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CN202010835756.3A
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李世容
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN112490198A publication Critical patent/CN112490198A/zh
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Abstract

提供了一种半导体封装件。所述半导体封装件包括包含第一贯穿电极的第一半导体芯片。第二半导体芯片堆叠在第一半导体芯片上。第二半导体芯片包括第二贯穿电极。多个导电凸块置于第一半导体芯片与第二半导体芯片之间。导电凸块将第一贯穿电极和第二贯穿电极彼此电连接。填充支撑层至少部分地覆盖第二半导体芯片的面对第一半导体芯片的第一表面，并且至少部分地填充导电凸块之间的空间。粘合层设置在填充支撑层上，至少部分地填充导电凸块之间的所述空间并且将第一半导体芯片和第二半导体芯片彼此粘附。

Description

包括导电凸块的半导体封装件
本申请要求于2019年9月11日在韩国知识产权局(KIPO)提交的第10-2019-0112510号韩国专利申请的优先权的权益，该韩国专利申请的内容通过引用全部包含于此。
技术领域
本公开涉及一种半导体封装件，更具体地，涉及一种包括导电凸块的半导体封装件及其制造方法。
背景技术
在制造包括通过贯穿电极彼此电连接的半导体芯片的多芯片封装件中，在使用基底支撑系统将晶圆支撑在载体基底上之后，可以研磨晶圆的背面以减小晶圆的厚度。然而，因为晶圆在研磨工艺期间可能翘曲或损坏，所以晶圆的厚度可以安全地减小多少会存在限制。
发明内容
根据本公开的示例性实施例，半导体封装件包括包含第一贯穿电极的第一半导体芯片。第二半导体芯片堆叠在第一半导体芯片上，并且第二半导体芯片包括第二贯穿电极。多个导电凸块置于第一半导体芯片与第二半导体芯片之间，并且将第一贯穿电极和第二贯穿电极彼此电连接。填充支撑层覆盖第二半导体芯片的面对第一半导体芯片的第一表面，并且填充导电凸块之间的空间。粘合层设置在填充支撑层上，并且填充导电凸块之间的所述空间并将第一半导体芯片和第二半导体芯片彼此粘附。
根据本公开的示例性实施例，半导体封装件包括包含第一基底的第一半导体芯片，第一基底具有第一表面以及与第一表面背对的第二表面。第一结合垫设置在第一表面上。第一贯穿电极穿透通过第一基底并电连接到第一结合垫。第二半导体芯片堆叠在第一半导体芯片的第二表面上，并且包括具有第三表面以及与第三表面背对的第四表面的第二基底。第三结合垫设置在第三表面上。第二贯穿电极穿透通过第二基底并电连接到第三结合垫。多个导电凸块置于第一半导体芯片与第二半导体芯片之间并且将第一贯穿电极和第二贯穿电极彼此电连接。间隙填充材料层设置在第一半导体芯片与第二半导体芯片之间以填充导电凸块之间的空间。间隙填充材料层包括至少部分地覆盖第二半导体芯片的面对第一半导体芯片的前侧的第一材料的填充支撑层和粘附到填充支撑层的第二材料的粘合层。
根据本公开的示例性实施例，半导体封装件包括封装件基底。第一半导体芯片堆叠在封装件基底上，并且包括具有第一表面以及与第一表面背对的第二表面的第一基底。第一结合垫设置在第一表面上。第一贯穿电极穿透通过第一基底并电连接到第一结合垫。多个导电凸块分别布置在封装件基底的基底垫与第一半导体芯片的第一结合垫之间。填充支撑层涂覆在第一半导体芯片的第一表面上，并且覆盖导电凸块的侧表面。粘合层设置在填充支撑层上，至少部分地覆盖导电凸块的所述侧表面，并且将封装件基底和第一半导体芯片粘合。
根据本公开的示例性实施例，在制造半导体封装件的方法中，提供在其第一表面上具有第一结合垫的第一基底。分别在第一基底的第一结合垫上形成凸块。在第一基底的第一表面上形成填充支撑层以填充凸块之间的空间。在填充支撑层上涂覆粘合层。研磨第一基底的与第一表面背对的第二表面。使用粘合层将第一基底粘附到第二基底。
根据本公开的示例性实施例，半导体封装件可以包括顺序地堆叠在封装件基底上的至少两个第一半导体芯片和第二半导体芯片。第一半导体芯片和第二半导体芯片可以经由第一导电凸块和第二导电凸块被堆叠。具有不同材料的双层结构的间隙填充材料层可以分别填充在封装件基底与第一半导体芯片之间以及在第一半导体芯片与第二半导体芯片之间。间隙填充材料层可以分别完全填充第一导电凸块中的相邻凸块之间的空间以及第二导电凸块中的相邻凸块之间的空间。可选地，间隙填充材料层可以部分地填充这些空间。间隙填充材料层可以包括填充支撑层和粘合层。
填充支撑层可以分别填充第一导电凸块之间的空间以及第二导电凸块之间的空间，因此，可以研磨晶圆级芯片的背面，使得第一半导体芯片和第二半导体芯片相对薄。此外，由于第一导电凸块和第二导电凸块由于填充支撑层而相对薄，因此可以获得相对薄的半导体封装件。
附图说明
通过以下结合附图进行的详细描述，将更清楚地理解本公开的示例性实施例及其许多伴随的方面，在附图中：
图1是示出根据本公开的示例性实施例的半导体封装件的剖视图；
图2是示出图1中的部分A的放大剖视图；
图3是示出图1中的部分B的放大剖视图；
图4是示出图1中的部分C的放大剖视图；
图5至图26是示出根据本公开的示例性实施例的制造半导体封装件的方法的剖视图；
图27A是示出根据比较实施例的堆叠在安装基底上的第一半导体芯片的剖视图；
图27B是示出根据本公开的示例性实施例的堆叠在安装基底上的第一半导体芯片的剖视图；以及
图28是示出根据本公开的示例性实施例的半导体封装件的剖视图。
具体实施方式
在下文中，将参照附图详细地解释本公开的示例性实施例。
图1是示出根据本公开的示例性实施例的半导体封装件的剖视图。图2是示出图1中的部分A的放大剖视图。图3是示出图1中的部分B的放大剖视图。图4是示出图1中的部分C的放大剖视图。
参照图1至图4，半导体封装件10可以包括堆叠的半导体芯片。半导体封装件10可以包括封装件基底500、第一半导体芯片至第四半导体芯片100、200、300、400和模制构件600。另外，半导体封装件10还可以包括电连接封装件基底500和第一半导体芯片至第四半导体芯片100、200、300、400的第一导电凸块至第四导电凸块160、260、360、460和外连接构件530。
封装件基底500可以包括包含设置在其中/其上的电路图案的印刷电路板(PCB)。第一绝缘层图案512可以设置在封装件基底500的上表面上以暴露基底垫510。第二绝缘层图案522可以设置在封装件基底500的下表面上以暴露外连接垫520。诸如焊球的外连接构件530可以设置在外连接垫520上。
多个半导体芯片可以堆叠在封装件基底500的上表面上。在该实施例中，第一半导体芯片至第四半导体芯片100、200、300、400可以基本彼此相同或类似。因此，相同或同样的附图标记将用于指代相同或同样的元件，并且在省略了一些元件的详细描述方面来说，可以假设这些元件至少与在说明书中的其它地方已经描述的对应元件类似。
第一半导体芯片至第四半导体芯片100、200、300、400可以堆叠在封装件基底500上。在该实施例中，半导体封装件被描绘为包括四个堆叠的半导体芯片100、200、300、400的多芯片封装件。然而，半导体封装件可以具有堆叠在其上的不同数量的半导体芯片，诸如两个堆叠的半导体芯片、三个堆叠的半导体芯片或多于四个堆叠的半导体芯片。
例如，半导体封装件10可以包括HBM(高带宽存储器)器件。半导体封装件10可以包括作为缓冲器裸片的第一半导体芯片100和顺序地堆叠在第一半导体芯片100上的作为存储器裸片的第二半导体芯片至第四半导体芯片200、300、400。第一半导体芯片至第四半导体芯片100、200、300、400可以通过硅通孔(TSV)彼此电连接。
第一半导体芯片100可以经由第一导电凸块160安装在封装件基底500上。第一半导体芯片100可以包括第一基底110、层间绝缘层120、第一结合垫(pad，或称为“焊盘”或“焊垫”)130、第一贯穿电极140和第二结合垫150。
第一基底110可以包括彼此背对的第一表面和第二表面。第一表面可以是有源表面，第二表面可以是非有源表面。各种电路图案可以设置在第一基底110的第一表面中。例如，第一基底110可以是单晶硅基底。电路图案可以包括晶体管、二极管等。电路图案可以构成电路元件。因此，第一半导体芯片100可以是包括形成在其中的多个电路元件的半导体器件。
层间绝缘层120可以设置在第一基底110的第一表面上。层间绝缘层120可以包括多个绝缘层120a、120b、120c、120d、120e和绝缘层中的布线122。第一结合垫130可以设置在层间绝缘层120中的最外面的绝缘层120e中。电路图案可以通过布线122电连接到第一结合垫130。
例如，布线122可以包括分别设置在绝缘层120a、120b、120c、120d、120e中的第一金属布线122a、第一接触件122b、第二金属布线122c、第二接触件122d和第三金属布线130。第三金属布线130的至少一部分可以用作第一结合垫130和/或用作着陆垫。因此，这里第三金属布线和第一结合垫两者可以由数字130表示。
可以示例性地示出包括两个金属布线层122a、122c的层间绝缘层120，并且将理解的是，在使用中可以存在少于或多于两个金属布线层。例如，层间绝缘层120可以是BEOL(线的后端)金属布线层，并且可以包括三个或更多个金属布线层。
第一贯穿电极140可以从第一基底110的第二表面延伸到第一表面以穿透通过第一基底110。第一贯穿电极140的端部可以与层间绝缘层120的第一金属布线122a进行接触。然而，本发明可以使用替代的互连方式，例如，第一贯穿电极140可以穿透通过层间绝缘层120以与第一结合垫130进行接触。
具有第二结合垫150的绝缘层152可以设置在第一基底110的第二表面上。第二结合垫150可以与第一贯穿电极140的另一端部进行接触。
在本公开的示例性实施例中，第一半导体芯片100可以经由第一导电凸块160安装在封装件基底500上。第一半导体芯片100可以布置在封装件基底500上，使得第一半导体芯片100的第一结合垫130面向封装件基底500的基底垫510。
第一导电凸块160可以置于封装件基底500与第一半导体芯片100之间。第一导电凸块160可以将封装件基底500的基底垫510和第一半导体芯片100的第一结合垫130彼此电连接。
在本公开的示例性实施例中，具有不同材料的双层结构的间隙填充材料层可以设置在封装件基底500与第一半导体芯片100之间。间隙填充材料层可以设置为完全填充第一导电凸块160中的相邻凸块之间的空间。可选地，间隙填充材料层可以部分地填充这些空间。间隙填充材料层可以包括填充支撑层170和粘合层180。
填充支撑层170可以涂覆在第一半导体芯片100的面对封装件基底500的前侧上，以至少部分地覆盖第一导电凸块160的侧表面。填充支撑层170可以覆盖第一导电凸块160的上部和中部的侧表面。第一导电凸块160的下部的一部分可以从填充支撑层170突出。
填充支撑层170可以包括能够在晶圆背面研磨工艺期间防止晶圆的翘曲的绝缘材料。填充支撑层170可以具有与第一基底110的材料(例如，硅)的热膨胀系数相同或类似的热膨胀系数。例如，填充支撑层170可以包括诸如环氧树脂、光敏聚酰亚胺等的聚合物材料。
粘合层180可以设置在填充支撑层170上以填充第一导电凸块160之间的空间。粘合层180可以至少部分地覆盖第一导电凸块160的从填充支撑层170突出的下部的侧表面。
例如，粘合层180可以包括非导电膜(NCF)。可以通过芯片结合设备的热压缩使第一结合垫130上的焊料凸块回流以形成第一导电凸块160，并且可以通过粘合层180将第一半导体芯片100粘附在封装件基底500上。
填充支撑层170可以具有第一厚度T1，并且粘合层180可以具有比第一厚度T1小的第二厚度T2。例如，填充支撑层170可以具有第一导电凸块160的总厚度的50％至90％的厚度。
第二半导体芯片200可以经由第二导电凸块260安装在第一半导体芯片100上。类似于第一半导体芯片100，第二半导体芯片200可以包括第二基底210、层间绝缘层、第一结合垫230、第二贯穿电极240和第二结合垫250。
第二半导体芯片200可以布置在第一半导体芯片100上，使得第二半导体芯片200的第一结合垫230面向第一半导体芯片100的第二结合垫150。
第二导电凸块260可以置于第一半导体芯片100与第二半导体芯片200之间。第二导电凸块260可以将第一半导体芯片100的第二结合垫150和第二半导体芯片200的第一结合垫230彼此电连接。
在本公开的示例性实施例中，具有不同材料的双层结构的间隙填充材料层可以设置在第一半导体芯片100与第二半导体芯片200之间。间隙填充材料层可以设置为完全填充第二导电凸块260中的相邻导电凸块之间的空间。可选地，间隙填充材料层可以部分地填充第二导电凸块260的相邻凸块之间的空间。间隙填充材料层可以包括填充支撑层270和粘合层280。
填充支撑层270可以涂覆在第二半导体芯片200的面对第一半导体芯片100的前侧上，以至少部分地覆盖第二导电凸块260的侧表面。填充支撑层270可以覆盖第二导电凸块260的上部和中部的侧表面。第二导电凸块260的下部的一部分可以从填充支撑层270突出。
粘合层280可以设置在填充支撑层270上以填充第二导电凸块260中的相邻凸块之间的空间。粘合层280可以覆盖第二导电凸块260的从填充支撑层270突出的下部的侧表面。例如，粘合层280可以包括非导电膜(NCF)。
填充支撑层270可以具有第一厚度，并且粘合层280可以具有比第一厚度小的第二厚度。例如，填充支撑层270可以具有第二导电凸块260的总厚度的50％至90％的厚度。
第三半导体芯片300可以经由第三导电凸块360安装在第二半导体芯片200上。类似于第一半导体芯片100和第二半导体芯片200，第三半导体芯片300可以包括第三基底310、层间绝缘层、第一结合垫330、第三贯穿电极340和第二结合垫350。
第三半导体芯片300可以布置在第二半导体芯片200上，使得第三半导体芯片300的第一结合垫330面向第二半导体芯片200的第二结合垫250。
第三导电凸块360可以置于第二半导体芯片200与第三半导体芯片300之间。第三导电凸块360可以将第二半导体芯片200的第二结合垫250和第三半导体芯片300的第一结合垫330彼此电连接。
在本公开的示例性实施例中，具有不同材料的双层结构的间隙填充材料层可以设置在第二半导体芯片200与第三半导体芯片300之间。间隙填充材料层可以设置为完全填充第三导电凸块360中的相邻凸块之间的空间。可选地，间隙填充材料层可以部分地填充第三导电凸块360中的相邻凸块之间的空间。间隙填充材料层可以包括填充支撑层370和粘合层380。
填充支撑层370可以涂覆在第三半导体芯片300的面对第二半导体芯片200的前侧上，以至少部分地覆盖第三导电凸块360的上部和中部的侧表面。第三导电凸块360的下部的一部分可以从填充支撑层370突出。
粘合层380可以设置在填充支撑层370上，以至少部分地覆盖第三导电凸块360的从填充支撑层370突出的下部的侧表面。例如，粘合层380可以包括非导电膜(NCF)。
填充支撑层370可以具有第一厚度，并且粘合层380可以具有比第一厚度小的第二厚度。例如，填充支撑层370可以具有第三导电凸块360的总厚度的50％至90％的厚度。
第四半导体芯片400可以经由第四导电凸块460安装在第三半导体芯片300上。第四半导体芯片400可以包括第四基底410、层间绝缘层和第一结合垫430。与第一半导体芯片至第三半导体芯片100、200、300不同，第四半导体芯片400可以不包括硅通孔。
第四半导体芯片400可以布置在第三半导体芯片300上，使得第四半导体芯片400的第一结合垫430面向第三半导体芯片300的第二结合垫350。
第四导电凸块460可以置于第三半导体芯片300与第四半导体芯片400之间。第四导电凸块460可以将第三半导体芯片300的第二结合垫350和第四半导体芯片400的第一结合垫430彼此电连接。
在本公开的示例性实施例中，具有不同材料的双层结构的间隙填充材料层可以设置在第三半导体芯片300与第四半导体芯片400之间。间隙填充材料层可以设置为完全填充第四导电凸块460中的相邻凸块之间的空间。可选地，间隙填充材料层可以部分地填充这些空间。间隙填充材料层可以包括填充支撑层470和粘合层480。
填充支撑层470可以涂覆在第四半导体芯片400的面对第三半导体芯片300的前侧上，以至少部分地覆盖第四导电凸块360的上部和中部的侧表面。第四导电凸块460的下部的一部分可以从填充支撑层470突出。
粘合层480可以设置在填充支撑层470上，以至少部分地覆盖第四导电凸块460的从填充支撑层470突出的下部的侧表面。例如，粘合层480可以包括非导电膜(NCF)。
填充支撑层470可以具有第一厚度，并且粘合层480可以具有比第一厚度小的第二厚度。填充支撑层470可以具有第四导电凸块460的总厚度的50％至90％的厚度。
模制构件600可以设置在封装件基底500上以至少部分地覆盖第一半导体芯片至第四半导体芯片100、200、300、400。模制构件600可以包括环氧树脂模制料(EMC)材料。
如上所述，多芯片封装件可以包括堆叠在封装件基底500上的至少两个第一半导体芯片100和第二半导体芯片200。第一半导体芯片100可以经由第一导电凸块160安装在封装件基底500上。第二半导体芯片200可以经由第二导电凸块260安装在第一半导体芯片100上。具有不同材料的双层结构的间隙填充材料层可以分别填充在封装件基底500与第一半导体芯片100之间以及在第一半导体芯片100与第二半导体芯片200之间。间隙填充材料层可以分别完全填充第一导电凸块160中的相邻凸块之间的空间以及第二导电凸块260中的相邻凸块之间的空间。可选地，间隙填充材料层可以部分地填充这些空间。间隙填充材料层可以包括填充支撑层170、270和粘合层180、280。
填充支撑层170、270可以设置在第一半导体芯片100的前侧和第二半导体芯片200的前侧上，以分别填充第一导电凸块160中的相邻凸块之间的空间以及第二导电凸块260中的相邻凸块之间的空间。因此，晶圆级芯片的背面可以被研磨，使得第一半导体芯片100和第二半导体芯片200相对薄。此外，随着第一导电凸块160和第二导电凸块260由于填充支撑层170、270而在高度上相对薄，所以在封装件基底500与第一半导体芯片100之间的间隙以及在第一半导体芯片100与第二半导体芯片200之间的间隙可以减小。
因此，可以获得更薄的半导体封装件。
在下文中，将解释制造图1中的半导体封装件的方法。
图5至图26是示出根据本公开的示例性实施例的制造半导体封装件的方法的剖视图。图6至图10是示出图5中的部分D的放大剖视图。图23是示出图22中的部分E的放大剖视图。图26是示出图25中的部分F的放大剖视图。
参照图5至图11，首先，可以在第一晶圆W1的第一结合垫230上形成凸块32。
在本公开的示例性实施例中，第一晶圆W1可以包括基底210、层间绝缘层220、第一结合垫230和贯穿电极240。可以在基底210的有源表面上设置层间绝缘层220。可以在层间绝缘层220的最外面的绝缘层220e中设置第一结合垫230。基底210可以包括形成有电路图案和单元的裸片区DA和至少部分地围绕裸片区DA的划线区SA。如稍后将更详细地描述的，第一晶圆W1的基底210可以沿着划分多个裸片区DA的划线区SA被锯切。
例如，基底210可以包括硅、锗、硅-锗或III-V化合物，例如GaP、GaAs、GaSb等。在本公开的一些示例性实施例中，基底210可以是绝缘体上硅(SOI)基底或绝缘体上锗(GOI)基底。
可以在基底210的有源表面中/上设置电路图案。电路图案可以包括诸如晶体管、二极管等的各种电路元件。
可以在基底210的有源表面上设置层间绝缘层220。层间绝缘层220可以包括多个绝缘层220a、220b、220c、220d、220e和绝缘层中的布线222。布线222可以包括分别设置在绝缘层220a、220b、220c、220d、220e中的第一金属布线222a、第一接触件222b、第二金属布线222c、第二接触件222d和第三金属布线230。第三金属布线230的至少一部分可以像着陆垫一样用作第一结合垫。第一结合垫230可以设置在第一晶圆W1的前侧中，在下文中，为了简化说明，第一晶圆W1的前侧被称为基底210的第一表面212。
可以设置贯穿电极240以穿透通过基底210。贯穿电极240可以通过层间绝缘层220的布线222电连接到第一结合垫230。可以在研磨基底210的背面(例如，如图16中所示的第二表面214)之前形成贯穿电极240(过孔第一工艺，过孔中间工艺)。可选地，如图16中所示，可以在研磨基底210的背面之后形成贯穿电极(过孔最后工艺)。
在本公开的示例性实施例中，可以在第一结合垫230上形成凸块32。
如图6中所示，可以在基底210的第一表面212上形成绝缘层图案20以暴露第一结合垫230，此后，可以在第一结合垫230上形成种子层22。
例如，绝缘层图案20可以包括氧化物、氮化物等。这些可以单独使用或以其混合物使用。另外，可以通过化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺、低压化学气相沉积(LPCVD)工艺、溅射工艺等形成绝缘层图案20。可选地，绝缘层图案20可以包括通过旋涂工艺或喷射工艺形成的聚合物层。在用于暴露第一结合垫230的保护层图案形成在基底210的第一表面212上的情况下，可以省略形成绝缘层图案20的工艺。
种子层22可以包括包含钛/铜(Ti/Cu)、钛/钯(Ti/Pd)、钛/镍(Ti/Ni)，铬/铜(Cr/Cu)或其组合的合金层。
然后，如图7中所示，可以在基底210的第一表面212上形成光致抗蚀剂图案24以具有至少部分地暴露种子层22的区域的开口。
如图8至图10中所示，可以在基底210的第一结合垫230上形成凸块32。
具体地，可以形成导电材料30以填充光致抗蚀剂图案24的开口，可以去除光致抗蚀剂图案24，然后，可以执行回流工艺以形成凸块32。例如，可以通过电镀工艺在种子层22上形成导电材料30。可选地，可以通过丝网印刷工艺、沉积工艺等形成凸块32。
凸块32可以具有距基底210的第一表面212的第一高度H1。例如，凸块32的第一高度H1可以在50μm至150μm的范围内。
参照图12至图17，可以在基底210的第一表面212上形成填充支撑层270，然后，可以研磨基底210的背面，例如，第二表面214。
如图12和图13中所示，在将填充支撑层270形成在基底210的第一表面212上以至少部分地覆盖凸块32之后，可以去除填充支撑层270的上表面以暴露凸块32。
然后，可以去除填充支撑层270的上部以暴露凸块32。可以通过研磨工艺、蚀刻工艺等去除填充支撑层270的一部分。这里，可以去除凸块32的上部以形成第二凸块34。因此，第二凸块34的高度H2可以小于凸块32的高度H1。因此，随着凸块的高度减小，在半导体芯片和晶圆之间的间隙或者在半导体芯片和半导体芯片之间的间隙减小，从而获得相对薄的封装件。
可以在基底210的第一表面212上形成填充支撑层270，以完全在填充凸块32中的相邻凸块之间的空间。可选地，填充支撑层270可以部分地填充这些空间。填充支撑层270可以包括能够在晶圆背面研磨工艺期间防止晶圆的翘曲的绝缘材料。
然后，如图14中所示，可以在基底210的第一表面212上的填充支撑层270上形成粘合层280。
例如，粘合层280可以包括非导电膜(NCF)。因此，在将与第一晶圆W1单独分开的基底210粘附在另一晶圆上或者半导体芯片上的同时可以使用粘合层，其中凸块置于基底210与另一晶圆或半导体芯片之间。因此，如图22中所示，可以在将基底210粘附在另一晶圆(或半导体芯片)上之前在填充支撑层270上形成粘合层280。
然后，如图15和图16中所示，可以使用基底支撑系统WSS研磨基底210的背面(例如，第二表面214)。在将第一晶圆W1布置在载体基底C上之后，可以研磨基底210的第二表面214。可以将基底210的第一表面212上的填充支撑层270粘附在载体基底C上的结合层G上。
可以通过研磨工艺来研磨基底210的第二表面214。这里，通过可完全填充第二凸块34中的相邻凸块之间的空间的填充支撑层270可以将基底210研磨得相对薄。例如，填充支撑层270可以防止第一晶圆W1在研磨工艺期间的翘曲，因此，可以在相同条件下使用基底支撑系统将基底210的背面研磨得相对薄。
参照图17，可以在基底210的第二表面214上形成第二结合垫250。
可以在基底210的第二表面214上形成具有第二结合垫250的绝缘层252。第二结合垫250可以形成在贯穿电极240的一个端部上。
在通过过孔最后工艺形成贯穿电极的情况下，可以在形成贯穿电极时或之后执行形成第二结合垫250的步骤。
参照图18，可以从基底210去除载体基底C，并且可以沿着划线区SA锯切第一晶圆W1，使得可以将基底210划分成单独的第二半导体芯片200。
参照图19，可以对第二晶圆执行与参照图5至图18描述的工艺相同或类似的工艺，以形成单独的第三半导体芯片300。
第三半导体芯片300可以包括基底310、分别设置在基底310的第一表面和第二表面上的第一结合垫330和第二结合垫350。贯穿电极340穿透通过基底310。第二凸块34设置在基底310上的第一垫330上。填充支撑层370填充在基底310的第一表面上的第二凸块34中的相邻凸块之间的空间。粘合层380设置在填充支撑层370上。
参照图20，可以对第三晶圆执行与参照图5至图18描述的工艺相同或类似的工艺，以形成单独的第四半导体芯片400。
第四半导体芯片400可以包括基底410。第一结合垫430设置在基底410的第一表面上。第二凸块34设置在基底410上的第一结合垫430上。填充支撑层470填充在基底410的第一表面上的第二凸块34中的相邻凸块之间的空间。粘合层480设置在填充支撑层470上。第四半导体芯片400可以不包括硅通孔。
参照图21，可以对第四晶圆W4执行与参照图5至图17描述的工艺相同或类似的工艺，以在基底110的第一表面上形成填充相邻第二凸块34之间的空间的填充支撑层170、以研磨基底110的第二表面并且形成第二结合垫150。
参照图22和图23，可以在第四晶圆W4的基底110上堆叠第二半导体芯片200。
在本公开的示例性实施例中，可以使用诸如非导电膜的粘合层280将第二半导体芯片200粘附在第四晶圆W4上。例如，在芯片结合设备的台上布置第四晶圆W4之后，第二半导体芯片200可以被吸附在芯片结合设备的头部上，然后可以被热压缩到第四晶圆W4上。
如图23中所示，可以加热粘合层280并且可以使第二凸块34回流以在基底110的第二结合垫150与第二半导体芯片200的第一结合垫230之间形成(第二)导电凸块260。这里，可以在第二半导体芯片200的基底210的前侧上形成填充支撑层270，并且可以在填充支撑层270上形成粘合层280。
可以将填充支撑层270涂覆在第二半导体芯片200的面对第一半导体芯片100的基底110的前侧上，以至少部分地覆盖(第二)导电凸块260的侧表面。填充支撑层270可以覆盖(第二)导电凸块260的上部和中部的侧表面。(第二)导电凸块260的下部可以从填充支撑层270突出。
粘合层280可以填充在填充支撑层270上的(第二)导电凸块260中的相邻凸块之间的空间。粘合层280可以覆盖(第二)导电凸块260的从填充支撑层270突出的下部的侧表面。
填充支撑层270可以具有第一厚度T1，粘合层280可以具有比第一厚度T1小的第二厚度T2。填充支撑层270可以具有(第二)导电凸块260的总厚度的50％至90％的厚度。
参照图24，可以执行与参照图22和图23描述的工艺相同或类似的工艺，以将第三半导体芯片300堆叠在第二半导体芯片200上并且将第四半导体芯片400堆叠在第三半导体芯片300上。
参照图25和图26，可以锯切第四晶圆W4，并且可以将堆叠的结构(堆叠的第一半导体芯片至第四半导体芯片100、200、300和400)安装在封装件基底500上。可以执行与参照图22和图23描述的工艺相同或类似的工艺以将第一半导体芯片100堆叠在封装件基底500上。
在本公开的示例性实施例中，可以使用诸如非导电膜的粘合层180将第一半导体芯片100粘附在封装件基底500上。例如，在芯片结合设备的台上布置封装件基底500之后，包括第一半导体芯片100的堆叠结构可以被吸附在芯片结合设备的头部上，然后可以被热压缩到封装件基底500上。
如图26中所示，可以加热粘合层180并且可以使第二凸块34回流以在封装件基底500的基底结合垫510与第一半导体芯片100的第一结合垫130之间形成第一导电凸块160。这里，可以在第一半导体芯片100的基底110的前侧上形成填充支撑层170，并且可以在填充支撑层170上形成粘合层180。填充支撑层170可以填充相邻导电凸块160之间的空间。填充支撑层170的厚度可以比粘合层180的厚度大。
然后，可以在封装件基底500的上表面上形成模制构件，以至少部分地覆盖第一半导体芯片至第四半导体芯片100、200、300、400，然后可以在封装件基底500的下表面上的外连接垫520上设置外连接构件530，以完成图1中的半导体封装件10。
在下文中，将解释根据比较实施例的堆叠的半导体芯片的厚度和根据本公开的示例性实施例的堆叠的半导体芯片的厚度。
图27A是示出根据比较实施例的堆叠在安装基底上的第一半导体芯片的剖视图，图27B是示出根据本公开的示例性实施例的堆叠在安装基底上的第一半导体芯片的剖视图。
参照图27A，可以执行与参照图5至图11描述的工艺相同或类似的工艺以在第一基底110的前侧上的第一结合垫130上形成凸块，并且使用基底支撑系统(WSS)研磨第一基底110的背面(例如，第二表面)。可以在将第一基底110的前侧粘附在载体基底上的同时执行研磨工艺。
然后，可以使用非导电膜180通过芯片结合工艺使凸块回流，以在封装件基底500的基底结合垫510与第一基底110的第一结合垫130之间形成导电凸块160。
在这种情况下，第一基底110可以具有第一厚度T1，封装件基底500和第一半导体芯片100可以通过第一间隙G1彼此间隔开。
参照图27B，可以执行与参照图5至图11描述的工艺相同或类似的工艺以在第一基底110的前侧上的第一结合垫130上形成凸块，并且可以执行与参照图12至图16描述的工艺相同或类似的工艺以在第一基底110的前侧上形成填充支撑层170并且研磨第一基底110的背面(例如，第二表面)。
可以在第一基底110的包括形成在第一基底110的前侧上的填充支撑层170的第二表面上执行研磨工艺。这里，填充支撑层170可以完全填充相邻凸块之间的空间以支撑第一基底110的前侧，因此，基底110可以被研磨得相对薄。例如，填充支撑层170可以防止晶圆在研磨工艺期间的翘曲，因此，可以在相同的条件下使用基底支撑系统将基底110的背面研磨得相对薄。
然后，可以使用非导电膜180通过芯片结合工艺使凸块回流，以在封装件基底500的基底结合垫510与第一基底110的第一结合垫130之间形成第一导电凸块160。
在这种情况下，第一基底110可以具有比第一厚度T1小的第二厚度T2，封装件基底500和第一半导体芯片100可以彼此间隔开比第一间隙G1小的第二间隙G2。
图28是示出根据本公开的示例性实施例的半导体封装件的剖视图。除了半导体器件的构造之外，半导体封装件可以与参照图1描述的半导体封装件基本相同或类似。因此，相同的附图标记可以用于指相同或同样的元件，并且在省略了一些元件的详细描述方面来说，可以假设这些元件至少与在说明书中的其它地方已经描述的对应元件类似。
参照图28，半导体封装件11可以包括封装件基底500、第一半导体器件60、至少一个第二半导体器件50a、50b和模制构件600。另外，半导体封装件11还可以包括外连接构件530。
在本公开的示例性实施例中，半导体封装件11可以是诸如系统级封装(SIP)的电子器件。第一半导体器件60可以是插入器，第二半导体器件50a、50b可以包括HBM(高带宽存储器)器件。可选地，第一半导体器件60可以包括诸如逻辑半导体器件的第一电子产品，第二半导体器件50a、50b可以包括诸如存储器器件的第二电子产品。
如图28中所示，第二半导体器件50a、50b可以如图1中所示包括彼此堆叠的第一半导体芯片至第四半导体芯片100、200、300、400。第一半导体芯片至第四半导体芯片100、200、300、400可以通过诸如硅通孔(TSV)的贯穿电极140、240、340彼此电连接。
第一半导体芯片100可以经由第一导电凸块160安装在第一半导体器件60上。第二半导体芯片200可以通过第二导电凸块260安装在第一半导体芯片100上。具有不同材料的双层结构的间隙填充材料层可以分别填充在第一半导体器件60与第一半导体芯片100之间以及在第一半导体芯片100与第二半导体芯片200之间。间隙填充材料层可以设置为分别完全填充第一导电凸块160中的每个之间的间隙以及在第二导电凸块260中的每个之间的间隙。可选地，间隙填充材料层可以部分地填充这些间隙。间隙填充材料层可以包括填充支撑层170、270和粘合层180、280。
填充支撑层170、270可以设置在第一半导体芯片100和第二半导体芯片200的前侧上，以分别填充相邻的第一导电凸块160之间的空间以及相邻的第二导电凸块260之间的空间，因此，可以研磨晶圆级芯片的背面，使得第一半导体芯片100和第二半导体芯片200相对薄。此外，随着第一导电凸块160和第二导电凸块260由于填充支撑层170、270而在高度上相对薄，第一半导体器件60与第一半导体芯片100之间的间隙以及在第一半导体芯片100与第二半导体芯片200之间的间隙可以减小。
因此，可以获得相对薄的半导体封装件。
半导体封装件可以应用于诸如计算系统的各种系统。半导体器件可以包括鳍式FET、DRAM、VNAND等。半导体封装件可以包括逻辑器件(诸如中央处理单元(CPU)、主处理单元(MPU)或应用处理器(AP))等、易失性存储器器件(诸如DRAM器件、SRAM器件)、非易失性存储器器件(诸如闪存器件、PRAM器件、MRAM器件、ReRAM器件或CMOS图像传感器(CIS))。
以上是对本公开的示例性实施例的说明，而不应理解为对本公开的限制。尽管在这里已经描述了本公开的一些示例性实施例，但是本领域技术人员将容易理解的是，在不实质上脱离本发明的新颖教导和方面的情况下，能够在示例性实施例中进行许多修改。

Claims (20)

1.一种半导体封装件，所述半导体封装件包括：
第一半导体芯片，包括第一贯穿电极；
第二半导体芯片，堆叠在第一半导体芯片上，并且包括第二贯穿电极；
多个导电凸块，置于第一半导体芯片与第二半导体芯片之间，所述多个导电凸块将第一贯穿电极和第二贯穿电极彼此电连接；
填充支撑层，至少部分地覆盖第二半导体芯片的面对第一半导体芯片的第一表面，并且至少部分地填充所述多个导电凸块中的相邻导电凸块之间的空间；以及
粘合层，设置在填充支撑层上并且至少部分地填充所述多个导电凸块中的相邻导电凸块之间的所述空间，并且将第一半导体芯片和第二半导体芯片彼此粘附。
2.根据权利要求1所述的半导体封装件，其中，填充支撑层至少部分地覆盖所述多个导电凸块中的每个导电凸块的上部和中部的侧表面，并且粘合层至少部分地覆盖所述多个导电凸块中的每个导电凸块的从填充支撑层突出的下部的侧表面。
3.根据权利要求1所述的半导体封装件，其中，填充支撑层具有第一厚度，并且粘合层具有比第一厚度小的第二厚度。
4.根据权利要求1所述的半导体封装件，其中，填充支撑层包括环氧树脂，并且粘合层包括非导电膜。
5.根据权利要求1至权利要求4中的任一项所述的半导体封装件，其中，第二半导体芯片包括位于第一表面上的第一结合垫和位于与第一表面背对的第二表面上的第二结合垫，并且所述多个导电凸块中的每个导电凸块设置在第一结合垫上。
6.根据权利要求5所述的半导体封装件，其中，第一结合垫和第二结合垫通过第二贯穿电极彼此电连接。
7.根据权利要求1至权利要求4中的任一项所述的半导体封装件，其中，第二半导体芯片还包括层间绝缘层，层间绝缘层包括位于其外表面中的第一结合垫。
8.根据权利要求1至权利要求4中的任一项所述的半导体封装件，所述半导体封装件还包括封装件基底，
其中，第一半导体芯片经由第二导电凸块安装在封装件基底上。
9.根据权利要求8所述的半导体封装件，所述半导体封装件还包括：
第二填充支撑层，至少部分地覆盖第一半导体芯片的面对封装件基底的第三表面，并且至少部分地填充第二导电凸块中的相邻凸块之间的空间；以及
第二粘合层，设置在第二填充支撑层上，并且至少部分地填充第二导电凸块中的相邻凸块之间的所述空间，并且将第一半导体芯片和封装件基底彼此粘附。
10.根据权利要求9所述的半导体封装件，其中，第一半导体芯片包括设置在第三表面上的第三结合垫和设置在与第三表面背对的第四表面上的第四结合垫，并且第二导电凸块设置在第三结合垫上。
11.一种半导体封装件，所述半导体封装件包括：
第一半导体芯片，包括：第一基底，包括第一表面以及与第一表面背对的第二表面；第一结合垫，设置在第一表面上；以及第一贯穿电极，穿透通过第一基底并电连接到第一结合垫；
第二半导体芯片，堆叠在第一半导体芯片的第二表面上，第二半导体芯片包括：第二基底，包括第三表面以及与第三表面背对的第四表面；第三结合垫，设置在第三表面上；以及第二贯穿电极，穿透通过第二基底并电连接到第三结合垫；
多个导电凸块，置于第一半导体芯片与第二半导体芯片之间并且将第一贯穿电极和第二贯穿电极彼此电连接；以及
间隙填充材料层，设置在第一半导体芯片与第二半导体芯片之间且至少部分地填充所述多个导电凸块中的相邻导电凸块之间的空间，并且包括至少部分地覆盖第二半导体芯片的面对第一半导体芯片的前侧的包含第一材料的填充支撑层和粘附在填充支撑层上的包含第二材料的粘合层。
12.根据权利要求11所述的半导体封装件，其中，填充支撑层至少部分地覆盖所述多个导电凸块中的每个导电凸块的上部和中部的侧表面，并且粘合层覆盖所述多个导电凸块中的每个导电凸块的从填充支撑层突出的下部的侧表面。
13.根据权利要求11所述的半导体封装件，其中，填充支撑层具有第一厚度，并且粘合层具有比第一厚度小的第二厚度。
14.根据权利要求11所述的半导体封装件，其中，填充支撑层包括环氧树脂材料，并且粘合层包括非导电膜。
15.根据权利要求11至权利要求14中的任一项所述的半导体封装件，其中，第一半导体芯片包括设置在第二表面上的第二结合垫，并且所述多个导电凸块中的每个导电凸块设置在第二结合垫与第三结合垫之间。
16.根据权利要求11至权利要求14中的任一项所述的半导体封装件，其中，第二半导体芯片包括位于第四表面上的第四结合垫，并且第三结合垫和第四结合垫通过第二贯穿电极彼此电连接。
17.根据权利要求11至权利要求14中的任一项所述的半导体封装件，其中，第二半导体芯片还包括层间绝缘层，层间绝缘层包括位于其外表面中的所述第三结合垫。
18.根据权利要求11至权利要求14中的任一项所述的半导体封装件，所述半导体封装件还包括封装件基底，
其中，第一半导体芯片经由多个第二导电凸块安装在封装件基底上。
19.根据权利要求18所述的半导体封装件，所述半导体封装件还包括：
第二填充支撑层，至少部分地覆盖第一半导体芯片的面对封装件基底的前侧，并且至少部分地填充所述多个第二导电凸块中的相邻导电凸块之间的空间；以及
第二粘合层，设置在第二填充支撑层上，并且至少部分地填充所述多个第二导电凸块中的相邻导电凸块之间的所述空间，并且将第一半导体芯片和封装件基底彼此粘附。
20.一种半导体封装件，所述半导体封装件包括：
封装件基底；
第一半导体芯片，堆叠在封装件基底上，第一半导体芯片包括：第一基底，包括第一表面以及与第一表面背对的第二表面；第一结合垫，位于第一表面上；以及第一贯穿电极，穿透通过第一基底并电连接到第一结合垫；
多个导电凸块，分别布置在封装件基底的基底垫与第一半导体芯片的第一结合垫之间；
填充支撑层，涂覆在第一半导体芯片的第一表面上，并且至少部分地覆盖所述多个导电凸块中的每个导电凸块的侧表面；以及
粘合层，设置在填充支撑层上并且至少部分地覆盖所述多个导电凸块中的每个导电凸块的所述侧表面，并且将封装件基底和第一半导体芯片彼此粘附。
CN202010835756.3A 2019-09-11 2020-08-19 包括导电凸块的半导体封装件 Pending CN112490198A (zh)

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