TWI517324B - 具較佳機械和熱機械效能的銲錫凸塊內連線 - Google Patents

具較佳機械和熱機械效能的銲錫凸塊內連線 Download PDF

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TWI517324B
TWI517324B TW097114880A TW97114880A TWI517324B TW I517324 B TWI517324 B TW I517324B TW 097114880 A TW097114880 A TW 097114880A TW 97114880 A TW97114880 A TW 97114880A TW I517324 B TWI517324 B TW I517324B
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Taiwan
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pad
bump
polymer layer
layer
semiconductor package
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TW097114880A
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TW200901413A (en
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阿瓦拉多雷能坦
陸原
瑞柏恩理查
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飛立帕奇帕國際股份有限公司
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Description

具較佳機械和熱機械效能的銲錫凸塊內連線
本發明內容有關於晶圓級晶片電子封裝技術(electronic wafer level chip scale packaging)以及覆晶封裝技術(flip chip packaging)與組件，更明確而言，係提供一種具有改良機械強度與耐衝擊性的焊料凸塊連線結構。
傳統上使用焊線接合(wire bonding)來提供半導體裝置之間的電性連接以及外部電路。在晶圓上製造出半導體裝置後，將半導體裝置從晶圓上切割下來，並且以面朝上的方式來封裝。隨後，在半導體裝置上的焊墊與封裝上的外引線(leads)之間焊接通常是金或銅材質的細小電線。
覆晶技術的名稱是從其封裝過程是使半導體裝置面朝下進行封裝而得名。並且藉著使導電焊料凸塊在半導體裝置表面上迴焊(reflowing)來達成半導體裝置與封裝外引線之間的電性連接。
在覆晶技術中，由於半導體裝置的整個面積都可用來形成焊墊(bond pad)，因而允許製造更大數量的電性連結，其中連接在焊墊上的線路通常形成在半導體裝置的周圍。覆晶技術亦可減少除焊線接合的電阻與電容而有利於在半導體裝置與外部電路之間形成更快速的電性連結。
晶圓級晶片封裝(WLCSP)或晶圓級封裝(WLP)技術藉著在半導體裝置製造過程中直接在半導體裝置上形成電性 連接，使得覆晶技術更向前推進。此進步允許將半導體裝置直接安裝在印刷電路板上(PCB)，而可省略掉單獨封裝的需求。完成封裝後的裝置尺寸類似於未封裝的半導體裝置尺寸。晶圓級晶片封裝將可獲得提高電子效能以及更小封裝尺寸的益處。在工業中，晶圓級晶片封裝從含鉛焊料冶金技術(solders with lead metallurgy)到無鉛冶金技術(non-lead metallurgies)的轉變，讓高可靠性晶片封裝較容易受冷熱交替與意外機械性衝擊影響。
重分佈層(RDL)技術允許較舊型的半導體裝置設計使用晶圓級晶片封裝，其焊墊係位在半導體裝置的周圍。重分佈層技術可在半導體裝置上的焊墊與焊料凸塊之間形成一電性路徑，並允許焊料凸塊平均地分佈在半導體裝置的整個表面區域上。
第1圖顯示在設置焊料凸塊前，位在裝置墊上的習知輸入輸出上覆凸塊結構(bump on IO structure)，第2A圖則顯示第1圖之IO上覆凸塊結構設置焊料凸塊106後的情形。該裝置含有基板101、裝置墊102以及鈍化層103。裝置墊102是金屬材料，典型包括鋁、銅或兩者的複合物。可使用任一種工業上常用的已知方法來形成該裝置墊102。基板101可能包括多種材料，例如矽(Silicon)、砷化鎵(Gallium Arsenide)、鉭酸鋰(Lithium Tantalate)、矽鍺(Silicon Germanium)或其他材料。為了方便清楚說明，在本文中，基板材料大體上是指矽，但不應將其解釋為本發明內容僅限於矽系基板。
裝置鈍化層103典型包含氮化矽或氮氧化物等材料。鈍化層103非連續地覆蓋在該裝置墊上，而是定義有多個開口並將該等開口個別稱為鈍化開口，在該些開口中沒有鈍化材料。第2圖為第1圖之IO上覆凸塊結構的俯視圖中，其示出鈍化開口的細節。鈍化開口通常為圓形並且同心地設置在裝置墊102上。鈍化開口定義出一個將於覆晶封裝或WLCSP後續製程中用以沉積金屬以製造連線且黏結至裝置墊的區域。
用來設置如第1與2圖所示之IO上覆凸塊結構的習知技術包括使用諸如金屬電鍍、金屬濺射等標準金屬沉積方法來形成凸塊下方金屬墊(UBM)105。凸塊下方金屬墊105可包含任意數目的已知材料，包括鈦(鎢)/銅(Ti(W)/Cu)、鋁/化學鍍鎳/金(Al/ElectroleSS Ni/Immersion Au)、鋁/化學鍍鎳/鈀金(Al/Electroless Ni/PdIAu)、鋁銅/化學鍍鎳/金(AlCu/ Electroless Ni/Immersion Au)、鋁銅矽/化學鍍鎳/金(AlCuSi/Electroless Ni/Immersion Au)及鋁矽/化學鍍鎳/金(AlSi/Electroless Ni/Immersion Au)。依據所使用的材料與技術，凸塊下方金屬墊105能黏附鈍化材料103與裝置墊102，並且通常形成約1.0微米或更厚的膜層。凸塊下方金屬墊105的上表面提供設置焊料凸塊的位置，並且有幫助焊料凸塊黏著。在第1與2圖中，聚合物104中的開孔定義出該UBM焊料凸塊位置。
傳統製程使用的聚合物材料係如聚醯亞胺(polyimide)、苯并環丁烯(benzocyclobutene，BCB)或類似 物。聚合物104的厚度典型約10微米或更薄。通常利用光學定義技術來定義聚合物104以創造出開口，該些開口通常為圓形並且同心地設置在凸塊下方金屬墊105上。在此範例以及多數的習知焊料凸塊結構中，裝置墊102的直徑大於或等於該凸塊下方金屬墊105的直徑，且兩者的比例約1：1或更大。在此種習知的焊料凸塊結構中，聚合物104中的開口直徑通常小於該凸塊下方金屬墊105的直徑，且其比例為0.86：1或更小。
第3與4圖分別顯示另一種習知IO上覆凸塊結構的剖面圖與俯視圖。在此習知範例中，裝置墊302的直徑小於該凸塊下方金屬墊305的直徑，且其比例為0.43：1。聚合物開口直徑小於該凸塊下方金屬墊305的直徑，且其比例典型為0.32：1。用於設置如第3與4圖所示之下層結構的習知技術包括在裝置鈍化層303及裝置墊302上設置聚合物304，該聚合物304係如聚醯亞胺、苯并環丁烯、聚苯并噁唑(polybenzoxazole)衍生物或其類似物等。聚合物304的厚度典型為10微米或更小。隨後光學定義該聚合物304以創造出開口，該些開口通常為圓形且同心地設置在該裝置鈍化開口上，並且打開至該裝置墊302的表面。
在製程的此階段時，聚合物304已定義出一用來連接至裝置鈍化層303的區域，並且該區域位在裝置鈍化層303中的開口內。聚合物304的開口區域稱為聚合物開口。一但定義好該聚合物開口時，利用諸如金屬電鍍、金屬濺射沉積等標準方法或類似方法來沉積該凸塊下方金屬墊 305。此步驟形成凸塊下方金屬墊305，並且凸塊下方金屬墊305的底部會黏附至聚合物304，黏附至裝置鈍化層303介於聚合物304與裝置墊302之間的任何暴露部分，以及黏附至裝置墊302本身。凸塊下方金屬墊305的頂面則定義為用來設置與黏著焊料凸塊的表面。
在此結構與多數的下層焊料凸塊結構中，裝置墊302的直徑小於凸塊下方金屬墊305的直徑，且其比例典型為0.43：1。此種比例讓凸塊下方金屬墊305大幅重疊在裝置墊302上。此外，聚合物304中的開口直徑通常小於凸塊下方金屬墊305的直徑，且其比例點行為0.32：1。
第5與6圖顯示一示範性習知重分佈層(RDL)下層結構在形成焊料凸塊之前的剖面圖。第6A圖則顯示一示範性習知重分佈層(RDL)下層結構已形成焊料凸塊之後的剖面圖。第7圖為第5與6圖所示結構的俯視圖。使用該領域中所熟知的標準金屬沉積法來形成RDL線路505。RDL線路可以是單層金屬層或是多層金屬堆疊層，例如鈦/鋁/鈦、銅、鋁、銅鎳、鉻/銅/鉻或其他金屬層。在RDL線路505之末端處的金屬通常形成圓形圖案，而成為停靠墊505a。停靠墊505a提供了供後續WLCSP或覆晶封裝製程使用的連接點。停靠墊可以是單層金屬層或是多層金屬堆疊層，例如鋁、鋁/鎳/銅、鈦/鋁/鈦、銅、鎳/金/銅或其他金屬層。一但形成線路505與停靠墊505a，在該線路505與停靠墊505a上沉積已經過光學定義的聚合物2材料層506。隨後在該聚合物2材料層506中定義出開口，且該開 口位在停靠墊505a的中心區域中並且暴露出一部分的停靠墊505a。位在停靠墊中心外側的聚合物2材料層506保持完整且覆蓋住線路505。聚合物2材料層506的厚度典型為20微米或更小。凸塊下方金屬墊507形成在聚合物2材料層506上並且位於停靠墊505a上，以在凸塊下方金屬墊507和停靠墊505a之間形成電性連接。典型地，停靠墊505a的直徑大於或等於該凸塊下方金屬墊507的直徑。
傳統停靠墊直徑和UBM直徑的比例為1：1或更大。聚合物2的開口直徑與UBM直徑的比例典型為0.9：1或更大。第6A圖顯示重分佈層(RDL)上的典型焊料凸塊。
半導體工業的主要趨勢是尋求採用更小特徵尺寸的製程技術，以使半導體裝置可展現出更多功能。系統單晶片裝置(System－on－a－chip，SoC)是這類採用較小特徵尺寸所製成之半導體裝置的一個範例，並且可作為第3與4圖所示結構的示範。將第1－2圖與第3－4圖做比較顯示出，較小特徵尺寸合併更強大功能導致需要縮減輸入輸出墊(IO墊)的尺寸。在WLCSP應用領域中的最終IO墊幾何結構已明顯較小於所需要的焊料凸塊，因而在焊料凸塊與最終IO墊幾何結構之間創造出窄頸式結構。窄頸結構為焊料凸塊帶來不穩定性與不一致性，並使得焊料凸塊更容易受到溫度冷熱交替以及意外機械撞擊影響。
因此，需要一種改良的半導體封裝件，其可在諸如機 械性掉落測試、機械性衝擊或震盪測試、機械性剪力測試、冷熱交替循環測試、溫度衝擊測試等可靠度測驗以及其他半導體封裝件試驗法中(特別是使用硬焊料組成而非含鉛焊料組成來作為焊料凸塊時)展現增強機械性能與熱機械性能。本發明揭露內容係有關於一種焊料凸塊連線結構，其能實質解決先前技術領域中因技術限制與缺點所產生的一或多個問題。
本發明的額外特徵與優點將於以下說明內容中提出，或可從以下敘述內容了解本發明的部分優點與特徵，或是藉由實施本發明而習得。參閱本案申請專利範圍、所附圖式以及發明說明中所舉出的示範結構，將可了解且獲得本發明之其他目的與優點。
在本發明某些實施例中提供一種重分佈晶片封裝件，其具有一基板與一具有最終金屬墊尺寸的最終金屬墊。一裝置鈍化層沉積在該最終金屬墊上，並且該鈍化層具有一鈍化開口，在該開口中係局部移除鈍化層以暴露出下方的最終金屬墊。一聚合物層沉積在該鈍化層上，並且該聚合物層具有一聚合物開口，在該開口中係局部移除該聚合物以暴露出下方的最終金屬墊。一導電層沉積在該聚合物層上，並且圖案化該導電層以提供一線路圖案與停靠墊(landing pad)，該停靠墊具有一停靠墊長度。一聚合物層沉積在該導電層上且該聚合物層具有一聚合物層開口，在開口中，係局部移除聚合物以暴露出下方的停靠墊。一凸塊下金屬層沉積在該聚合物層上，並且該凸塊下金屬層具 有一最終凸塊下金屬尺寸與一凸塊下金屬凸出部(under bump metal overhang)。該聚合物開口直徑比上該最終凸塊下金屬層直徑的比例範圍約從0.35：1至約0.85：1。該停靠墊直徑比上該最終凸塊下金屬層直徑的比例範圍約從0.5：1至約0.95：1。在凸塊下金屬層與其他區域具有大致圓形幾何形狀的實施例中，以上所定義的長度相當於該凸塊下金屬層與其他區域的直徑。
在本發明某些實施例中提供一種IO上焊料凸塊晶片封裝件，其具有一基板與一具有最終金屬墊尺寸的最終金屬墊。一裝置鈍化層沉積在該最終金屬墊上，並且該鈍化層具有一鈍化開口，在該開口中係局部移除鈍化層以暴露出下方的最終金屬墊。一聚合物層沉積在該鈍化層上，並且該聚合物層具有一聚合物開口，在該開口中係局部移除該聚合物層以暴露出下方的最終金屬墊。一凸塊下金屬層沉積在該聚合物層上，並且該凸塊下金屬層具有一最終凸塊下金屬尺寸。該聚合物開口和該最終凸塊下金屬尺寸的比例範圍約從0.35：1至約0.85：1。該最終金屬墊尺寸和該最終凸塊下金屬尺寸的比例範圍約從0.5：1至約0.95：1。該鈍化開口和該最終凸塊下金屬尺寸的比例範圍約從0.35：1至約0.80：1。在凸塊下金屬層與其他區域具有大致圓形幾何形狀的實施例中，以上所定義的長度相當於該凸塊下金屬層與其他區域的直徑。
需明白的是，上述概要敘述與以下詳細說明內容皆為示範與說明本發明之用，目的是為本文所揭露具有良好熱 機械強度與掉落試驗性能的焊料凸塊連線結構提供進一步說明。
以下敘述內容與附圖顯示出多個特定實施例，其足以教示熟悉該項技術者實施本文中所揭示的系統與方法。然而，本發明還可具有包含結構、邏輯、製程或其他變化得其他實施例，並且該些實施例亦為本發明範圍所涵蓋。所示範例僅為典型的可行變化態樣。
以下說明用來實施本發明系統與方法不同實施例的多個元件。可使用已知的結構來建構多種元件。亦須了解到，可利用各種技術來實施本發明的系統與方法。
現下內容揭示一種具有改良熱機械強度與掉落測試性能之焊料凸塊內連線結構的數個特定實施例。半導體裝置封裝件通常是晶片規格封裝件或晶圓級封裝件，例如用於晶片直焊基板組件(chip－on－board assembly)或用於覆晶封裝用途的標準覆晶封裝件。此類的封裝件的實施方法範例描述於由Elenius等人於2002年8片27號申請且標題為「使用於大型軟焊球的晶片規格封裝」的美國專利6,441,487號、由Kata等人於1998年12月1號申請且標題為「製造半導體裝置與半導體晶圓之製程」的美國專利5,844,304號、由Higdon等人於1996年8月20號申請且標題為「用於覆晶積體電路裝置的可焊式接觸」的美國專利5,547,740號、由Higdon等人於2001年6月26號申請 且標題為「表面黏著電路裝置及其焊料凸塊設置方法」的美國專利6,251,501號以及由Vrtis等人於2005年10月28日申請且標題為「具有聚合物層上含凸塊之半導體裝置封裝」的PCT/U505/39008號專利申請案中，並且將該些文獻中有關於封裝應用、結構與製造方法的教示內容納入本文中以供參考。
本文中所揭露的連線結構能為習知製造技術帶來提高熱機械強度以及改善掉落測試性能的優點。本文中揭示一種理想的下層結構，其定義出UBM直徑、聚合物開口直徑、裝置鈍化開口的直徑以及裝置墊直徑。雖然在本文敘述內容中，UBM、聚合物開口、裝置鈍化開口及/或裝置墊是採用圓形幾何形狀，但是在不偏離本發明範圍或精神的情況下，也可使用其他幾何形狀來取代之。例如，在一實施例中，一或多個結構可採用方形幾何形狀，但並不僅限於此。在此種實施例中，該結構的邊長可取代相應的直徑。
第8與9圖示範一採用本文揭示比例的IO上覆凸塊結構。在第8與9圖中，裝置墊802之直徑與UBM 805之直徑的比例範圍從0.5：1至0.95：1。聚合物804中的開口直徑比上UBM 805之直徑的比例範圍從0.35：1至0.85：1。裝置鈍化層803中的開口直徑比上UBM 805之直徑的比例範圍從0.35：1至0.80：1。採用這些尺寸比例，此IO上覆凸塊結構允許熱應力與機械應力所帶來的力更平均地分佈至整個IO上覆凸塊結構，因而改善該結構在不利條件下的整體性能，該些不利條件將進一步敘述如下。
第10、11與12圖顯示一示範性重分佈層(RDL)下層結構。在第10至12圖中，停靠墊1005a的直徑比上UBM 1007之直徑的比例範圍從0.5：1至0.95：1。聚合物2層1006中的開口直徑比上UBM 1007之直徑的比例範圍從0.35：1至0.85：1。採用這些尺寸比例，此RDL下層結構允許熱應力與機械應力所帶來的力更平均地分佈至整個RDL下層結構，從而改善該結構在不利條件下的整體性能，該些不利條件將進一步敘述如下。
由於若該半導體裝置是一種攜帶式裝置，則該半導體裝置可能發生掉落情況，因此聯合電子裝置工程協會(JEDEC)測量標準JESD22－B111提供一種評估覆晶晶片或WLCSP晶片抵抗機械衝擊能力的方法。習知的WLCSP裝置在經歷過100次掉落以前就已故障。而本發明所揭示的各種實施例可使WLCSP裝置的掉落測試性能提高約200%以上，使得其能夠承受100次或更多次的掉落衝擊。
藉由實施本文中所述的元件幾何結構，此新穎的凸塊結構能提供增強的熱機械穩定度，並且提高整體結構吸收意外掉落所造成之衝擊的能力。例如，在溫度交替循環測試(TCT，錯誤率5%，可信度95%)中，熱機械穩定度可提高100%以上，並且在某些情況下可承受超過600次循環。JEDEC掉落測試性能提高超過100%。在使用JESDA104B測試方法對IO上覆凸塊實施例進行溫度交替循環測試的二級測試時，該新穎結構整體上表現出經歷600次以上的循環才出現第一次故障。類似地，在使用JESD22－B111標 準測試方法對IO上覆凸塊結構進行掉落測試時，該結構通過經歷800次掉落卻未發生故障。該重分佈凸塊結構通過使用JESDA104B測試方法進行1000次循環的溫度交替循環試驗的二級測試，並且該重分佈凸塊結構也通過使用JESD22－B111標準掉落試驗進行800次掉落的測試。
雖然以上說明了本發明多個特定的示範裝置與方法，但熟悉該項技術者應可了解到在其他實施例中可能可以重新安排及/或省略上述步驟中的多個步驟。上述有關特定實施例的敘述是用來說明本發明的整體本質，可在不偏離本發明整體概念下利用現有知識來修飾或變化上述實施例，使其適用於不同應用用途。例如，可使用額外的聚合物層與重分佈線路，以形成位於半導體晶圓上方的多層金屬層(例如可高達五層)。因此，此類修飾與變化態樣涵蓋在本文揭露實施例之等效物的範圍內。在本文中所使用的各種術語或用詞僅做說明目的，並非用來限制本發明。
101‧‧‧基板
102‧‧‧裝置墊
103‧‧‧鈍化層
104‧‧‧聚合物
105‧‧‧凸塊下方金屬墊
106‧‧‧焊料凸塊
505‧‧‧線路
505a‧‧‧停靠墊
506‧‧‧聚合物2材料層
507‧‧‧凸塊下方金屬墊
801‧‧‧矽
802‧‧‧裝置墊
803‧‧‧鈍化層
804‧‧‧聚合物1
805‧‧‧凸塊下方金屬
1005a‧‧‧停靠墊
1006‧‧‧聚合物2層
1007‧‧‧凸塊下方金屬墊
本說明書所附圖式係用以進一步了解本發明所揭示具有改良熱機械強度與改良掉落測試性能的焊料凸塊連線結構，該些附圖為本案說明書的一部分並且配合敘述內容來出示本發明多個實施例，以說明本發明具有改良熱機械強度與改良掉落測試性能之焊料凸塊連線結構至少一實施例的原理。該些圖式為：第1圖顯示在形成焊料凸塊之前，位於裝置墊上的習 知IO上覆凸塊結構；第2圖顯示第1圖之IO上覆凸塊結構的俯視圖；第2A圖顯示在裝置墊上形成IO上覆凸塊結構的典型習知製程，包含形成焊料凸塊的步驟；第3圖顯示在形成焊料凸塊之前，另一種位於裝置墊上的習知IO上覆凸塊結構；第4圖顯示第3圖之IO上覆凸塊結構的俯視圖；第5圖係示範習知重分佈層(RDL)結構的剖面圖；第6圖顯示第5圖之重分佈層結構的局部細部圖；第6A圖係示範習知含有焊料凸塊之RDL上覆凸塊結構的剖面圖；第7圖為第5圖之重分佈層結構的俯視圖；第8圖為根據本發明實施例所做之IO上覆凸塊結構範例的剖面圖；第9圖為第8圖之IO上覆凸塊結構範例的俯視圖；第10圖為根據本發明實施例所做之重分佈層結構範例的剖面圖；第11圖為第10圖之重分佈層結構的局部細部圖；第12圖為第10圖之重分佈層結構範例的俯視圖。
801‧‧‧矽
802‧‧‧裝置墊
803‧‧‧鈍化層
804‧‧‧聚合物1
805‧‧‧凸塊下方金屬

Claims (16)

  1. 一種半導體封裝件，包含：一裝置墊，該裝置墊直接位於一半導體基板上；一鈍化層，該鈍化層沉積於該裝置墊及該半導體基板上方，且該鈍化層具有一鈍化開口，其中局部移除該鈍化層以暴露出下方的該裝置墊；一聚合物層，該聚合物層沉積於該鈍化層上方，且該聚合物層具有一聚合物開口，其中局部移除該聚合物層以暴露出下方的該裝置墊及該鈍化層；及一凸塊下方金屬墊(UBM)，該凸塊下方金屬墊沉積於該聚合物層上方且經由該聚合物開口沉積於該裝置墊上；其中該裝置墊之一直徑比上該凸塊下方金屬墊之一直徑的比例範圍係從0.5：1至0.95：1，且其中該聚合物層中的該開口之一直徑比上該凸塊下方金屬墊之該直徑的比例範圍係從0.35：1至0.85：1。
  2. 如申請專利範圍第1項所述之半導體封裝件，其中該鈍化層中的該開口之一直徑比上該凸塊下方金屬墊之該直徑的比例範圍係從0.35：1至0.80：1。
  3. 如申請專利範圍第1項所述之半導體封裝件，其中熱應力與機械應力所帶來的力量更平均地分佈於一整個輸入輸出(IO)上覆凸塊結構。
  4. 如申請專利範圍第1項所述之半導體封裝件，其中該裝置墊、該凸塊下方金屬墊、該聚合物層以及該鈍化層採用圓形幾何形狀。
  5. 如申請專利範圍第1項所述之半導體封裝件，其中該裝置墊、該凸塊下方金屬墊、該聚合物層以及該鈍化層採用方形幾何形狀。
  6. 如申請專利範圍第1項所述之半導體封裝件，其中該聚合物層為聚醯亞胺(polyimide)。
  7. 如申請專利範圍第1項所述之半導體封裝件，其中該聚合物層為苯并環丁烯(benzocyclobutene，BCB)。
  8. 如申請專利範圍第1項所述之半導體封裝件，其中該聚合物層為聚苯并噁唑(polybenzoxazole)。
  9. 一種半導體封裝件，包含：一裝置墊，該裝置墊位於一基板上；一第一聚合物層，該第一聚合物層在該基板上方，該第一聚合物層具有一開口以暴露出該裝置墊；一重分佈層(RDL)，該重分佈層包括一停靠墊，該重 分佈層設置於該第一聚合物層上且導電耦合至該裝置墊；一第二聚合物層，該第二聚合物層位於該重分佈層上；及一凸塊下方金屬墊(UBM)，該凸塊下方金屬墊在該停靠墊上且延伸至該第二聚合物層之一頂面上，其中該凸塊下方金屬墊經由該第二聚合物層中的一開口而電連接至該停靠墊；其中該停靠墊之一直徑比上該凸塊下方金屬墊之一直徑的比例範圍係從0.5：1至0.95：1。
  10. 如申請專利範圍第9項所述之半導體封裝件，其中該第二聚合物層中的該開口之一直徑比上該凸塊下方金屬墊之該直徑的比例範圍係從0.35：1至0.85：1。
  11. 如申請專利範圍第9項所述之半導體封裝件，其中熱應力與機械應力所帶來的力量更平均地分佈於整個該重分佈層(RDL)下層結構。
  12. 如申請專利範圍第9項所述之半導體封裝件，其中該停靠墊、該凸塊下方金屬墊及該第二聚合物層採用圓形幾何形狀。
  13. 如申請專利範圍第9項所述之半導體封裝件，其中該 停靠墊、該凸塊下方金屬墊及該第二聚合物層採用方形幾何形狀。
  14. 如申請專利範圍第9項所述之半導體封裝件，其中該第二聚合物層為聚醯亞胺。
  15. 如申請專利範圍第9項所述之半導體封裝件，其中該第二聚合物層為苯并環丁烯(BCB)。
  16. 如申請專利範圍第9項所述之半導體封裝件，其中該第二聚合物層為聚苯并噁唑。
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