JPS5287983A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS5287983A
JPS5287983A JP411776A JP411776A JPS5287983A JP S5287983 A JPS5287983 A JP S5287983A JP 411776 A JP411776 A JP 411776A JP 411776 A JP411776 A JP 411776A JP S5287983 A JPS5287983 A JP S5287983A
Authority
JP
Japan
Prior art keywords
semiconductor device
production
dicing
delamination
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP411776A
Other languages
Japanese (ja)
Inventor
Keiji Miyamoto
Hiroshi Kato
Toru Kawanobe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP411776A priority Critical patent/JPS5287983A/en
Publication of JPS5287983A publication Critical patent/JPS5287983A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Landscapes

  • Formation Of Insulating Films (AREA)
  • Dicing (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To prevent the delamination of the film around the chip and produce a semiconductor device of high reliability by forming metal bump electrodes in the openings of a polymide resin film, then dicing the wafer.
COPYRIGHT: (C)1977,JPO&Japio
JP411776A 1976-01-19 1976-01-19 Production of semiconductor device Pending JPS5287983A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP411776A JPS5287983A (en) 1976-01-19 1976-01-19 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP411776A JPS5287983A (en) 1976-01-19 1976-01-19 Production of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5287983A true JPS5287983A (en) 1977-07-22

Family

ID=11575830

Family Applications (1)

Application Number Title Priority Date Filing Date
JP411776A Pending JPS5287983A (en) 1976-01-19 1976-01-19 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5287983A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55166947A (en) * 1979-06-14 1980-12-26 Hitachi Ltd Thin film capacitor integrated circuit
JPH03184360A (en) * 1989-12-13 1991-08-12 Canon Inc Manufacture of semiconductor device
EP0704895B1 (en) * 1994-09-30 2002-06-05 Nec Corporation Process for manufacturing semiconductor device and semiconductor wafer
US6830999B2 (en) * 1997-09-12 2004-12-14 Agere Systems Inc. Method of fabricating flip chip semiconductor device utilizing polymer layer for reducing thermal expansion coefficient differential
US6903451B1 (en) 1998-08-28 2005-06-07 Samsung Electronics Co., Ltd. Chip scale packages manufactured at wafer level
JP2006140508A (en) * 1998-08-28 2006-06-01 Samsung Electronics Co Ltd Manufacturing method of semiconductor package
JP2006156772A (en) * 2004-11-30 2006-06-15 Denso Corp Semiconductor device and method for manufacturing the same
US7973418B2 (en) 2007-04-23 2011-07-05 Flipchip International, Llc Solder bump interconnect for improved mechanical and thermo-mechanical performance

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55166947A (en) * 1979-06-14 1980-12-26 Hitachi Ltd Thin film capacitor integrated circuit
JPH03184360A (en) * 1989-12-13 1991-08-12 Canon Inc Manufacture of semiconductor device
EP0704895B1 (en) * 1994-09-30 2002-06-05 Nec Corporation Process for manufacturing semiconductor device and semiconductor wafer
USRE39603E1 (en) 1994-09-30 2007-05-01 Nec Corporation Process for manufacturing semiconductor device and semiconductor wafer
US6830999B2 (en) * 1997-09-12 2004-12-14 Agere Systems Inc. Method of fabricating flip chip semiconductor device utilizing polymer layer for reducing thermal expansion coefficient differential
US6903451B1 (en) 1998-08-28 2005-06-07 Samsung Electronics Co., Ltd. Chip scale packages manufactured at wafer level
JP2006140508A (en) * 1998-08-28 2006-06-01 Samsung Electronics Co Ltd Manufacturing method of semiconductor package
JP4512027B2 (en) * 1998-08-28 2010-07-28 三星電子株式会社 Manufacturing method of semiconductor package
JP2006156772A (en) * 2004-11-30 2006-06-15 Denso Corp Semiconductor device and method for manufacturing the same
US7973418B2 (en) 2007-04-23 2011-07-05 Flipchip International, Llc Solder bump interconnect for improved mechanical and thermo-mechanical performance
US8188606B2 (en) 2007-04-23 2012-05-29 Flipchip International, Llc Solder bump interconnect
US8446019B2 (en) 2007-04-23 2013-05-21 Flipchip International, Llc Solder bump interconnect

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