CN110692127B - 使用扇出内插器小芯片的高密度互连 - Google Patents

使用扇出内插器小芯片的高密度互连 Download PDF

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CN110692127B
CN110692127B CN201880035627.7A CN201880035627A CN110692127B CN 110692127 B CN110692127 B CN 110692127B CN 201880035627 A CN201880035627 A CN 201880035627A CN 110692127 B CN110692127 B CN 110692127B
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rdl
components
interposer
package
terminals
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CN110692127A (zh
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翟军
仲崇华
胡坤忠
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Apple Inc
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Apple Inc
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Abstract

本公开提供了多部件封装件结构，其中内插器小芯片(110)被集成以提供部件之间的精细布线。在一个实施方案中，该内插器小芯片(110)和多个导电导孔(142)被包封在包封层(140)中。第一部件(130)和第二部件(132)的第一多个端子(135A)可以与多个导电柱电连接，并且第一部件和第二部件的第二多个端子(135B)可以与该内插器小芯片(110)电连接。

Description

使用扇出内插器小芯片的高密度互连
相关专利申请
本专利申请要求于2017年6月9日提交的美国临时申请62/517,789的优先权权益，该美国临时申请以引用方式并入本文。
技术领域
本文所述的实施方案涉及半导体封装，并且更具体地涉及包括内插器小芯片的半导体封装件。
背景技术
对便携式和移动电子设备诸如移动电话、个人数字助理(PDA)、数字相机、便携式播放器、游戏设备和其他移动设备的当前市场需求要求将更多性能和特征集成到越来越小的空间中。因此，管芯的输入/输出密度和集成在单个封装件内的管芯数量已经显著增加。具体地讲，已提出各种2.5D和3D封装方案作为多管芯封装方案来连接单个封装件内的相邻芯片。
发明内容
本文描述了多部件封装件结构，其中内插器小芯片被集成以提供部件之间的精细布线。在根据实施方案的管芯最后方法中，一个或多个内插器小芯片和多个导电柱可被嵌入在包封层内。该多个导电柱可延伸穿过包封层的厚度，用于包封层的第一侧和第二侧之间的电连接。在一个实施方案中，多个部件并排安装在包封层的第一侧上。第一部件和第二部件的第一多个端子与多个导电柱电连接，并且第一部件和第二部件的第二多个端子与内插器小芯片电连接。内插器小芯片将第一部件和第二部件互连。重新分布层(RDL)可任选地跨包封层的第一侧上方，其中第一部件和第二部件安装在RDL的与包封层相对的第一侧上。类似的结构以及其他结构也可在管芯优先方法中形成。
在根据实施方案的管芯优先方法中，第一部件和第二部件被嵌入在包封层内，并且一个或多个内插器小芯片被安装在包封层的第一侧上。内插器小芯片将第一部件和第二部件互连。在一个实施方案中，第一部件和第二部件的第一多个端子与横向邻近内插器小芯片的多个导电凸块电连接，并且第一部件和第二部件的第二多个端子与内插器小芯片电连接。
RDL可任选地跨包封层的第一侧，其中内插器小芯片被安装在RDL上，并且多个导电凸块连结到RDL接触垫。在任一构型中，任选的RDL可包括多个重新分布线的第一扇出互连布线区域以及与内插器小芯片互连的第二布线区域。例如，第二布线区域可包括堆叠或偏置导孔。在其他实施方案中，导电凸块不横向邻近内插器小芯片放置。在一个实施方案中，在将内插器小芯片安装在RDL上之前，多个导电柱任选地被镀覆在RDL上，然后内插器小芯片和多个导电柱被包封在第二包封层内。在根据实施方案的管芯优先或管芯最后方法中，导电凸块可任选地形成在RDL的着陆垫上。另选地，封装件可以被进一步处理，其中以此类着陆垫进行另选电连接。例如，该封装件可进一步集成到嵌入式晶圆级封装工艺中。
附图说明
图1A是根据一个实施方案的包括嵌入式内插器小芯片的多部件封装件的横截面侧视图图示。
图1B是根据一个实施方案的包括嵌入式内插器小芯片和重新分布层的多部件封装件的横截面侧视图图示。
图2是根据一个实施方案的形成包括嵌入式内插器小芯片的多部件封装件的方法的处理流程。
图3是根据一个实施方案的形成在承载衬底上的多个柱的横截面侧视图图示。
图4是根据一个实施方案的邻近多个柱被安装到承载衬底上的内插器小芯片的横截面侧视图图示。
图5是根据一个实施方案的形成在嵌入式内插器小芯片和多个柱上方的重新分布层的横截面侧视图图示。
图6是根据一个实施方案的安装在重新分布层上的多个部件的横截面侧视图图示。
图7是根据一个实施方案的包括嵌入式内插器小芯片和背侧重新分布层的多部件封装件的横截面侧视图图示。
图8是根据一个实施方案的包括多个不同管芯和嵌入式内插器小芯片的封装件的横截面侧视图图示。
图9是根据一个实施方案的包括嵌入式内插器小芯片和散热器的多部件封装件的横截面侧视图图示。
图10是根据一个实施方案的包括嵌入式内插器小芯片和嵌入式管芯的多部件封装件的横截面侧视图图示。
图11是根据一个实施方案的包括嵌入式内插器小芯片和加强环的多部件封装件的横截面侧视图图示。
图12A是根据一个实施方案的包括内插器小芯片的多部件封装件的横截面侧视图图示。
图12B是根据一个实施方案的包括内插器小芯片和重新分布层的多部件封装件的横截面侧视图图示。
图12C是根据一个实施方案的包括嵌入式内插器小芯片和重新分布层的多部件封装件的横截面侧视图图示。
图13是根据一个实施方案的形成包括内插器小芯片的多部件封装件的方法的处理流程。
具体实施方式
本实施方案描述了半导体封装件和制造方法，其中内插器小芯片被用于互连多个部件。在一个实施方案中，封装件包括嵌入在包封层内并且电连接到第一部件和第二部件的端子的多个导电柱和一个或多个内插器小芯片。在一个实施方案中，封装件包括嵌入在包封层内的第一部件和第二部件。第一部件和第二部件的第一多个端子与横向邻近与第一部件和第二部件的第二多个端子电连接的一个或多个内插器小芯片的多个导电凸块电连接。在这两个实施方案中，该一个或多个内插器小芯片将第一部件和第二部件互连。在这两个实施方案中，重新分布层(RDL)可任选地位于包括第一部件和第二部件的层和包括内插器小芯片并任选地包括多个导电柱的层之间。
在一个方面，内插器小芯片包括密脚距的部件到部件布线，而任选的RDL包括用于封装件的疏脚距扇出布线。这样，可避免在RDL内包括密脚距布线的成本和复杂性。另外，不必将具有硅通孔(TSV)的内插器包括在封装件内。
在另一方面，一些实施方案描述封装方法，其可对封装件产量具有积极影响。封装方法也可与通常利用硅内插器的封装工艺序列诸如硅晶圆堆叠封装兼容。因此，根据实施方案的任选RDL和嵌入式内插器小芯片可利用晶圆级设计规则来制造，同时在封装序列中替换常规内插器。
在另一方面，本实施方案描述可任选地包括集成无源器件诸如电阻器、电感器、电容器等的内插器小芯片构型。根据实施方案，设想了用于将内插器小芯片集成在封装件内的各种修改和变型。该封装件可附加地包括背侧RDL、相同或不同部件的组合，以及散热器、加强环或嵌入式有源管芯的添加。
在各种实施方案中，参照附图来进行描述。然而，某些实施方案可在不存在这些具体细节中的一个或多个具体细节或者不与其他已知的方法和构型相结合的情况下被实施。在以下的描述中，示出许多具体细节诸如特定构型、尺寸和工艺等，以提供对实施方案的透彻理解。在其他情况下，未对熟知的半导体工艺和制造技术进行特别详细地描述，以免不必要地模糊实施方案。整个说明书中所提到的“一个实施方案”是指结合实施方案所描述的特定特征、结构、构型或特性被包括在至少一个实施方案中。因此，整个说明书中多处出现短语“在一个实施方案中”不一定是指相同的实施方案。此外，特定特征、结构、构型或特性可以任何适当的方式组合在一个或多个实施方案中。
本文所使用的术语“在...上方”、“至”、“在...之间”、“跨”和“在...上”可指一层相对于其他层的相对位置。一层相对于另一层来说为“在其上方”、“跨其”、或“在其上”或者连结“至”另一层或者与另一层“接触”可为直接与另一层接触或可具有一个或多个居间层。一层在多层“之间”可为直接与该多层接触或可具有一个或多个居间层。
现在参见图1A，提供了根据一个实施方案的包括嵌入式内插器小芯片的多部件封装件的横截面侧视图图示。如图所示，封装件100可包括内插器小芯片110和多个导电柱142嵌入在包封层140内。该多个导电柱142可延伸穿过包封层的厚度，用于包封层140的第一侧141和第二侧147之间的电连接。在一个实施方案中，多个部件130、132并排安装在包封层140的第一侧141上。第一部件和第二部件的第一多个端子135A与多个导电柱142电连接，并且第一部件和第二部件的第二多个端子135B与内插器小芯片110电连接。内插器小芯片110将第一部件130和第二部件132互连。根据实施方案，第一部件130和第二部件132可为管芯或封装件，或其组合。在一个实施方案中，内插器小芯片110任选地包括集成的无源器件，诸如电阻器、电感器、电容器等。
多个导电柱142可延伸穿过包封层140的厚度。在一个实施方案中，多个导电凸块150(例如焊料凸块，C4)连结到多个导电柱142。如图所示，保护层144可任选地位于多个导电柱142和内插器小芯片110下面。开口可任选地被形成穿过保护层144以暴露多个导电柱142。另外，管芯附接膜146可任选地由于内插器小芯片110附接操作而存在。在一个实施方案中，多个接触垫126任选地形成在包封层140的第一侧141上。第一部件130和第二部件132可任选地连结到多个接触垫126，或直接在内插器小芯片110着陆垫112的暴露表面111以及导电柱142的暴露表面143上。
现在参见图1B，提供了根据一个实施方案的包括嵌入式内插器小芯片和RDL的多部件封装件的横截面侧视图图示。如图所示，RDL 120可任选地跨包封层140的第一侧141上方，其中第一部件130和第二部件132安装在RDL 120的与包封层140相对的第一侧121上。在一个实施方案中，封装件100包括RDL 120、安装在RDL 120的第一侧121上的第一部件130(例如，管芯或封装件)和第二部件132(例如，管芯或封装件)。包封层140跨RDL 120的与第一侧121相对的第二侧122上方。内插器小芯片110在RDL 120的第二侧122上被嵌入在包封层140内。根据实施方案，内插器小芯片110将第一部件130和第二部件132互连。在一个实施方案中，内插器小芯片110任选地包括集成的无源器件，诸如电阻器、电感器、电容器等。
RDL 120可以是一个或多个重新分布线124和钝化层125。重新分布线124的材料可由金属材料形成，该金属材料诸如：铜(Cu)；钛(Ti)；镍(Ni)；金(Au)；Ti、Ni、Au或Cu中至少一者的组合；或其它合适的金属、合金、或金属和/或合金的组合。钝化层125可为任何合适的绝缘材料，诸如氧化物或聚合物(例如，聚酰亚胺)。在一个实施方案中，重新分布线124可包括直接形成在导电柱142的暴露表面143上的接触垫123。可使用合适的技术诸如溅镀、然后进行蚀刻来形成重新分布线124。可使用沉积和图案化的序列在RDL 120内形成多个重新分布线124和钝化层125。在一个实施方案中，RDL 120的第一侧121包括接触垫或凸块下金属化(UBM)垫126。在所示的实施方案中，RDL 120附加地包括多个堆叠或偏置导孔127。堆叠或偏置导孔127也可直接形成在内插器小芯片110着陆垫112的暴露表面111上。堆叠或偏置导孔127的相对侧可附加地包括接触垫126(例如UBM垫)。
在一个实施方案中，RDL 120可包括与多个导电柱142互连的多个重新分布线124的第一扇出互连布线区域120A以及与内插器小芯片110互连的第二布线区域120B。例如，第二布线区域120B可包括堆叠或偏置导孔127。内插器小芯片110可包括内插器布线115，其特征在于脚距比多个重新分布线124的RDL 120扇出互连布线更密。堆叠或偏置导孔127的布置可延伸穿过RDL 120，以将内插器小芯片110与第一部件130和第二部件132互连。
在一个实施方案中，第一多个导电凸块131(例如焊料)将第一部件130和第二部件132连接到RDL 120，并且第二多个导电凸块133(例如，微凸块；焊料)将第一部件130和第二部件132连接到RDL 120。更具体地讲，第二多个导电凸块133通过延伸穿过RDL 120的堆叠或偏置导孔127的布置而与内插器小芯片110互连，而第一多个导电凸块131通过多个重新分布线124的扇出互连布线而与延伸穿过包封层140的厚度的多个导电柱142互连。在一些实施方案中，第一多个导电凸块131可具有比第二多个导电凸块133更疏的脚距，但它们也可具有类似的脚距。
图2是根据实施方案的形成包括嵌入式内插器小芯片110的多部件封装件100诸如图1A至图1B所示封装件的方法的处理流程。为了简洁起见，图2中提供的处理流程与图3至图6中提供的横截面侧视图图示同时描述。
现在参照图3，在操作2010处，在承载衬底202上形成多个导电柱142。导电柱142的材料可包括但不限于金属材料，诸如铜、钛、镍、金及其组合或合金。导电柱142可使用合适的处理技术来形成，并且可由各种合适的材料(例如，铜)和层形成。在一个实施方案中，导电柱142通过镀覆技术形成，诸如使用图案化光刻胶层电镀来限定柱结构尺寸，随后移除该图案化光刻胶层。承载衬底202可以是多种衬底，诸如硅或玻璃。还可包括任选的导电层204，以有利于镀覆导电柱142。
参见图4，在操作2020处，内插器小芯片110随后邻近多个导电柱202附接到载体衬底202。例如，这可使用任选的管芯附接膜146来实现。然后在操作2030处，内插器小芯片110和多个导电柱142被包封在包封层140中。根据实施方案，包封层140可利用干膜技术(例如，层合)或液基技术(例如，固化膜)来形成。例如，包封层140可为在电子封装中常用的任何合适的模塑复合材料。在一个实施方案中，包封层140被平坦化以暴露多个导电柱142的表面143和内插器小芯片110的着陆垫112的表面111。例如，着陆垫112可以是金属柱形凸块。接触垫126(例如UBM垫)任选地形成在多个导电柱142的暴露表面143和内插器小芯片110的着陆垫112的暴露表面111上。根据实施方案，图4中所提供的结构可在晶片级形成。可附加地执行测试以验证多个导电柱142和内插器小芯片110的电连接。
现在参见图5，在操作2040处，RDL 120任选地形成在经包封的内插器小芯片110和多个导电柱142上方并与其电接触。形成RDL 120可包括形成与多个导电柱142互连的重新分布线124的第一扇出互连布线区域120A，以及与内插器小芯片110互连的第二布线区域120B(例如，堆叠或偏置导孔127)。内插器小芯片110可包括内插器布线，其特征在于脚距比重新分布线124的RDL扇出互连布线更密。在一个实施方案中，重新分布线124可包括直接形成在导电柱142的暴露表面143上的接触垫123。堆叠或偏置导孔127也可直接形成在内插器小芯片110着陆垫112的暴露表面111上。根据实施方案，图5中所提供的结构可在晶片级形成。可附加地执行测试以验证RDL 120和内插器小芯片110内的电连接。
现在参见图6，在操作2050处，第一部件130和第二部件132于是被安装。在第一实施方案中，诸如图1A所示的实施方案中，第一部件130和第二部件132被安装在导电柱142、或形成在其上的着陆垫112或接触垫126上。在第二实施方案中，诸如图1B所示的实施方案中，第一部件130和第二部件132被安装在RDL 120上。根据实施方案，第一部件130和第二部件132可使用合适的技术附接，诸如倒装芯片结合技术以及使用导电凸块131、133(例如焊料)。在一个实施方案中，第二多个导电凸块133为微凸块，并且可以比第一多个导电凸块131小。应当理解，也可在晶片级执行部件附接，包括大量部件。在一个实施方案中，第一部件130和第二部件132是相同类型的管芯或封装件。例如，它们可以都是逻辑管芯或封装件(例如CPU、GPU、SoC等)或存储器管芯或封装件。在一个实施方案中，第一部件130和第二部件132可以是不同类型的管芯或封装件、或者是管芯和封装件的组合。在一个实施方案中，第一部件130是CPU管芯或封装件，而第二部件132是GPU管芯或封装件。
在安装部件之后，第一部件130和第二部件132可任选地被底部填充或利用模塑复合材料重叠注塑，以保护连结结构的机械完整性或化学完整性。然后可在操作2060处移除承载衬底202和任选的导电层204。在一个实施方案中，可形成任选的保护层144，然后将多个导电凸块150(例如焊料凸块，C4)连结到多个导电柱142，并且切割各个封装件100，从而得到图1A至图1B所示的结构。
在以下对图7至图12C的描述中，提供了若干封装件变型形式。应当理解，实施方案不限于所示的具体配置，并且这些封装件变型形式中的若干者可被组合在单个实施方案内。另外，尽管所示的具体封装件变型形式包括RDL 120，但RDL是任选的。因此，以下封装件变型形式应被理解为示例性的，而不是限制性的。
图7是根据一个实施方案的包括嵌入式内插器小芯片110和背侧RDL 160的多部件封装件100的横截面侧视图图示。在此类实施方案中，可在移除承载衬底202之后形成背侧RDL 160。背侧RDL 160可包括一个或多个重新分布线164和钝化层165。在一个实施方案中，重新分布线164可包括直接形成在导电柱142的暴露表面145上的接触垫163。在一个实施方案中，背侧RDL 160的背侧也可包括接触垫或凸块下金属化(UBM)垫166以接收导电凸块150。
在此之前，已经描述了第一部件130和第二部件132可为不同类型的管芯或封装件，或者管芯和封装件的组合。图8是根据一个实施方案的包括多个不同管芯或封装件和嵌入式内插器小芯片的封装件100的横截面侧视图图示。如图所示，第一部件130和第二部件132具有不同尺寸。在一个实施方案中，第一部件130是管芯，而第二部件132是封装件。因此，根据一个实施方案，内插器小芯片110可提供管芯和封装件之间的精细布线。
图9是根据一个实施方案的包括嵌入式内插器小芯片110和散热器170的多部件封装件100的横截面侧视图图示。如图所示，散热器170可固定到多个部件130、132上，以及使用例如导热底部填充材料172固定。
图10是根据一个实施方案的包括嵌入式内插器小芯片110和嵌入式管芯180的多部件封装件100的横截面侧视图图示。管芯180可与内插器小芯片110类似地被集成。例如，管芯180可使用管芯附接膜146而被附接。类似地，任选的RDL 120可包括直接形成在着陆垫182(例如，金属柱形凸块)的暴露表面181上的接触垫123。在RDL 120不存在的情况下，导电凸块131可连结到着陆垫182，或形成在其上的接触垫126。在一个实施方案中，嵌入式管芯180被包括以用于功率递送目的，例如当第一部件130和第二部件132包括处理器管芯诸如CPU和/或GPU时。
图11是根据一个实施方案的包括嵌入式内插器小芯片110和加强环190的多部件封装件100的横截面侧视图图示。在此类实施方案中，在安装部件130、132之后以及在拆卸承载衬底202之前，可任选地附接加强环190。
图12A是根据一个实施方案的包括内插器小芯片110的多部件封装件100的横截面侧视图图示。在一具体实施方案中，内插器小芯片100包括集成的无源器件。如图所示，封装件100可包括包封层240，以及嵌入在包封层240内的第一部件130和第二部件132。内插器小芯片110安装在包封层240的第一侧241上。第一部件130和第二部件132的第一多个端子135A与横向邻近内插器小芯片110的多个导电凸块150电连接，并且第一部件130和第二部件132的第二多个端子135B与内插器小芯片110电连接。内插器小芯片110将第一部件130和第二部件132互连。如图所示，底部填充材料195可任选地被施用在内插器小芯片110和包封层240之间，以及围绕导电凸块117(例如，微凸块；焊料)。保护层244可任选地形成在第一部件130和第二部件132上方。
图12B是根据一个实施方案的包括内插器小芯片110和RDL 120的多部件封装件100的横截面侧视图图示。如图所示，RDL 120可位于包封层240的第一侧241上，并且包括与第一部件130和第二部件132互连的第一扇出互连布线区域120A，以及将第一部件130和第二部件132与内插器小芯片110互连的第二布线区域120B。在一个实施方案中，内插器小芯片110安装在RDL 120上，并且多个导电凸块150连结到第一扇出互连布线区域120A的RDL接触垫126。在一个实施方案中，封装件100包括RDL 120、附接到RDL 120的第一侧121的第一部件130(例如，管芯或封装件)和第二部件132(例如，管芯或封装件)。包封层140跨RDL 120的第一侧121上方并且包封第一部件130和第二部件132。内插器小芯片110安装在RDL 120的第二侧122上。在一个实施方案中，内插器小芯片110互连第一部件130和第二部件132。类似于前面的描述，RDL 120可包括与第一部件130和第二部件132互连的第一扇出互连布线区域120A，以及将第一部件130和第二部件132与内插器小芯片110互连的第二布线区域120B(例如，堆叠或偏置导孔127)。
在图12B所示的具体实施方案中，多个导电凸块150(例如焊料凸块，C4)被连结到RDL 120的接触垫或UBM接触垫126，使得它们横向邻近内插器小芯片110。内插器小芯片110可以利用多个明显比封装件100的导电凸块150小的导电凸块117(例如，微凸块；焊料)直接安装在堆叠或偏置导孔127或导孔127上的接触垫126上。内插器小芯片110可包括内插器布线115，其特征在于脚距比多个重新分布线124的RDL 120扇出互连布线更密。堆叠或偏置导孔127的布置可延伸穿过RDL 120，以将内插器小芯片110与第一部件130和第二部件132互连。内插器小芯片根据实施方案可任选地包括集成的无源器件。
图12C是根据一个实施方案的包括嵌入式内插器小芯片和重新分布层的多部件封装件的横截面侧视图图示。图12C基本上类似于图12B，但是添加了从RDL 120的第二侧122延伸的多个导电柱142，其中内插器小芯片110和多个导电柱140嵌入在包封层140内。保护层144可任选地形成在包封层140和内插器小芯片110上方。保护层144可被图案化，然后镀覆或沉积以形成着陆垫148。导电凸块150(例如焊料凸块，C4)可任选地形成在着陆垫148上。另选地，封装件100可被进一步处理，其中以着陆垫148进行另选电连接。例如，封装件100然后可在嵌入式晶圆级封装工艺中被进一步封装。内插器小芯片110可任选地包括一个或多个通孔200(例如，硅通孔)，以与内插器小芯片110的与导电凸块117相对的侧(例如，背侧)上的着陆垫148和导电凸块150连接。
图13是根据实施方案的形成包括内插器小芯片110的多部件封装件100诸如图12A至图12C所示封装件的方法的处理流程。在操作1310处，多个部件130、132附接到承载衬底102。例如，这可任选地使用管芯附接膜146来促进。然后在操作1320处，在承载衬底102上利用包封层140包封部件130、132。包封层140然后可被平坦化。这可任选地暴露端子135A、135B(例如，金属柱形凸块)的表面。另选地，包封层140可被图案化，然后镀覆以形成金属柱形凸块。
RDL 120然后任选地在操作1330处被形成在被包封部件130、132上方且与其电接触，或者更具体地形成在端子135A、135B上方并与其电接触。在一个实施方案中，RDL 120包括直接形成在第一部件130和第二部件132的第一多个端子135A上的接触垫123。RDL可附加地包括直接形成在第一部件130和第二部件132的第二多个端子135B上的堆叠导孔127。此类制造序列可减轻与第一部件130和第二部件132相关联的翘曲，具体地讲是与避免在安装期间的回流以及薄的第一部件130和第二部件132相关联。可使用沉积和图案化的序列在RDL 120内形成多个堆叠或偏置导孔127、重新分布线124和钝化层125。在一个实施方案中，RDL 120包括接触垫126(例如UBM垫)。接触垫126也可形成在最后一个堆叠或偏置的导孔127上。然后可任选地在操作1331处从RDL 120的第二侧122镀覆多个导电柱142。导电柱142可被镀覆在接触垫126上。在操作1340处，使用合适的技术诸如倒装芯片结合技术来安装内插器小芯片110。在一个实施方案中，利用多个导电凸块117(例如，微凸块；焊料)来实现连结。
在安装内插器小芯片110之后，内插器小芯片110可任选地在操作1341处被底部填充以保护连结结构的机械完整性或化学完整性。在操作1343处，任选的多个导电柱和内插器小芯片可任选地被包封(例如，嵌入)在包封层中。钝化层144和着陆垫148可任选地在操作1345处形成。然后可在操作1350处移除承载衬底202。在一个实施方案中，可在各个阶段形成任选的保护层144。在一些实施方案中，多个导电凸块150(例如焊料凸块，C4)可连结到多个接触垫126/放置在其上。然后可执行各个封装件100的切割，从而得到图12A至图12C所示的结构。
在利用实施方案的各个方面时，对本领域技术人员显而易见的是，对于形成包括内插器小芯片的封装件而言，以上实施方案的组合或变型是可能的。尽管以特定于结构特征和/或方法行为的语言对实施方案进行了描述，但应当理解，所附权利要求并不一定限于所描述的特定特征或行为。所公开的特定特征和行为相反应当被理解为用于进行例示的权利要求的实施方案。

Claims (17)

1.一种封装件，包括：
包封层；
内插器小芯片，所述内插器小芯片嵌入在所述包封层内；
多个导电柱，所述多个导电柱嵌入在所述包封层内；和
重新分布层(RDL)，RDL跨所述包封层的第一侧上方；
其中所述RDL包括与所述多个导电柱互连的第一扇出互连布线区域以及与所述内插器小芯片互连的第二布线区域；
第一部件和第二部件，所述第一部件和所述第二部件位于所述RDL与所述包封层相对的第一侧上；
其中所述内插器小芯片包括内插器布线，所述内插器布线的特征在于比所述第一扇出互连布线区域更密的脚距，以及所述第二布线区域包括延伸穿过所述RDL以将所述内插器小芯片与所述第一部件和所述第二部件互连的堆叠导孔或偏置导孔的布置；
其中所述第一部件和所述第二部件的第一多个端子直接在所述RDL上并与其电连接以及与所述多个导电柱电连接，并且第一部件和第二部件的第二多个端子直接在所述堆叠导孔或偏置导孔的布置上并与其电连接以及与所述内插器小芯片电连接，其中所述内插器小芯片将所述第一部件和所述第二部件互连，并且所述第一多个端子具有比所述第二多个端子更疏的脚距。
2.根据权利要求1所述的封装件，还包括直接在所述堆叠导孔或偏置导孔的布置上的多个凸块下金属化(UBM)垫，并且所述内插器小芯片被连结到所述多个UBM垫上。
3.根据权利要求2所述的封装件，其中所述堆叠导孔或偏置导孔的布置从所述第一部件和所述第二部件完全穿过RDL延伸到所述多个UBM垫。
4.根据权利要求3所述的封装件，其中所述堆叠导孔或偏置导孔的布置由堆叠导孔组成。
5.根据权利要求1所述的封装件，其中所述第一部件和所述第二部件嵌入在所述RDL的所述第一侧上的包封层内。
6.根据权利要求5所述的封装件，其中所述RDL包括直接形成在所述第一部件和所述第二部件的所述第一多个端子上的接触垫。
7.根据权利要求5所述的封装件，还包括在所述内插器小芯片和所述RDL之间的底部填充材料。
8.根据权利要求1所述的封装件，其中所述第一部件选自第一管芯和第一封装件，并且所述第二部件选自第二管芯和第二封装件。
9.一种形成封装件的方法，包括：
将第一部件和第二部件附接到承载衬底；
在所述承载衬底上包封所述第一部件和所述第二部件；
与所述承载衬底相对地直接在包封的所述第一部件和所述第二部件上并与其电接触地形成重新分布层(RDL)；
其中所述RDL包括直接在所述第一部件和所述第二部件的第一多个端子上并与其电连接的第一扇出互连布线区域以及第二布线区域，所述第二布线区域包括直接在所述第一部件和所述第二部件的第二多个端子上并与其电连接的堆叠导孔或偏置导孔的布置，并且所述堆叠导孔或偏置导孔的布置延伸穿过所述RDL并连接到所述第一部件和所述第二部件；
其中所述第一多个端子具有比所述第二多个端子更疏的脚距；
与所述承载衬底相对地将内插器小芯片安装在所述RDL上，使得所述第一部件和所述第二部件的所述第二多个端子通过所述堆叠导孔或偏置导孔的布置与所述内插器小芯片电连接，并且所述内插器小芯片将所述第一部件和所述第二部件互连；以及
移除所述承载衬底。
10.根据权利要求9所述的方法，还包括在移除所述承载衬底之前，将多个导电凸块横向邻近所述内插器小芯片地放置在所述第一部件和所述第二部件上。
11.根据权利要求9所述的方法，还包括在移除所述承载衬底之前，将底部填充材料施用在所述内插器小芯片。
12.根据权利要求11所述的方法，还包括在将所述内插器小芯片安装在所述RDL上之前在所述RDL上镀覆多个导电柱。
13.一种封装件，包括：
包封层；
第一部件和第二部件，所述第一部件和所述第二部件嵌入在所述包封层内；和
内插器小芯片，所述内插器小芯片安装在所述包封层的第一侧上；
其中所述内插器小芯片将所述第一部件和所述第二部件互连；和
重新分布层(RDL)，RDL位于所述包封层的所述第一侧上并且直接在所述第一部件和所述第二部件的第一多个端子以及所述第一部件和所述第二部件的第二多个端子上并与其电连接，其中所述内插器小芯片安装在所述RDL上，所述RDL包括直接在所述第一部件和所述第二部件的所述第一多个端子上并与其互连的第一扇出互连布线区域以及直接在所述第一部件和所述第二部件的所述第二多个端子上的第二布线区域，所述第二布线区域将所述第一部件和所述第二部件与所述内插器小芯片互连，其中所述第一多个端子具有比所述第二多个端子更疏的脚距；
其中所述内插器小芯片包括内插器布线，所述内插器布线的特征在于比所述第一扇出互连布线区域更密的脚距，并且所述第二布线区域包括延伸穿过所述RDL以将所述内插器小芯片与所述第一部件和所述第二部件互连的堆叠导孔或偏置导孔的布置。
14.根据权利要求13所述的封装件，还包括在所述内插器小芯片和所述RDL之间的底部填充材料。
15.根据权利要求13所述的封装件，还包括连结到所述第一扇出互连布线区域的RDL接触垫的多个导电凸块。
16.根据权利要求13所述的封装件，还包括从所述RDL延伸的多个导电柱。
17.根据权利要求13所述的封装件，其中所述内插器小芯片包括集成的无源器件。
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