TW201903979A - 使用扇出型中介層小晶片的高密度互連 - Google Patents

使用扇出型中介層小晶片的高密度互連 Download PDF

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Publication number
TW201903979A
TW201903979A TW107117447A TW107117447A TW201903979A TW 201903979 A TW201903979 A TW 201903979A TW 107117447 A TW107117447 A TW 107117447A TW 107117447 A TW107117447 A TW 107117447A TW 201903979 A TW201903979 A TW 201903979A
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component
package
rdl
interposer
encapsulation layer
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TW107117447A
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TWI723264B (zh
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翟軍
仲崇華
胡坤忠
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美商蘋果公司
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Abstract

描述將一中介層小晶片整合於其中以在組件之間提供之精細繞線的多組件封裝結構。在實施例中，將該中介層小晶片與複數個導電通孔囊封在一囊封層中。該第一組件及該第二組件的第一複數個端子可與該複數個導電柱電連接，且第一組件及第二組件的第二複數個端子可與該中介層小晶片電連接。

Description

使用扇出型中介層小晶片的高密度互連
本文描述的實施例相關於半導體封裝，且更具體地相關於包括中介層小晶片的半導體封裝。
可攜式及行動電子裝置（諸如，行動電話、個人數位助理(PDA)、數位相機、可攜式播放器、遊戲、及其他行動裝置）的目前市場需求要求將更多效能及特徵整合至越來越小的空間中。結果，晶粒的輸入/輸出密度與整合在單一封裝內的晶粒數目已顯著增加。已特別提議作為多晶粒封裝解決方案的各種2.5D及3D封裝解決方案以連接單一封裝內的相鄰晶粒。
描述將一中介層小晶片整合於其中以在組件之間提供精細繞線的多組件封裝結構。在根據實施例的晶粒後貼合方法(die-last approach)中，可將一或多個中介層小晶片及複數個導電柱內嵌在囊封層內。用於在囊封層的第一側及第二側之間的電連接之複數個導電柱可延伸通過囊封層的厚度。在實施例中，將多個組件並排地安裝在囊封層的第一側上。第一及第二組件的第一複數個端子與複數個導電柱電連接，且第一及第二組件的第二複數個端子與中介層小晶片電連接。中介層小晶片將第一及第二組件互連。再分布層(RDL)可可選地跨越囊封層的第一側上方，其具有安裝在相對於囊封層之RDL的第一側上之第一及第二組件。相似及其他結構也可以晶粒先貼合方法(die-first approach)形成。
在根據實施例的晶粒先貼合方法中，將第一及第二組件內嵌在囊封層內，並將一或多個中介層小晶片安裝在囊封層的第一側上。中介層小晶片將第一及第二組件互連。在實施例中，第一及第二組件的第一複數個端子與橫向相鄰於中介層小晶片的複數個導電凸塊電連接，且第一及第二組件的第二複數個端子與中介層小晶片電連接。
RDL可可選地跨越囊封層的第一側，其具有安裝在RDL上的中介層小晶片，及接合至RDL接觸墊的複數個導電凸塊。在任一組態中，可選的RDL可包括多條再分布線之扇出型互連繞線的第一區域，及與中介層小晶片互連之繞線的第二區域。例如，繞線的第二區域可包括堆疊或偏移通孔。在其他實施例中，導電凸塊不放置成橫向地相鄰於中介層小晶片。在實施例中，在將中介層小晶片安裝在RDL上之前，將複數個導電柱可選地電鍍在RDL上，然後將中介層小晶片及複數個導電柱封裝在第二囊封層內。在根據實施例的晶粒先貼合或晶粒後貼合方法的任一方法中，導電凸塊可可選地形成在RDL的著陸墊上。替代地，封裝可係替代電連接以此種著陸墊產生的進一步處理。例如，封裝可進一步整合至內嵌型晶圓級封裝處理中。
［相關申請案之交互參照］
本申請案主張於2017年6月9日申請之美國臨時專利申請案第62/517,789號的優先權，其以引用方式併入本文中。
實施例描述在其中使用中介層小晶片來互連多個組件的半導體封裝及製造方法。在實施例中，封裝包括內嵌在囊封層內，並電連接至第一及第二組件之端子的複數個導電柱及一或多個中介層小晶片。在實施例中，封裝包括內嵌在囊封層內的第一及第二組件。第一及第二組件之第一複數個端子與橫向相鄰於一或多個中介層小晶片的複數個導電凸塊電連接，該等中介層小晶片與第一及第二組件的第二複數個端子電連接。在二個實施例中，一或多個中介層小晶片將第一及第二組件互連。在二個實施例中，再分布層(RDL)可可選地位於包括第一及第二組件之層與包括中介層小晶片及可選地包括複數個導電柱的層之間。
在一態樣中，中介層小晶片包括細節距之組件至組件繞線，而可選的RDL包括用於封裝的粗節距扇出型繞線。以此方式，能避免將細節距繞線包括在RDL內的成本及複雜度。額外地，不必將具有貫矽通孔(TSV)的中介層包括在封裝內。
在另一態樣中，一些實施例描述對於封裝良率上可具有正面效果的封裝方法。封裝方法也可與封裝處理序列相容，諸如，常使用矽中介層的矽基板上晶圓上晶片封裝(chip-on-wafer-on-silicon)。因此，根據實施例之可選的RDL及內嵌型中介層小晶片能使用晶圓級設計規則製造，而置換封裝序列中的習知中介層。
在另一態樣中，實施例描述中介層小晶片組態，其可可選地包括整合式被動裝置（諸如，電阻器、電感器、電容器等）。根據實施例而設想將中介層小晶片整合在封裝內的各種修改及變化。封裝可額外地包括背側RDL、相同或不同組件的組合、及散熱器、加強環、或內嵌型主動晶粒的加入。
在各種實施例中，參照圖式進行說明。然而，某些實施例可在無這些特定細節之一或多者的情況下實行或可與其他已知的方法及組態結合實行。在下列敘述中，為了提供對實施例的全面瞭解而提出眾多特定細節（例如，特定組態、尺寸、及程序等）。在其他例子中，為了避免不必要地使本實施例失焦，所以並未特別詳細地敘述公知的半導體程序及製造技術。此專利說明書通篇指稱的「一實施例(one embodiment)」係指與該實施例一同描述之具體特徵、結構、組態、或特性係包括在至少一實施例中。因此，此專利說明書通篇於各處出現之詞組「在一實施例中(in one embodiment)」不必然指稱相同實施例。此外，在一或多個實施例中，可以任何合適的方式結合特定特徵、結構、組態、或特性。
如本文所用之「在…上方(over)」、「至(to)」、「介於…之間(between)」、「橫跨(spanning)」、及「在…上(on)」之用語可指稱一層相對於其他層之一相對位置。在另一層「上方」、「橫跨」另一層、或在另一層「上」或者接合「至」另一層或與另一層「接觸(contact)」的一層可直接與該另一層接觸或可具有一或多個中介層。一層介於（多個）層「之間」可直接與該等層接觸或可具有一或多個中介層。
現在參考圖1A，提供根據實施例之包括內嵌型中介層小晶片的多組件封裝之截面側視圖。如圖所示，封裝100可包括內嵌在囊封層140內的中介層小晶片110複數個導電柱142。針對在囊封層140的第一側141及第二側147之間的電連接，複數個導電柱142可延伸通過該囊封層的厚度。在實施例中，將多個組件130、132並排地安裝在囊封層140的第一側141上。第一及第二組件的第一複數個端子135A與複數個導電柱142電連接，且第一及第二組件的第二複數個端子135B與中介層小晶片110電連接。中介層小晶片110將第一組件130及第二組件132互連。根據實施例，第一組件130及第二組件132可係晶粒、封裝、或其組合。在實施例中，中介層小晶片110可選地包括整合式被動裝置，諸如，電阻器、電感器、電容器等。
複數個導電柱142可延伸通過囊封層140的厚度。在實施例中，將複數個導電凸塊150（例如，銲料凸塊、C4）接合至複數個導電柱142。如圖所示，保護層144可可選地位於複數個導電柱142及中介層小晶片110之下。開口可可選地通過保護層144形成，以暴露複數個導電柱142。額外地，晶粒附接膜146可可選地由於中介層小晶片110附接操作而存在。在實施例中，將複數個接觸墊126可選地形成在囊封層140的第一側141上。第一組件130及第二組件132可可選地接合至複數個接觸墊126，或可直接接合在中介層小晶片110之著陸墊112的暴露表面111上及導電柱142之暴露表面143上。
現在參考圖1B，提供根據實施例之包括內嵌型中介層小晶片的多組件封裝之截面側視圖。如圖所示，RDL 120可可選地跨越囊封層140的第一側141上方，其具有相對於囊封層140之安裝在RDL 120的第一側121上之第一組件130及第二組件132。在實施例中，封裝100包括RDL 120、安裝在RDL 120之第一側121上的第一組件130（例如，晶粒或封裝）及第二組件132（例如，晶粒或封裝）。囊封層140跨越相對於第一側121之RDL 120的第二側122上方。將中介層小晶片110內嵌在RDL 120之第二側122上的囊封層140內。根據實施例，中介層小晶片110將第一組件130及第二組件132互連。在實施例中，中介層小晶片110可選地包括整合式被動裝置，諸如，電阻器、電感器、電容器等。
RDL 120可一或多條再分布線124及鈍化層125。再分布線124的材料可形成自金屬材料，諸如：銅(Cu)；鈦(Ti)；鎳(Ni)；金(Au)；Ti、Ni、Au、或Cu之至少一者的組合；或其他合適金屬、合金、或金屬及/或合金的組合。鈍化層125能係任何合適絕緣材料，諸如，氧化物、或聚合物（例如，聚醯亞胺）。在實施例中，再分布線124能包括直接形成在導電柱142之暴露表面143上的接觸墊123。再分布線124可使用合適技術形成，諸如，濺鍍，然後蝕刻。多條再分布線124及鈍化層125可使用一系列沈積及圖案化形成在RDL 120內。在實施例中，RDL 120的第一側121包括接觸墊或凸塊下金屬化(UBM)墊126。在所說明的實施例中，RDL 120額外包括複數個堆疊或偏移通孔127。堆疊或偏移通孔127也可直接形成在中介層小晶片110之著陸墊112的暴露表面111上。堆疊或偏移通孔127的相對側可額外包括接觸墊126（例如，UBM墊）。
在實施例中，RDL 120可包括與複數個導電柱142互連的多條再分布線124之扇出型互連繞線的第一區域120A，及與中介層小晶片110互連之繞線的第二區域120B。例如，繞線的第二區域120B可包括堆疊或偏移通孔127。中介層小晶片110可包括中介層繞線115，其特徵在於比多條再分布線124的RDL 120之扇出型互連繞線更細的節距。堆疊或偏移通孔127的配置可延伸通過RDL 120以將中介層小晶片110與第一組件130及第二組件132互連。
在實施例中，第一複數個導電凸塊131（例如，銲料）將第一組件130及第二組件132連接至RDL 120，且第二複數個導電凸塊133（例如，微凸塊；銲料）將第一組件130及第二組件132連接至RDL 120。更具體地說，第二複數個導電凸塊133經由延伸通過RDL 120之堆疊或偏移通孔127的配置與中介層小晶片110互連，而第一複數個導電凸塊131與藉由多條再分布線124之扇出型互連繞線延伸通過囊封層140之厚度的複數個導電柱142互連。在一些實施例中，第一複數個導電凸塊131可具有比第二複數個導電凸塊133更粗的節距，雖然彼等也可具有相似節距。
圖2係根據實施例形成包括內嵌型中介層小晶片110之多組件封裝100（諸如圖1A至圖1B中所繪示的）的方法之處理流程。為了簡潔起見，連同在圖3至圖6中提供的截面側視圖，來描述在圖2中提供的處理流程。
現在參照圖3，在操作2010，將複數個導電柱142形成在載體基材202上。導電柱142的材料能包括，但不限於，金屬材料，諸如，銅、鈦、鎳、金、及彼等的組合或合金。導電柱142可使用合適處理技術形成，並可以各式各樣合適材料（例如，銅）及層形成。在實施例中，導電柱142係藉由電鍍技術，諸如，使用圖案化光阻層界定柱結構尺寸的電鍍，然後藉由移除圖案化光阻層而形成。載體基材202可係各式各樣的基材，諸如，矽或玻璃。可額外包括可選的導電層204以促進導電柱142的電鍍。
參考圖4，在操作2020，然後將中介層小晶片110相鄰於複數個導電柱202附接至載體基材202。例如，此可使用可選的晶粒附接膜146完成。然後在操作2030，將中介層小晶片110及複數個導電柱142囊封在囊封層140中。根據實施例，囊封層140可使用乾膜技術（例如，層壓）或基於液體的技術（例如，固化膜）形成。例如，囊封層140可係常使用在電子封裝中的任何合適模製化合物。在實施例中，將囊封層140平坦化以暴露複數個導電柱142的表面143與中介層小晶片110之著陸墊112的表面111。例如，著陸墊112可係金屬柱形凸塊。將接觸墊126（例如，UBM墊）可選地形成在複數個導電柱142的暴露表面143及中介層小晶片110之著陸墊112的表面111上。根據實施例，圖4中提供的結構可以晶圓規模形成。可額外實施測試以驗證複數個導電柱142與中介層小晶片110的電連接。
現在參考圖5，在操作2040，RDL 120可選地形成在經囊封中介層小晶片110與複數個導電柱142上方並與其等電接觸。形成RDL 120可包括形成與複數個導電柱142互連的再分布線124之扇出型互連繞線的第一區域120A，及與中介層小晶片110互連之繞線（例如，堆疊或偏移通孔127）的第二區域120B。中介層小晶片110可包括中介層繞線，其特徵在於比再分布線124的RDL之扇出型互連繞線更細的節距。在實施例中，再分布線124能包括直接形成在導電柱142之暴露表面143上的接觸墊123。堆疊或偏移通孔127也可直接形成在中介層小晶片110之著陸墊112的暴露表面111上。根據實施例，圖5中提供的結構可以晶圓規模形成。可額外實施測試以驗證RDL 120內、及中介層小晶片110的電連接。
現在參考圖6，在操作2050，然後安裝第一組件130與第二組件132。在第一實施例中，諸如，繪示於圖1A中的實施例，將第一組件130及第二組件132安裝在導電柱142、著陸墊112、或形成於其上的接觸墊126上。在第二實施例中，諸如，繪示於圖1B中的實施例，將第一組件130及第二組件132安裝在RDL 120上。根據實施例，第一組件130及第二組件132可使用合適技術附接，諸如，覆晶接合及使用導電凸塊131、133（例如，銲料）。在實施例中，第二複數個導電凸塊133係微凸塊，並可小於第一複數個導電凸塊131。應理解組件附接也可以包括大量之組件的晶圓規模實施。在實施例中，第一組件130及第二組件132係相同類型的晶粒或封裝。例如，彼等二者可都係邏輯晶粒或封裝（例如，CPU、GPU、SoC等）或記憶體晶粒或封裝。在實施例中，第一組件130及第二組件132可係不同類型的晶粒或封裝，或晶粒與封裝的組合。在實施例中，第一組件130係CPU晶粒或封裝，而第二組件132係GPU晶粒或封裝。
在安裝組件後，第一組件130及第二組件132可可選地係以模製化合物底部填充或包覆模製，以保護接合結構的機械或化學完整性。在操作2060，然後可將載體基材202與可選的導電層204移除。在實施例中，可形成可選的保護層144，接著將複數個導電凸塊150（例如，銲料凸塊、C4）接合至複數個導電柱142，且切割獨立封裝100，造成在圖1A至圖1B中繪示的結構。
在圖7至圖12C的以下描述中，提供數個封裝變化。應理解實施例未受所說明之具體組態限制，且可將封裝變化的數者組合在單一實施例中。額外地，在所說明之具體封裝變化包括RDL 120的同時，該RDL係可選的。因此，應瞭解以下封裝變化係說明性的，而非限制性的。
圖7係根據實施例之包括內嵌型中介層小晶片110及背側RDL 160的多組件封裝100之截面側視圖。在此種實施例中，背側RDL 160可在移除載體基材202之後形成。背側RDL 160可包括一或多條再分布線164及鈍化層165。在實施例中，再分布線164能包括直接形成在導電柱142之暴露表面145上的接觸墊163。在實施例中，背側RDL 160的背側也可包括接觸墊或凸塊下金屬化(UBM)墊166以接受導電凸塊150。
至此，已描述第一組件130及第二組件132可係不同類型的晶粒或封裝，或晶粒與封裝的組合。圖8係根據實施例之包括多個不同晶粒或封裝及內嵌型中介層小晶片的封裝100之截面側視圖。如圖所示，第一組件130及第二組件132包括不同尺寸。在實施例中，第一組件130係晶粒，而第二組件132係封裝。因此，根據實施例，中介層小晶片110可在晶粒與封裝之間提供精細繞線。
圖9係根據實施例之包括內嵌型中介層小晶片110及散熱器170的多組件封裝100之截面側視圖。如圖所示，例如，散熱器170可固定至多個組件130、132上並使用導熱底部填充材料172固定。
圖10係根據實施例之包括內嵌型中介層小晶片110及內嵌型晶粒180的多組件封裝100之截面側視圖。晶粒180可與中介層小晶片110相似地整合。例如，晶粒180可使用晶粒附接膜146附接。相似地，可選的RDL 120可包括直接形成在著陸墊182（例如，金屬柱形凸塊）之暴露表面181上的接觸墊123。在RDL 120不存在處，導電泵131能接合至形成於其上的著陸墊182或接觸墊126。在實施例中，包括用於電力傳遞目的的內嵌型晶粒180，例如，當第一組件130及第二組件132包括處理器晶粒時，諸如，CPU及/或GPU。
圖11係根據實施例之包括內嵌型中介層小晶片110及加強環190的多組件封裝100之截面側視圖。在此種實施例中，加強環190可可選地在組件130、132的安裝後，及載體基材202的分離前附接。
圖12A係根據實施例之包括中介層小晶片110的多組件封裝100之截面側視圖。在具體實施例中，中介層小晶片100包括整合式被動裝置。如所繪示的，封裝100可包括囊封層240，及內嵌在囊封層240內的第一組件130與第二組件132。中介層小晶片110安裝在囊封層240的第一側241上。第一組件130及第二組件132的第一複數個端子135A與橫向相鄰於中介層小晶片110的複數個導電凸塊150電連接，且第一組件130及第二組件132的第二複數個端子135B與中介層小晶片110電連接。中介層小晶片110將第一組件130及第二組件132互連。如圖所示，底部填充材料195可可選地施加在中介層小晶片110與囊封層240之間，以及導電凸塊117周圍（例如，微凸塊；銲料）。保護層244可可選地形成在第一組件130及第二組件132上方。
圖12B係根據實施例之包括中介層小晶片110及RDL 120的多組件封裝100之截面側視圖。如圖所示，RDL 120可在囊封層240的第一側241上，並包括與第一組件130及第二組件132互連之扇出型互連繞線的第一區域120A，及將第一組件130及第二組件132與中介層小晶片110互連之繞線的第二區域120B。在實施例中，中介層小晶片110安裝在RDL 120上，且複數個導電凸塊150接合至扇出型互連繞線之第一區域120A的RDL接觸墊126。在實施例中，封裝100包括RDL 120、附接至RDL 120之第一側121上的第一組件130（例如，晶粒或封裝）及第二組件132（例如，晶粒或封裝）。囊封層140跨越RDL 120的第一側121上方並囊封第一組件130及第二組件132。中介層小晶片110安裝在RDL 120的第二側122上。在實施例中，中介層小晶片110將第一組件130及第二組件132互連。相似於先前描述，RDL 120可包括與第一組件130及第二組件132互連之扇出型互連繞線的第一區域120A，及將第一組件130及第二組件132與中介層小晶片110互連之繞線（例如，堆疊或偏移通孔127）的第二區域120B。
在繪示於圖12B的特定實施例中，將複數個導電凸塊150（例如，銲料凸塊、C4）接合至RDL 120的接觸墊或UBM接觸墊126，使得彼等橫向地相鄰於中介層小晶片110。中介層小晶片110可直接安裝在堆疊或偏移通孔127，或在具有複數個導電凸塊117（例如，微凸塊；銲料）的通孔127上的接觸墊126上，其實質小於封裝100的導電凸塊150。中介層小晶片110可包括中介層繞線115，其特徵在於比多條再分布線124的RDL 120之扇出型互連繞線更細的節距。堆疊或偏移通孔127的配置可延伸通過RDL 120以將中介層小晶片110與第一組件130及第二組件132互連。根據實施例，中介層小晶片可可選地包括整合式被動裝置。
圖12C係根據實施例之包括內嵌型中介層小晶片及再分布層的多組件封裝之截面側視圖。具有從RDL 120的第二側122延伸之複數個導電柱142的加入，具有內嵌在囊封層140內的中介層小晶片110與複數個導電柱140的圖12C實質相似於圖12B。保護層144可可選地形成在囊封層140及中介層小晶片110上方。保護層144可圖案化，之後電鍍或沈積以形成著陸墊148。導電凸塊150（例如，銲料凸塊、C4）可可選地形成在著陸墊148上。替代地，封裝100可受替代電連接以著陸墊148製成的進一步處理。例如，然後封裝100可在內嵌型晶圓級封裝處理中受進一步封裝。中介層小晶片110可可選地包括一或多個貫穿通孔200（例如，貫穿矽通孔）以與著陸墊148及在相對於導電凸塊117之中介層小晶片110的側（例如，背側）上的導電凸塊150連接。
圖13係根據實施例形成包括中介層小晶片110之多組件封裝100（諸如圖12A至圖12C中所繪示的）的方法之處理流程。在操作1310，複數個組件130、132附接至載體基材102。例如，此可可選地使用晶粒附接膜146來促進。在操作1320，然後使用囊封層140將組件130、132囊封在載體基材102上。然後可將囊封層140平坦化。此可可選地暴露端子135A、135B（例如，金屬柱形凸塊）的表面。替代地，囊封層140可圖案化，之後藉由電鍍以形成金屬柱形凸塊。
在操作1330，然後將RDL 120可選地形成在經囊封組件130、132上方並與其電接觸，或更具體地說，在端子135A、135B上方並與其電接觸。在實施例中，RDL 120包括直接形成在第一組件130及第二組件132之第一複數個端子135A上的接觸墊123。RDL可額外包括直接形成在第一組件130及第二組件132之第二複數個端子135B上的堆疊通孔127。此種製造序列可緩和與第一組件130及第二組件132關聯的翹曲，特別在安裝及薄化第一組件130與第二組件132期間與避免回流關聯的翹曲。多個堆疊或偏移通孔127、再分布線124、及鈍化層125可使用一系列沈積及圖案化形成在RDL 120內。在實施例中，RDL 120包括接觸墊126（例如，UBM墊）。接觸墊126也可形成在最後的堆疊或偏移通孔127上。在操作1331，然後複數個導電柱142可可選地從RDL 120的第二側122電鍍。導電柱142可電鍍在接觸墊126上。在1340，中介層小晶片110使用合適技術安裝，諸如，覆晶接合。在實施例中，接合係使用複數個導電凸塊117（例如，微凸塊；銲料）實現。
在中介層小晶片110的安裝後，中介層小晶片110可可選地在操作1341底部填充以保護經接合結構的機械或化學完整性。可選的複數個導電柱與中介層小晶片可可選地在操作1343囊封（例如，內嵌）在囊封層內。鈍化層144與著陸墊148可可選地在操作1345形成。然後載體基材202可在操作1350移除。在實施例中，可選的保護層144可在各階段形成。在一些實施例中，複數個導電凸塊150（例如，銲料凸塊、C4）能接合至/放置在複數個導電柱126上。然後可實施獨立封裝100的切割，造成在圖12A至圖12C中繪示的結構。
在使用實施例的各種態樣的過程中，所屬技術領域中具有通常知識者將明白上述實施例的組合或變化對於形成包括中介層小晶片的封裝而言係可行的。雖然已經以結構特徵及/或方法動作之特定語言敘述實施例，應了解附加的申請專利範圍不必受限於所述的特定特徵或行為。替代地，所揭示之特定的特徵或動作應理解為可用於說明之申請專利範圍的實施例。
100‧‧‧封裝
110‧‧‧中介層小晶片
111‧‧‧暴露表面
112‧‧‧著陸墊
115‧‧‧中介層繞線
117‧‧‧導電凸塊
120‧‧‧RDL
120A‧‧‧第一區域
120B‧‧‧第二區域
121‧‧‧第一側
122‧‧‧第二側
123‧‧‧接觸墊
124‧‧‧再分布線
125‧‧‧鈍化層
126‧‧‧接觸墊
127‧‧‧堆疊或偏移通孔
130‧‧‧組件
131‧‧‧導電凸塊
132‧‧‧組件
133‧‧‧導電凸塊
135A‧‧‧端子
135B‧‧‧端子
140‧‧‧囊封層
141‧‧‧第一側
142‧‧‧導電柱
143‧‧‧暴露表面
144‧‧‧保護層
145‧‧‧暴露表面
146‧‧‧晶粒附接膜
147‧‧‧第二側
148‧‧‧著陸墊
150‧‧‧導電凸塊
160‧‧‧背側RDL
163‧‧‧接觸墊
164‧‧‧再分布線
165‧‧‧鈍化層
166‧‧‧凸塊下金屬化(UBM)墊
170‧‧‧散熱器
172‧‧‧導熱底部填充材料
180‧‧‧晶粒
181‧‧‧暴露表面
182‧‧‧著陸墊
190‧‧‧加強環
195‧‧‧底部填充材料
200‧‧‧貫穿通孔
202‧‧‧載體基材
204‧‧‧導電層
240‧‧‧囊封層
241‧‧‧第一側
244‧‧‧保護層
［圖1A］係根據實施例之包括內嵌型中介層小晶片的多組件封裝之截面側視圖。 ［圖1B］係根據實施例之包括內嵌型中介層小晶片及再分布層的多組件封裝之截面側視圖。 ［圖2］係根據實施例之形成包括內嵌型中介層小晶片的多組件封裝之方法的流程圖。 ［圖3］係根據實施例之形成在載體基材上的複數個柱之截面側視圖。 ［圖4］係根據實施例之相鄰於複數個柱之安裝在載體基材上的中介層小晶片之截面側視圖。 ［圖5］係根據實施例之形成在內嵌型中介層小晶片及複數個柱上方的再分布層之截面側視圖。 ［圖6］係根據實施例之安裝在再分布層上的複數個組件之截面側視圖。 ［圖7］係根據實施例之包括內嵌型中介層小晶片及背側再分布層的多組件封裝之截面側視圖。 ［圖8］係根據實施例之包括多個不同晶粒及內嵌型中介層小晶片的封裝之截面側視圖。 ［圖9］係根據實施例之包括內嵌型中介層小晶片及散熱器的多組件封裝之截面側視圖。 ［圖10］係根據實施例之包括內嵌型中介層小晶片及內嵌型晶粒的多組件封裝之截面側視圖。 ［圖11］係根據實施例之包括內嵌型中介層小晶片及加強環的多組件封裝之截面側視圖。 ［圖12A］係根據實施例之包括中介層小晶片的多組件封裝之截面側視圖。 ［圖12B］係根據實施例之包括中介層小晶片及再分布層的多組件封裝之截面側視圖。 ［圖12C］係根據實施例之包括內嵌型中介層小晶片及再分布層的多組件封裝之截面側視圖。 ［圖13］係根據實施例之形成包括中介層小晶片的多組件封裝之方法的流程圖。

Claims (21)

  1. 一種封裝，其包含： 一囊封層； 一中介層小晶片，其內嵌在該囊封層內； 複數個導電柱，其內嵌在該囊封層內；及 一第一組件及一第二組件，其在該囊封層的一第一側上； 其中該第一組件及該第二組件的第一複數個端子與該複數個導電柱電連接，且第一組件及第二組件的第二複數個端子與該中介層小晶片電連接，其中該中介層小晶片將該第一組件及該第二組件互連。
  2. 如請求項1之封裝，其進一步包含在該囊封層之該第一側上的複數個接觸墊，其中該第一組件及該第二組件接合至該複數個接觸墊。
  3. 如請求項1之封裝，其進一步包含跨越該囊封層之該第一側上方的一再分布層(RDL)，其中該第一組件及該第二組件相對於該囊封層在該RDL的一第一側上。
  4. 如請求項3之封裝，其中該RDL包含與該複數個導電柱互連之扇出型互連繞線的一第一區域，及與該中介層小晶片互連之繞線的一第二區域。
  5. 如請求項4之封裝，其中該中介層小晶片包括中介層繞線，其特徵在於比扇出型互連繞線之該第一區域更細的一節距。
  6. 如請求項5之封裝，其中繞線的該第二區域包括延伸通過該RDL之堆疊通孔或偏移通孔的一配置，以將該中介層小晶片與該第一組件及該第二組件互連。
  7. 如請求項5之封裝，其進一步包含將該第一組件及該第二組件連接至該RDL的第一複數個導電凸塊，及將該第一組件及該第二組件連接至該RDL的第二複數個導電凸塊。
  8. 如請求項5之封裝，其中該第一組件及該第二組件內嵌在該RDL之該第一側上的一囊封層內。
  9. 如請求項8之封裝，其中該RDL包含直接形成在該第一組件及該第二組件之該第一複數個端子上的接觸墊，
  10. 如請求項1之封裝，其中該第一組件係選自由一第一晶粒及一第一封裝所組成之群組，且該第二組件係選自由一第二晶粒及一第二封裝所組成之群組。
  11. 一種形成一封裝的方法，其包含： 附接一第一組件及一第二組件至一載體基材； 囊封在該載體基材上的該第一組件及該第二組件； 將一中介層小晶片相對於該載體基材安裝在該第一組件及該第二組件上，使得該第一組件及該第二組件與該中介層小晶片電連接；及 移除該載體基材。
  12. 如請求項11之方法，其進一步包含在移除該載體基材之前將複數個導電凸塊橫向地相鄰於該中介層小晶片而放置在該第一組件與該第二組件上。
  13. 如請求項11之方法，其進一步包含： 形成一再分布層(RDL)在經囊封的該第一組件及該第二組件上方並與其等電接觸；及 將該中介層小晶片相對於該第一組件與該第二組件安裝在該RDL上。
  14. 如請求項13之方法，其進一步包含在將該中介層小晶片安裝在該RDL上之前將複數個導電柱電鍍在該RDL上，並將該中介層小晶片與該複數個導電柱囊封在一第二囊封層內。
  15. 一種封裝，其包含： 一囊封層； 一第一組件及一第二組件，其等內嵌在該囊封層內；及 一中介層小晶片，其安裝在該囊封層的一第一側上； 其中該中介層小晶片將該第一組件及該第二組件互連。
  16. 如請求項15之封裝，其中該第一組件及該第二組件的第一複數個端子與橫向相鄰於該中介層小晶片的複數個導電凸塊電連接，且第一組件及第二組件的第二複數個端子與該中介層小晶片電連接。
  17. 如請求項15之封裝，其進一步包含在該囊封層之該第一側上的一再分布層(RDL)，其中該中介層小晶片安裝在該RDL上，該RDL包含與該第一組件及該第二組件互連之扇出型互連繞線的一第一區域，及將該第一組件及該第二組件與該中介層小晶片互連之繞線的一第二區域。
  18. 如請求項17之封裝，其進一步包含複數個導電凸塊，其接合至扇出型互連繞線之該第一區域的RDL接觸墊。
  19. 如請求項17之封裝，其進一步包含從該RDL延伸的複數個導電柱，且該複數個導電柱及該中介層小晶片內嵌在一第二囊封層內。
  20. 如請求項17之封裝，其中該中介層小晶片包括中介層繞線，其特徵在於比扇出型互連繞線之該第一區域更細的一節距。
  21. 如請求項15之封裝，其中該中介層小晶片包括一整合式被動裝置。
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