CN103489844B - 封装半导体器件的方法和装置 - Google Patents

封装半导体器件的方法和装置 Download PDF

Info

Publication number
CN103489844B
CN103489844B CN201210457335.7A CN201210457335A CN103489844B CN 103489844 B CN103489844 B CN 103489844B CN 201210457335 A CN201210457335 A CN 201210457335A CN 103489844 B CN103489844 B CN 103489844B
Authority
CN
China
Prior art keywords
ppi
pad
line
hollow space
ppi pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201210457335.7A
Other languages
English (en)
Other versions
CN103489844A (zh
Inventor
吴逸文
何明哲
吕文雄
杜家玮
刘重希
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN103489844A publication Critical patent/CN103489844A/zh
Application granted granted Critical
Publication of CN103489844B publication Critical patent/CN103489844B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0235—Shape of the redistribution layers
    • H01L2224/02351—Shape of the redistribution layers comprising interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0236—Shape of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02375—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/03828—Applying flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05551—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605—Shape
    • H01L2224/06051—Bonding areas having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10145—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H01L2224/13027—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being offset with respect to the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16106—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting one bonding area to at least two respective bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本发明提供了封装半导体器件的方法和装置。公开了用于晶圆级封装(WLP)半导体器件的方法和装置。可以通过钝化后互连(PPI)线和PPI焊盘将电路的接触焊盘连接到焊料凸块。PPI焊盘可以包括中空部分和开口。PPI焊盘可以与PPI线作为一个整体一起形成。PPI焊盘的中空部分可以用于控制球安装工艺中所用的焊剂的量从而使得任何多余量的焊剂可以从PPI焊盘的实心部分的开口溢出。可以将焊料球直接安装到PPI焊盘而不使用如常规WLP封装件所需的任何凸块下金属(UBM)。

Description

封装半导体器件的方法和装置
技术领域
本发明涉及半导体器件封装，具体而言，涉及晶圆级封装(WLP)半导体器件的方法和装置。
背景技术
半导体器件用于各种电子应用，如个人电脑、手机、数码相机和其他电子设备。半导体行业通过不断减小最小部件尺寸，从而使得更多元件集成到给定面积上，进而持续提高各种电子元件(例如，晶体管、二极管、电阻器、电容器等)的集成密度。在一些应用中，这些更小的电子元件也需要比过去的封装件更小的利用更少面积的封装件。
已开发出来的一种用于半导体器件的较小的封装件是晶圆级封装件(WLP)，其中，集成电路被封装在通常包括再分布层(RDL)或钝化后互连件(PPT)的封装件中，该RDL或PPT用于使电路的接触焊盘的引线成扇形散开，从而可以以比电路的接触焊盘更大的间距制造电接触件。
由于成本和结构简单的优势，WLP封装件已越来越多地应用到集成电路封装中。然而，WLP的标准制造工艺是昂贵的，其可能需要四个光掩膜，此外，在将焊料球安装在晶圆上的RDL或PPI上的过程中使用的非最佳的焊剂量可能导致不能稳固地连接焊料球。需要解决这些问题的方法和系统。
发明内容
为了解决上述技术问题，一方面，本发明提供了一种封装件器件，包括：接触焊盘，位于电路的表面上；钝化层，位于所述电路的表面和所述接触焊盘的第一部分的上方，其中所述接触焊盘的第二部分保持外露；钝化后互连(PPI)线，位于所述钝化层上并接触所述接触焊盘的第二部分；以及PPI焊盘，连接到所述PPI线，所述PPI焊盘包括中空部分和开口。
所述的器件还包括位于所述钝化层与所述PPI线和所述PPI焊盘之间的聚合物层。
所述的器件还包括位于所述PPI焊盘的中空部分上方并接触所述PPI焊盘的焊料球。
在所述的器件中，所述PPI焊盘和所述PPI线被制成一个整体。
在所述的器件中，所述PPI焊盘具有环形、矩形或正方形的形状。
在所述的器件中，所述PPI焊盘具有外径介于约180μm到约260μm范围内的环形形状。
在所述的器件中，所述PPI焊盘具有宽度尺寸介于约10μm到约130μm范围内的环形形状。
在所述的器件中，所述PPI焊盘的开口的长度介于约10μm到约50μm的范围内。
在所述的器件中，所述PPI焊盘的中空部分的形状是圆形、矩形或正方形。
在所述的器件中，所述PPI焊盘还包括位于中空部分内的实心部分。
在所述的器件中，所述PPI焊盘还包括位于中空部分内的实心部分，其中，所述实心部分的形状是圆形、矩形或正方形。
在所述的器件中，所述PPI焊盘还包括位于中空部分内的实心部分，其中，所述实心部分是直径介于约10μm到约160μm范围内的圆形物。
在所述的器件中，所述PPI焊盘还包括位于中空部分内的实心部分，其中，所述实心部分设置在所述PPI的中空部分的中心。
另一方面，本发明提供了一种形成封装件器件的方法，包括：提供电路，所述电路具有位于所述电路的表面上的接触焊盘；在所述电路的表面和所述接触焊盘的第一部分的上方形成钝化层，并且暴露出所述接触焊盘的第二部分；在所述钝化层上形成与所述接触焊盘的第二部分相接触的钝化后互连(PPI)线；以及形成连接到所述PPI线并包括中空部分和开口的PPI焊盘。
所述的方法还包括在所述钝化层与所述PPI线和所述PPI焊盘之间形成聚合物层。
所述的方法还包括将焊料球设置于所述PPI焊盘的中空部分的上方并与所述PPI焊盘接触。
在所述的方法中，作为一个整体同时形成所述PPI焊盘和所述PPI线。
所述的方法还包括在所述中空部分内形成所述PPI焊盘的实心部分。
在所述的方法中，所述PPI焊盘具有外径介于约180μm到约260μm范围内的环形形状。
又一方面，本发明提供了一种封装件器件，包括：接触焊盘，位于电路的表面上；钝化层，位于所述电路的表面和所述接触焊盘的第一部分的上方，其中所述接触焊盘的第二部分保持外露；聚合物层，位于所述钝化层和所述接触焊盘的第三部分上，其中所述接触焊盘的第四部分保持外露；钝化后互连(PPI)线，位于所述聚合物层上并接触所述接触焊盘的第四部分；PPI焊盘，位于所述聚合物层上并连接到所述PPI线，所述PPI焊盘包括中空部分和开口；以及焊料球，位于所述PPI焊盘的中空部分的上方并接触所述PPI焊盘。
附图说明
为了更充分地理解本发明及其优点，现在将参考结合附图所进行的以下描述，其中：
图1(a)至图1(d)示出以截面图或俯视图显示的具有改进的钝化后互连设计的WLP工艺的实施例；以及
图2(a)至图2(d)示出以截面图或俯视图显示的具有改进的钝化后互连设计的WLP工艺的另一实施例。
除非另有说明，不同附图中的相应数字和符号通常是指相应的部件。绘制附图用于清楚地示出各个实施例的相关方面而不必按比例绘制。
具体实施方式
在下面详细论述本发明的实施例的制造和使用。然而，应该理解，本发明的实施例提供了许多可以在各种具体环境中实现的可应用的概念。所论述的具体实施例仅是制造和使用实施例的说明性具体方式，而不用于限制本发明的范围。
本发明公开了晶圆级封装(WLP)的方法和装置。可以通过钝化后互连(PPI)线和PPI焊盘将电路的接触焊盘连接到焊料凸块，其中PPI焊盘具有改进的设计。PPI焊盘可以包括中空部分和开口。PPI焊盘的中空部分可以起到控制球安装工艺中所用焊剂的量的作用，从而可以使任何多余量的焊剂从PPI焊盘的开口溢出(escape)。焊料球可以直接安装在PPI焊盘上而不使用如常规WLP封装件所需要的任何凸块下金属(UBM)，从而降低成本，同时提高接合性能。
晶圆级封装件(WLP)通常与要求高速度、高密度和更大的引脚数量的集成电路(IC)一起使用。图1(a)至图1(d)示出以截面图或俯视图显示的具有改进PPI焊盘设计的WLP工艺的实施例。
图1(a)示出，在由硅或其他块状半导体材料制成的基板上可以形成IC 30或电路30。IC 30可以是基础半导体晶圆的一部分，其包含未示出的其他半导体IC。根据电路的电气设计，IC 30包含有源器件和无源器件、导电层和介电层。电路30的长度仅作说明之用并且可以不按比例绘制。图1(a)至图1(d)所示的用于电路30的说明性工艺适用于在电路30所在的同一晶圆上封装其他电路。仅示出了用于通过如图1(c)所示的钝化后互连(PPI)线和PPI焊盘连接电路30的一个接触焊盘与一个焊料球/凸块的工艺。PPI线和焊盘可以被称为再分配层(RDL)。根据其功能设计，电路30可以包括通过PPI线和PPI焊盘的网络连接到多个焊料球/凸块的多个接触焊盘。根据半导体器件的功能，来自电路30的电信号通过PPI线和PPI焊盘的网络按路径发送到一个或多个焊料凸块。
使用图案化和沉积工艺形成作为接触焊盘32的导电层。电路30可以具有位于其表面上的多个接触焊盘32。接触焊盘32可以由铝(Al)、铜(Cu)、锡(Sn)、镍(Ni)、金(Au)、银(Ag)或其它导电金属材料制成。接触焊盘32的沉积采用电镀或化学镀工艺。接触焊盘32的尺寸、形状和位置只作说明之用而不用于限制。电路30的多个接触焊盘(未示出)可以具有相同或不同的尺寸。
在电路30的表面上方以及在接触焊盘32的顶部上可以形成用于结构支撑和物理隔离的钝化层34。钝化层34可以由氮化硅(SiN)、二氧化硅(SiO2)、氮氧化硅(SiON)、聚酰亚胺(PI)、苯并环丁烯(BCB)、聚苯并恶唑(PBO)或其它绝缘材料制成。可以通过使用掩膜限定的光刻胶蚀刻工艺移除钝化层34的一部分以暴露出接触焊盘32的一部分同时仍覆盖接触焊盘32的其它部分来形成钝化层34的开口。形成的开口的尺寸、形状和位置只作说明之用而不用于限制。
可以在钝化层34上沿着钝化层34的轮廓形成聚合物层54，填充接触焊盘32上方的钝化层34的开口的一部分。聚合物层54可以不完全地填充接触焊盘32上方的钝化层34的开口，替代为可以对聚合物层54进行图案化形成开口以暴露出接触焊盘32的一部分，同时覆盖接触焊盘32的剩余部分。聚合物层54的图案化可以包括光刻技术。聚合物层54可以由聚合物如环氧树脂、聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等形成，但是也可以使用其它相对较软的通常为有机的介电材料。形成方法包括旋涂或其它常用的方法。举例来说，聚合物层54的厚度可以介于约5μm到约30μm之间。整个说明书中所列举的尺寸仅是示例，且将会随着集成电路的按比例缩小而改变。
如图1(b)所示，金属材料用于在聚合物层54上沿着聚合物层54的轮廓形成钝化后互连(PPI)线56。PPI线56进一步连接到如图1(b)所示的PPI焊盘60上。在一个实施例中，PPI线56和PPI焊盘60之间的连接可以是平滑而不间断的，使两者成为一个整体。在以截面图示出的图1(b)中，PPI焊盘60包括中空部分58-1和开口58-2。PPI焊盘具有开口58-2控制焊剂的量从而使焊剂不能溢出，从而为界定焊料球提供适量的焊剂。如果焊剂溢出，溢出的焊剂将从PPI焊盘60中通过开口58-2流出来。
图1(d)以俯视图示出了PPI焊盘60及其与PPI线56的连接的更多细节。PPI线56是在接触焊盘32上方延伸的线。PPI线56填充聚合物层54的开口并接触接触焊盘32。因此，PPI线56与接触焊盘32形成电连接。PPI线56可以具有窄的、宽的或楔形的(tapered)形状。PPI线56可以具有基本上不变的厚度和宽度。PPI线56终止于PPI焊盘60，因此PPI线56和PPI焊盘60的主体可以形成为一个整体。
PPI焊盘60用于连接到焊料球，通过PPI线56和PPI焊盘60在接触焊盘32到焊料球之间形成连接。PPI焊盘60包括中空部分58-1和开口58-2。焊料球/凸块可以安装在中空部分58-1上并与PPI焊盘60相接触，从而可以在焊料球和PPI焊盘60之间形成电连接。焊料球的直径也可以大于中空部分58-1的直径或宽度。
如图1(d)所示，PPI焊盘可以具有环绕中空部分58-1并带有开口58-2的环形形状。连接中空部分58-1和开口58-2以形成一个连接部分。在三维空间中，它们形成用于容纳焊剂的腔。PPI焊盘60可以具有其它形状，如矩形或正方形。举例来说，PPI焊盘60可以具有外径D4的尺寸介于约180μm到约260μm范围内的环形形状。举例来说，PPI焊盘60可以具有宽度尺寸D 1介于约10μm到约130μm范围内的环形形状。举例来说，PPI焊盘60的开口58-2的尺寸(其可以是长度)D5可以介于约10μm到约50μm的范围内。中空部分58-1的形状可以是圆形、矩形、正方形或一些其它形状。
PPI焊盘60在到达聚合物层54的末端之前可以在某处停止。如图1(b)和图1(d)所示，聚合物层54的终端与PPI焊盘60的边缘之间的距离约是尺寸D2。在形成连接时尺寸D2可以是非常灵活的。
返回参照图1(b)，示出PPI线56和PPI焊盘60的高度只作说明之用而不用于限制。举例来说，PPI线56和PPI焊盘的高度可以小于约30μm，例如介于约2μm到10μm之间，或者介于到的范围内。PPI线56和PPI焊盘可以由例如Ti、Al、Ni、镍钒(NiV)、Cu、或铜合金制成。形成方法包括电镀、化学镀、溅射、化学汽相沉积法等。举例来说，可以由使用Ti、TiW或Cr的粘着层的单层或多层制成PPI线56和PPI焊盘60。根据半导体器件的功能，电路30与若干PPI线56和PPI焊盘60连接从而形成可以与电路30的接触焊盘电连接的PPI线和PPI焊盘的网络。
可以将焊剂(未示出)施加到PPI线56和PPI焊盘60。焊剂主要用来帮助焊料流动，从而使图1(c)中所示的焊料球82与PPI焊盘60形成良好的接触。可以以多种方法中的任何一种包括刷涂或喷涂进行施加。焊剂通常具有从焊料表面去除氧化物屏障的酸性成分，并且具有在组装工艺期间有助于阻止芯片在基板表面上移动的粘着性。在相关领域所用的焊剂中，最为常见的是含松香作为主要成分的那些焊剂。松香包含诸如松香酸或左旋海松酸的羧酸，并且羧基基团用于去除待焊接的金属表面的氧化膜。
如图1(c)所示，在中空部分58-1的顶部上的PPI焊盘60上设置焊料连接件82，其可以是焊料凸块或焊料球。本申请中所用的词语“焊料”包括但不限于铅基焊料和无铅焊料，如用于铅基焊料的Pb-Sn组分和包含锡、铜和银或者“SAC”组分的无铅焊料；以及具有共同的熔点并在电气应用中形成导电焊料连接的其它共晶体。对于无铅焊料，可以使用具有不同组成的SAC焊料，如SAC 105(Sn 98.5％，Ag 1.0％，Cu 0.5％)、SAC 305、SAC 405等。无铅焊料连接件(如焊料球)也可以由SnCu化合物形成而不使用银(Ag)。可选地，无铅焊料连接件也可以包括锡和银(Sn-Ag)以及任何铜。焊料连接件82可以是形成栅格的焊料球阵列中的一种，被称为“球栅阵列”或“BGA”。然而，这里所描述的实施例不限于BGA封装件或BGA球。实施例不限于球形或球状的焊料连接件。
图1(c)示出安装在电路30的顶部上的焊料球82的截面图。焊料球82可以直接安装到PPI焊盘60而不使用如常规WLP封装件所需要的任何凸块下金属(UBM)，从而降低成本同时提高接合性能。接触焊盘32连接到PPI线56和PPI焊盘60，其进一步连接到焊料球82。图1(a)至图1(d)所示的工艺仅作说明之用而不用于限制。本领域的技术人员能够很容易地预见到加工步骤和加工材料可以有许多种变化。
图2(a)至图2(d)示出以截面图或俯视图显示的具有改进的钝化后互连设计的WLP工艺的另一实施例。
图2(a)中示出，在由硅或其它块状半导体材料制成的基板上形成电路30。使用图案化和沉积工艺形成作为接触焊盘32的导电层。电路30可以具有多个接触焊盘32。可以在电路30上方和在接触焊盘32的顶部上形成用于结构支撑和物理隔离的钝化层34。可以通过使用掩膜限定的光刻胶蚀刻工艺去除钝化层34的一部分以暴露出接触焊盘32的一部分来形成钝化层34的开口。可以在钝化层34上沿着钝化层34的轮廓形成聚合物层54，填充位于接触焊盘32上方的钝化层34的开口的一部分。聚合物层54可以不完全地填充位于接触焊盘32上方的钝化层34的开口，替代为可以对聚合物层54进行图案化以形成开口从而暴露出部分接触焊盘32。图2(a)的更多细节与对图1(a)所述的细节相同。
如图2(b)所示，金属材料用于在聚合物层54上沿着聚合物层54的轮廓形成钝化后互连(PPI)线56。该PPI线56进一步连接到如图2(b)所示的PPI焊盘60。在一个实施例中，PPI线56和PPI焊盘60的连接是平滑而不间断地，这使两者成为一个整体。
以截面图示出，图2(b)所示的PPI焊盘60包括中空部分58-1、开口58-2和实心部分60-2。PPI焊盘60具有开口58-2控制焊剂的量使得焊剂不能溢出，从而为界定焊料球提供适量的焊剂。如果焊剂溢出，溢出的焊剂将会从PPI焊盘60中通过开口58-2流出去。
图2(d)以俯视图示出了PPI焊盘60及其与PPI线56的连接的更多细节。PPI线56可以是在接触焊盘32上方延伸的线。PPI线56填充聚合物层54的开口并且与接触焊盘32相接触。因此PPI线56与接触焊盘32形成电连接。PPI线56可以具有窄的、宽的或楔形的形状。PPI线56可以具有基本上不变的厚度和宽度。在一个实施例中，PPI线56终止于PPI焊盘60，因此PPI线和PPI焊盘60的主体形成为一个整体。
PPI焊盘60用于连接到焊料球，因此通过PPI线和PPI焊盘60在接触焊盘32和焊料球之间形成连接。在图2(d)中以俯视图示出，PPI焊盘60包括中空部分58-1、开口58-2和实心部分60-2。可以将焊料球/凸块安装在中空部分58-1上并与PPI焊盘60接触从而使得可以在焊料球和PPI焊盘60之间形成电连接。焊料球的直径可以大于中空部分58-1的直径或宽度。
如图2(d)所示，PPI焊盘60可以具有带有开口58-2的环形形状，并且其环绕中空部分58-1。PPI焊盘60可以具有其他形状，如矩形或正方形。举例来说，PPI焊盘60可以具有外径D4的尺寸介于约180μm到约260μm范围内的环形形状。举例来说，PPI焊盘60可以具有宽度尺寸D1介于约10μm到约130μm范围内的环形形状。举例来说，PPI焊盘60的开口58-2的尺寸(其可以是长度)D5可以介于约10μm到约50μm的范围内。中空部分58-1的形状可以为圆形、矩形、正方形或一些其他形状。
如图2(d)所示，中空部分58-1可以处于PPI焊盘60的中心。连接中空部分58-1和开口58-2以形成一个连接区域。在三维空间中，它们形成用于容纳焊剂的腔。
如图2(d)所示，PPI焊盘60的实心部分60-2可以是设置在中空部分58-1内的圆。实心部分60-2也可以具有其他形状，如矩形或正方形。实心部分60-2可以是直径D3的尺寸为约10μm到约160μm的圆。实心部分60-2可以设置在中空部分58-1的中心。实心部分60-2可以不与PPI焊盘60连接。在一些实施例中，实心部分60-2可以与PPI焊盘60连接。PPI焊盘60和实心部分60-2可以具有不同的形状。
包括中空部分58-1、开口58-2和实心部分60-2的PPI焊盘60在到达聚合物层54的末端之前可以在某处停止。如图2(b)和图2(d)所示，聚合物层54的终端和PPI焊盘60的边缘之间的距离约为尺寸D2。在形成连接时尺寸D2可以是非常灵活的。
图2(d)中所示的PPI焊盘60仅作说明之用并不用于限制。位于中空部分58-1内的实心部分可能多于一个。实心部分60-2可以与PPI焊盘连接或不连接。只要PPI焊盘60的外周长具有开口使得焊剂能够溢出，并且PPI焊盘60具有用来装入一定量的焊剂的腔，都将是可选的PPI焊盘设计。
返回参照图2(b)，示出的PPI线56和PPI焊盘60的高度仅作说明之用而不用于限制。举例来说，PPI线56和PPI焊盘60的高度可以小于约30μm，例如介于约2μm到约10μm之间，或者介于到的范围内。PPI线56和PPI焊盘60可以由例如Ti、Al、Ni、镍钒(NiV)、Cu或Cu合金制成。形成方法包括电镀、化学镀、溅射、化学汽相沉积法等。举例来说，PPI线56和PPI焊盘60可以由使用Ti、TiW或Cr的粘着层的单层或多层制成。根据半导体器件的功能，电路30与若干PPI线56和PPI焊盘60连接从而形成可以与半导体电路30的接触焊盘电连接的PPI线和PPI焊盘的网络。
可以将焊剂(未示出)施加到PPI线56和PPI焊盘60。焊剂主要用来帮助焊料流动，从而使图2(c)所示的焊料球82与PPI焊盘60形成良好的接触。这可以以多种方法中的任何一种包括刷涂或喷涂来实施。焊剂通常具有从焊料表面去除氧化物屏障的酸性成分，并且具有有助于在组装工艺期间阻止芯片在基板表面上移动的粘着特性。
如图2(c)所示，在中空部分58-1顶部上的PPI焊盘60上设置焊料连接件82，其可以是焊料凸块或焊料球。本申请中使用的词语“焊料”包括但不限于铅基焊料和无铅焊料，如用于铅基焊料Pb-Sn组分和包含锡、铜和银或者“SAC”组分的无铅焊料；以及在电气应用中具有共同的熔点并形成导电焊料连接的其它共晶体。焊料连接件82可以是形成为栅格的焊料球阵列中的一种，被称为“球栅阵列”或“BGA”。然而，这里所述的实施例不限于BGA封装件或BGA球。实施例不限于球形或球状的焊料连接件。
图2(c)示出了安装在半导体器件30顶部上的焊料球82的截面图。接触焊盘32连接到PPI线56和PPI焊盘60，其进一步连接到焊料球82。图2(a)至图2(d)所示的工艺仅作说明之用而不用于限制。本领域技术人员能够很容易地预见到加工步骤和加工材料可能有多种变化。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的实施例的精神和范围的情况下，在其中进行各种改变、替换和更改。而且，本申请的范围并不仅限于说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明的发明内容将很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。此外，每条权利要求构成单独的实施例，并且多个权利要求和实施例的组合在本发明的范围内。

Claims (20)

1.一种封装件器件，包括：
接触焊盘，位于电路的表面上；
钝化层，位于所述电路的表面和所述接触焊盘的第一部分的上方，其中所述接触焊盘的第二部分保持外露；
钝化后互连(PPI)线，位于所述钝化层上并接触所述接触焊盘的第二部分；以及
PPI焊盘，连接到所述PPI线，所述PPI焊盘包括中空部分和开口，所述PPI焊盘的顶面与所述PPI线的顶面平齐。
2.根据权利要求1所述的器件，还包括位于所述钝化层与所述PPI线和所述PPI焊盘之间的聚合物层。
3.根据权利要求1所述的器件，还包括位于所述PPI焊盘的中空部分上方并接触所述PPI焊盘的焊料球。
4.根据权利要求1所述的器件，其中，所述PPI焊盘和所述PPI线被制成一个整体。
5.根据权利要求1所述的器件，其中，所述PPI焊盘具有环形、矩形或正方形的形状。
6.根据权利要求1所述的器件，其中，所述PPI焊盘具有外径介于180μm到260μm范围内的环形形状。
7.根据权利要求1所述的器件，其中，所述PPI焊盘具有宽度尺寸介于10μm到130μm范围内的环形形状。
8.根据权利要求1所述的器件，其中，所述PPI焊盘的开口的长度介于10μm到50μm的范围内。
9.根据权利要求1所述的器件，其中，所述PPI焊盘的中空部分的形状是圆形、矩形或正方形。
10.根据权利要求1所述的器件，其中，所述PPI焊盘还包括位于中空部分内的实心部分。
11.根据权利要求10所述的器件，其中，所述实心部分的形状是圆形、矩形或正方形。
12.根据权利要求10所述的器件，其中，所述实心部分是直径介于10μm到160μm范围内的圆形物。
13.根据权利要求10所述的器件，其中，所述实心部分设置在所述PPI的中空部分的中心。
14.一种形成封装件器件的方法，包括：
提供电路，所述电路具有位于所述电路的表面上的接触焊盘；
在所述电路的表面和所述接触焊盘的第一部分的上方形成钝化层，并且暴露出所述接触焊盘的第二部分；
在所述钝化层上形成与所述接触焊盘的第二部分相接触的钝化后互连(PPI)线；以及
形成连接到所述PPI线并包括中空部分和开口的PPI焊盘，所述PPI焊盘的顶面与所述PPI线的顶面平齐。
15.根据权利要求14所述的方法，还包括：
在所述钝化层与所述PPI线和所述PPI焊盘之间形成聚合物层。
16.根据权利要求14所述的方法，还包括：
将焊料球设置于所述PPI焊盘的中空部分的上方并与所述PPI焊盘接触。
17.根据权利要求14所述的方法，其中，作为一个整体同时形成所述PPI焊盘和所述PPI线。
18.根据权利要求14所述的方法，还包括：
在所述中空部分内形成所述PPI焊盘的实心部分。
19.根据权利要求14所述的方法，其中，所述PPI焊盘具有外径介于180μm到260μm范围内的环形形状。
20.一种封装件器件，包括：
接触焊盘，位于电路的表面上；
钝化层，位于所述电路的表面和所述接触焊盘的第一部分的上方，其中所述接触焊盘的第二部分保持外露；
聚合物层，位于所述钝化层和所述接触焊盘的第三部分上，其中所述接触焊盘的第四部分保持外露；
钝化后互连(PPI)线，位于所述聚合物层上并接触所述接触焊盘的第四部分；
PPI焊盘，位于所述聚合物层上并连接到所述PPI线，所述PPI焊盘的顶面与所述PPI线的顶面平齐，所述PPI焊盘包括中空部分和开口；以及
焊料球，位于所述PPI焊盘的中空部分的上方并接触所述PPI焊盘。
CN201210457335.7A 2012-06-08 2012-11-14 封装半导体器件的方法和装置 Active CN103489844B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/492,285 2012-06-08
US13/492,285 US8937388B2 (en) 2012-06-08 2012-06-08 Methods and apparatus of packaging semiconductor devices

Publications (2)

Publication Number Publication Date
CN103489844A CN103489844A (zh) 2014-01-01
CN103489844B true CN103489844B (zh) 2016-09-07

Family

ID=49714621

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210457335.7A Active CN103489844B (zh) 2012-06-08 2012-11-14 封装半导体器件的方法和装置

Country Status (3)

Country Link
US (2) US8937388B2 (zh)
KR (2) KR20130138078A (zh)
CN (1) CN103489844B (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9899329B2 (en) 2010-11-23 2018-02-20 X-Celeprint Limited Interconnection structures and methods for transfer-printed integrated circuit elements with improved interconnection alignment tolerance
US8934259B2 (en) 2011-06-08 2015-01-13 Semprius, Inc. Substrates with transferable chiplets
US20160093600A1 (en) * 2014-09-25 2016-03-31 X-Celeprint Limited Compound micro-assembly strategies and devices
US9799719B2 (en) 2014-09-25 2017-10-24 X-Celeprint Limited Active-matrix touchscreen
US10340258B2 (en) * 2015-04-30 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US10217730B2 (en) 2016-02-25 2019-02-26 X-Celeprint Limited Efficiently micro-transfer printing micro-scale devices onto large-format substrates
US10395966B2 (en) 2016-11-15 2019-08-27 X-Celeprint Limited Micro-transfer-printable flip-chip structures and methods
US10600671B2 (en) 2016-11-15 2020-03-24 X-Celeprint Limited Micro-transfer-printable flip-chip structures and methods
US10224231B2 (en) 2016-11-15 2019-03-05 X-Celeprint Limited Micro-transfer-printable flip-chip structures and methods
US11024608B2 (en) 2017-03-28 2021-06-01 X Display Company Technology Limited Structures and methods for electrical connection of micro-devices and substrates
KR20180136148A (ko) * 2017-06-14 2018-12-24 에스케이하이닉스 주식회사 범프를 구비하는 반도체 장치
CN109786349B (zh) * 2018-01-11 2020-11-03 苏州能讯高能半导体有限公司 一种排气式器件以及器件焊接结构
KR20210058454A (ko) 2019-11-14 2021-05-24 삼성전자주식회사 반도체 패키지
CN112885800A (zh) 2019-11-29 2021-06-01 长鑫存储技术有限公司 半导体结构及其制造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5929521A (en) * 1997-03-26 1999-07-27 Micron Technology, Inc. Projected contact structure for bumped semiconductor device and resulting articles and assemblies
CN101636831A (zh) * 2007-04-23 2010-01-27 弗利普芯片国际有限公司 用于改善的机械和热机械性能的焊料凸点互连

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8368150B2 (en) * 2003-03-17 2013-02-05 Megica Corporation High performance IC chip having discrete decoupling capacitors attached to its IC surface
KR100541394B1 (ko) * 2003-08-23 2006-01-10 삼성전자주식회사 비한정형 볼 그리드 어레이 패키지용 배선기판 및 그의제조 방법
KR101059625B1 (ko) 2008-06-09 2011-08-25 삼성전기주식회사 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법
KR101565798B1 (ko) 2009-03-31 2015-11-05 삼성전자주식회사 콘택 패드와 도전 라인과의 일체형 구조를 가지는 반도체 소자
US8735273B2 (en) * 2011-07-08 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Forming wafer-level chip scale package structures with reduced number of seed layers
US9548281B2 (en) * 2011-10-07 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US9355978B2 (en) * 2013-03-11 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices and methods of manufacture thereof
US9245833B2 (en) * 2012-08-30 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Metal pads with openings in integrated circuits

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5929521A (en) * 1997-03-26 1999-07-27 Micron Technology, Inc. Projected contact structure for bumped semiconductor device and resulting articles and assemblies
CN101636831A (zh) * 2007-04-23 2010-01-27 弗利普芯片国际有限公司 用于改善的机械和热机械性能的焊料凸点互连

Also Published As

Publication number Publication date
KR20130138078A (ko) 2013-12-18
CN103489844A (zh) 2014-01-01
US20130328190A1 (en) 2013-12-12
US9368462B2 (en) 2016-06-14
KR101611772B1 (ko) 2016-04-11
US20150123276A1 (en) 2015-05-07
US8937388B2 (en) 2015-01-20
KR20150016927A (ko) 2015-02-13

Similar Documents

Publication Publication Date Title
CN103489844B (zh) 封装半导体器件的方法和装置
US9633963B2 (en) Packaging devices and methods of manufacture thereof
US9111949B2 (en) Methods and apparatus of wafer level package for heterogeneous integration technology
TWI710085B (zh) 半導體結構及其製造方法
US20160293576A1 (en) Packaging Methods for Semiconductor Devices, Packaged Semiconductor Devices, and Design Methods Thereof
CN106098665B (zh) 互连结构、封装的半导体器件和半导体器件的封装方法
CN102201351A (zh) 半导体器件和形成用于无铅凸块连接的双ubm结构的方法
US9443812B2 (en) Semiconductor device with post-passivation interconnect structure and method of forming the same
US10037953B2 (en) Contact pad for semiconductor devices
US20220230940A1 (en) Barrier Structures Between External Electrical Connectors
US9576888B2 (en) Package on-package joint structure with molding open bumps
CN104425419B (zh) 半导体器件及其制造方法
KR101452587B1 (ko) 이종 집적 기술에 대한 웨이퍼 레벨 패키지의 방법 및 장치
CN104051332B (zh) 封装器件及其制造方法
CN111261609A (zh) 半导体器件及其制备方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant