CN105280508A - 具有凸块结构的基板及其制造方法 - Google Patents

具有凸块结构的基板及其制造方法 Download PDF

Info

Publication number
CN105280508A
CN105280508A CN201410441271.0A CN201410441271A CN105280508A CN 105280508 A CN105280508 A CN 105280508A CN 201410441271 A CN201410441271 A CN 201410441271A CN 105280508 A CN105280508 A CN 105280508A
Authority
CN
China
Prior art keywords
nickel dam
layer
copper
layers
cube structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410441271.0A
Other languages
English (en)
Other versions
CN105280508B (zh
Inventor
吴非艰
廖苍生
黄静怡
李俊德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chipbond Technology Corp
Original Assignee
Chipbond Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipbond Technology Corp filed Critical Chipbond Technology Corp
Publication of CN105280508A publication Critical patent/CN105280508A/zh
Application granted granted Critical
Publication of CN105280508B publication Critical patent/CN105280508B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05022Disposition the internal layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/11452Chemical vapour deposition [CVD], e.g. laser CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/11848Thermal treatments, e.g. annealing, controlled cooling
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13083Three-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)

Abstract

本发明是关于一种具有凸块结构的基板及其制造方法,该基板包括:半导体基板,具有本体、导接垫及保护层;凸块下金属层,电性连接该导接垫;以及凸块结构,包含铜层及镍层,该铜层位于该凸块下金属层与该镍层之间,该铜层与该凸块下金属层电性连接。该制造方法包括:在半导体基板上形成铜层后,借由控制形成于该铜层上的镍层厚度,以使该铜层与该镍层所组成的凸块结构在退火后,该凸块结构的硬度可符合要求,以避免该具有凸块的基板覆晶结合于玻璃基板时,造成该玻璃基板的破裂。

Description

具有凸块结构的基板及其制造方法
技术领域
本发明是有关于一种具有凸块结构的基板及其制造方法,特别是关于一种具有由铜层及镍层组成凸块结构的基板,借由控制镍层厚度,以使该凸块结构在退火后的硬度可符合要求。
背景技术
在覆晶封装技术中,是在芯片的主动面上形成凸块,再借由该凸块使该芯片覆晶结合于玻璃基板,该凸块的材质可为金或铜,然由于黄金价格攀升,因此以该凸块的材质以铜为主流,然由于铜的硬度相较于金的硬度高,因此当该芯片以该铜凸块覆晶结合于该玻璃基板时,会造成该玻璃基板破裂。
由此可见,上述现有的覆晶封装技术中的凸块在结构与使用上,显然仍存在有不便与缺陷,而亟待加以进一步改进。为了解决上述存在的问题,相关厂商莫不费尽心思来谋求解决之道,但长久以来一直未见适用的设计被发展完成,而一般产品又没有适切结构能够解决上述问题,此显然是相关业者急欲解决的问题。
发明内容
本发明的目的在于提供一种具有凸块结构的基板及其制造方法,所要解决的技术问题是借由控制形成于铜层上的镍层厚度,以使该铜层与该镍层所组成的凸块结构在退火后,该凸块结构的硬度可符合要求,其可避免该具有凸块的基板覆晶结合于玻璃基板时,造成该玻璃基板的破裂。
本发明的目的是采用以下技术方案来实现的。本发明提供一种具有凸块结构的基板制造方法,包含:提供半导体基板,该半导体基板具有本体、导接垫及保护层,该导接垫形成于该本体,该保护层覆盖该本体,该保护层具有第一开口,该第一开口显露出该导接垫;形成凸块下金属层,该凸块下金属层覆盖该保护层及该导接垫,该凸块下金属层并与该导接垫电性连接,该凸块下金属层包含有待保留部及待移除部;形成光阻层,该光阻层覆盖该凸块下金属层;图案化该光阻层,经图案化的该光阻层具有第二开口,该第二开口显露出该凸块下金属层的该待保留部;形成铜层,在该光阻层的该第二开口中形成该铜层,该铜层与该凸块下金属层的该待保留部电性连接;形成镍层,在该光阻层的该第二开口中形成该镍层,该镍层形成于该铜层上方,且该镍层与该铜层电性连接,该镍层与该铜层组成凸块结构,该镍层具有上表面及下表面,该上表面至该下表面之间的垂直距离为该镍层的厚度,其中该镍层的厚度由计算式H=12.289D+96.674决定,H为退火后该凸块结构硬度,该凸块结构退火后的硬度单位为Hv,D为该镍层的厚度,该镍层的厚度单位为微米;移除该光阻层,以显露出该凸块下金属层的该待移除部;以及移除该凸块下金属层的待移除部,以该凸块结构为屏蔽,将该凸块下金属层的该待移除部移除,仅保留该凸块下金属层的该待保留部。
本发明的目的还可采用以下技术措施进一步实现。
较佳的,前述的具有凸块结构的基板制造方法,其中该铜层具有顶面及底面,该顶面至该底面之间的垂直距离为该铜层的厚度,其中该铜层的厚度不小于该镍层的厚度。
较佳的,前述的具有凸块结构的基板制造方法,其中在形成镍层的步骤后及在移除该光阻层前,在该光阻层的该第二开口中形成接合层,且该接合层形成于该镍层的该上表面。
本发明的目的还采用以下技术方案来实现的。本发明提供一种具有凸块结构的基板,其中凸块结构具有预定的退火后硬度,该具有凸块结构的基板包含:半导体基板,具有本体、导接垫及保护层,该导接垫形成于该本体,该保护层覆盖该本体,该保护层具有第一开口,该第一开口显露出该导接垫;凸块下金属层,电性连接该导接垫;以及凸块结构,包含铜层及镍层,该铜层位于该凸块下金属层与该镍层之间,该铜层与该凸块下金属层电性连接,该镍层具有上表面及下表面,该上表面至该下表面之间的垂直距离为该镍层的厚度,其中该镍层的厚度由计算式H=12.289D+96.674决定,该凸块结构退火后硬度为H,该凸块结构退火后的硬度单位为Hv,该镍层的厚度为D,该镍层的厚度单位为微米。
本发明的目的还可采用以下技术措施进一步实现。
较佳的,前述的具有凸块结构的基板,其中该铜层具有顶面及底面,该顶面至该底面之间的垂直距离为该铜层的厚度,其中该铜层的厚度不小于该镍层的厚度。
较佳的,前述的具有凸块结构的基板,其中另包含接合层,该接合层形成于该镍层的该上表面。
借由上述技术方案,本发明具有凸块结构的基板及其制造方法至少具有下列优点及有益效果:本发明是借由控制该凸块结构的镍层厚度,以使该凸块结构在退火后的硬度可符合要求,以避免该具有凸块的基板覆晶结合于玻璃基板时,造成该玻璃基板的破裂。
上述说明仅是本发明技术方案的概述,为了能够更清楚了解本发明的技术手段,而可依照说明书的内容予以实施,并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂,以下特举较佳实施例,并配合附图,详细说明如下。
附图说明
图1A至图1H为本发明具有凸块结构的基板制造方法的步骤剖视图。
图2为本发明具有凸块结构的基板覆晶结合于玻璃基板的剖视图。
【主要元件符号说明】
100:具有凸块结构的基板110:半导体基板
111:本体112:导接垫
113:保护层114:第一开口
120:凸块下金属层121:待保留部
122:待移除部130:光阻层
131:第二开口140:铜层
141:顶面142:底面
10:镍层11:上表面
12:下表面160:接合层
200:玻璃基板210:接点
A:凸块结构D:镍层的厚度
D1:铜层的厚度H:凸块结构退火后硬度
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及较佳实施例,对依据本发明提出的一种具有凸块结构的基板及其制造方法的具体实施方式、结构、特征及其功效,详细说明如后。
请参阅图1A至图1H,其揭露一种具有凸块结构的基板制造方法,其包含图1A的“提供半导体基板”步骤、图1B的“形成凸块下金属层”步骤、图1C的“形成光阻层”步骤、图1D的“图案化该光阻层”步骤、图1E的“形成铜层”步骤、图1F的“形成镍层”步骤、图1G的“移除该光阻层”步骤,以及图1H的“移除该凸块下金属层的待移除部”步骤。
首先,请参阅图1A,在“提供半导体基板”步骤中,该半导体基板110具有本体111、导接垫112及保护层113,该导接垫112形成于该本体111,该保护层113覆盖该本体111,该保护层113具有第一开口114,该第一开口114显露出该导接垫112,该导接垫112可选自于铜(Cu)、铝(Al)、铜合金、或其他导电材料。
接着,请参阅图1B,在“形成凸块下金属层”步骤中,该凸块下金属层120覆盖该保护层113及该导接垫112,该凸块下金属层120并与该导接垫112电性连接,该凸块下金属层120包含有待保留部121及待移除部122,该待保留部121连接该导接垫112。
接着,请参阅图1C,在“形成光阻层”步骤中,该光阻层130覆盖该凸块下金属层120。该光阻层130可选自于正光阻膜或为负光阻膜,该光阻层130可经由涂布及固化(curing)等步骤形成该凸块下金属层120上。
接着,请参阅图1D,在“图案化该光阻层”步骤中,以微影技术、刻蚀技术(干刻蚀工艺或湿刻蚀工艺)图案化该光阻层130,经图案化的该光阻层130具有第二开口131,该第二开口131显露出该凸块下金属层120的该待保留部121。
接着,请参阅图1E,在“形成铜层”步骤中,以电镀、无电电镀、印刷、溅镀或化学气相沉积(CVD)法,在该光阻层130的该第二开口131中形成该铜层140,该铜层140具有顶面141及底面142,该铜层140与该凸块下金属层120的该待保留部121电性连接,在本实施例中,该铜层140的该底面142接触该凸块下金属层120的该待保留部121。
接着,请参阅图1F,在“形成镍层”步骤中,可选择以电镀、无电电镀、印刷、溅镀或化学气相沉积(CVD)法,在该光阻层130的该第二开口131中形成该镍层150,该镍层150形成于该铜层140上方,且该镍层150与该铜层140电性连接,在本实施例中该镍层150接触该铜层140的该顶面141,该镍层150与该铜层140组成凸块结构A,在形成该镍层150的步骤中,该镍层150的厚度由计算式H=12.289D+96.674决定,其中H为退火后该凸块结构硬度,D为该镍层的厚度,该凸块结构退火后的硬度单位为Hv,该镍层150具有上表面151及下表面152,该上表面151至该下表面152之间的垂直距离为该镍层的厚度D,该镍层的厚度单位为微米(um)。
请再请参阅图1F,在“形成镍层”步骤中,若欲使退火后凸块结构A的硬度达到用户需求,可借由计算式H=12.289D+96.674控制该镍层150的厚度D,其可避免生产者在形成该镍层150时,因该镍层150厚度不足或厚度太厚,而影响退火后凸块结构A的硬度无法达到使用者需求的问题,且可避免以猜测方式决定该镍层150的厚度后,造成退火后凸块结构A的硬度无法控制的问题,此外,该铜层140的该顶面141及该底面142之间的垂直距离为该铜层140的厚度D1,较佳地,该铜层140的厚度D1不小于该镍层150的厚度D。
请再请参阅图1F,在本实施例中,其中在形成该镍层150后,可选择以电镀、无电电镀、印刷、溅镀或化学气相沉积(CVD)法,在该光阻层130的该第二开口131中形成接合层160,该接合层160形成于该镍层150的该上表面,该接合层160可选自于含金(Au)、锡(Sn)、锡铅(SnPb)、银(Ag)、或其他相似的材料。
接着请参阅图1G,在“移除该光阻层”步骤中,该光阻层130被移除,以显露出该凸块下金属层120的该待移除部122。
最后,请参阅图1H,在“移除该凸块下金属层的待移除部”步骤中,是以该凸块结构A为屏蔽,将该凸块下金属层120的该待移除部122移除,仅保留该凸块结构A下的该待保留部121,以形成具有凸块结构的基板100。
请参阅图2,将该具有凸块结构的基板100覆晶接合于包含有接点210的玻璃基板200上,由于该凸块结构A的该镍层150的厚度由计算式H=12.289D+96.674决定该凸块结构A退火后的硬度,因此可避免该具有凸块结构的基板100覆晶接合于该玻璃基板200时,因该凸块结构A退火后的硬度不符合该玻璃基板200的需求,而造成该玻璃基板200在覆晶接合时破裂。
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制,虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。

Claims (6)

1.一种具有凸块结构的基板制造方法,其特征在于包含:
提供半导体基板,该半导体基板具有本体、导接垫及保护层,该导接垫形成于该本体,该保护层覆盖该本体,该保护层具有第一开口,该第一开口显露出该导接垫;
形成凸块下金属层,该凸块下金属层覆盖该保护层及该导接垫,该凸块下金属层并与该导接垫电性连接,该凸块下金属层包含有待保留部及待移除部;
形成光阻层,该光阻层覆盖该凸块下金属层;
图案化该光阻层,经图案化的该光阻层具有第二开口,该第二开口显露出该凸块下金属层的该待保留部;
形成铜层,在该光阻层的该第二开口中形成该铜层,该铜层与该凸块下金属层的该待保留部电性连接;
形成镍层,在该光阻层的该第二开口中形成该镍层,该镍层形成于该铜层上方,且该镍层与该铜层电性连接,该镍层与该铜层组成凸块结构,该镍层具有上表面及下表面,该上表面至该下表面之间的垂直距离为该镍层的厚度,其中该镍层的厚度由计算式H=12.289D+96.674决定,H为退火后该凸块结构硬度,该凸块结构退火后的硬度单位为Hv,D为该镍层的厚度,该镍层的厚度单位为微米;
移除该光阻层,以显露出该凸块下金属层的该待移除部;以及
移除该凸块下金属层的待移除部,以该凸块结构为屏蔽,将该凸块下金属层的该待移除部移除,仅保留该凸块下金属层的该待保留部。
2.如权利要求1所述的具有凸块结构的基板制造方法,其特征在于该铜层具有顶面及底面,该顶面至该底面之间的垂直距离为该铜层的厚度,其中该铜层的厚度不小于该镍层的厚度。
3.如权利要求1所述的具有凸块结构的基板制造方法,其特征在于在形成镍层的步骤后及在移除该光阻层前,在该光阻层的该第二开口中形成接合层,且该接合层形成于该镍层的该上表面。
4.一种具有凸块结构的基板,其中凸块结构具有预定的退火后硬度,其特征在于该具有凸块结构的基板包含:
半导体基板,具有本体、导接垫及保护层,该导接垫形成于该本体,该保护层覆盖该本体,该保护层具有第一开口,该第一开口显露出该导接垫;
凸块下金属层,电性连接该导接垫;以及
凸块结构,包含铜层及镍层,该铜层位于该凸块下金属层与该镍层之间,该铜层与该凸块下金属层电性连接,该镍层具有上表面及下表面,该上表面至该下表面之间的垂直距离为该镍层的厚度,其中该镍层的厚度由计算式H=12.289D+96.674决定,该凸块结构退火后硬度为H,该凸块结构退火后的硬度单位为Hv,该镍层的厚度为D,该镍层的厚度单位为微米。
5.如权利要求4所述的具有凸块结构的基板,其特征在于该铜层具有顶面及底面,该顶面至该底面之间的垂直距离为该铜层的厚度,其中该铜层的厚度不小于该镍层的厚度。
6.如权利要求4所述的具有凸块结构的基板,其特征在于另包含接合层,该接合层形成于该镍层的该上表面。
CN201410441271.0A 2014-07-25 2014-08-29 具有凸块结构的基板及其制造方法 Active CN105280508B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW103125555A TWI488244B (zh) 2014-07-25 2014-07-25 具有凸塊結構的基板及其製造方法
TW103125555 2014-07-25

Publications (2)

Publication Number Publication Date
CN105280508A true CN105280508A (zh) 2016-01-27
CN105280508B CN105280508B (zh) 2018-11-16

Family

ID=52208796

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201420500399.5U Withdrawn - After Issue CN204067341U (zh) 2014-07-25 2014-08-29 具有凸块结构的基板
CN201410441271.0A Active CN105280508B (zh) 2014-07-25 2014-08-29 具有凸块结构的基板及其制造方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201420500399.5U Withdrawn - After Issue CN204067341U (zh) 2014-07-25 2014-08-29 具有凸块结构的基板

Country Status (6)

Country Link
US (1) US9177830B1 (zh)
JP (1) JP2016032090A (zh)
KR (1) KR20160012857A (zh)
CN (2) CN204067341U (zh)
SG (1) SG10201407629YA (zh)
TW (1) TWI488244B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107481988A (zh) * 2017-07-28 2017-12-15 永道无线射频标签(扬州)有限公司 一种未使用导电胶的覆晶芯片封装产品及其制作工艺
CN108231728A (zh) * 2016-12-12 2018-06-29 英飞凌科技奥地利有限公司 半导体器件、电子组件及方法
CN110310939A (zh) * 2018-03-27 2019-10-08 矽品精密工业股份有限公司 基板结构及其制法及导电凸块

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI488244B (zh) * 2014-07-25 2015-06-11 Chipbond Technology Corp 具有凸塊結構的基板及其製造方法
US10692830B2 (en) * 2017-10-05 2020-06-23 Texas Instruments Incorporated Multilayers of nickel alloys as diffusion barrier layers
US11127704B2 (en) 2017-11-28 2021-09-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with bump structure and method of making semiconductor device
TW201930646A (zh) * 2018-01-05 2019-08-01 頎邦科技股份有限公司 具凸塊結構之半導體裝置及其製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63224241A (ja) * 1987-03-12 1988-09-19 Toshiba Corp 半導体装置の製造方法
US20030030142A1 (en) * 2001-07-25 2003-02-13 Rohm Co., Ltd. Semiconductor device and method of manufacturing the same
CN101944496A (zh) * 2009-07-02 2011-01-12 台湾积体电路制造股份有限公司 柱状结构及其形成方法、倒装芯片接合结构
CN204067341U (zh) * 2014-07-25 2014-12-31 颀邦科技股份有限公司 具有凸块结构的基板

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000323510A (ja) * 1999-05-11 2000-11-24 Shinko Electric Ind Co Ltd 柱状電極付き半導体ウエハ及びその製造方法並びに半導体装置
TWI252546B (en) 2004-11-03 2006-04-01 Advanced Semiconductor Eng Bumping process and structure thereof
JP2007287906A (ja) * 2006-04-17 2007-11-01 Elpida Memory Inc 電極と電極の製造方法、及びこの電極を備えた半導体装置
US8269345B2 (en) 2007-10-11 2012-09-18 Maxim Integrated Products, Inc. Bump I/O contact for semiconductor device
TW201019440A (en) 2008-11-03 2010-05-16 Int Semiconductor Tech Ltd Bumped chip and semiconductor flip-chip device applied from the same
US8736050B2 (en) 2009-09-03 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Front side copper post joint structure for temporary bond in TSV application
US8659155B2 (en) 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US8492891B2 (en) * 2010-04-22 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with electrolytic metal sidewall protection
US8546254B2 (en) 2010-08-19 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps using patterned anodes
TW201227898A (en) 2010-12-24 2012-07-01 Unimicron Technology Corp Package substrate and fabrication method thereof
TWI440150B (zh) 2011-05-20 2014-06-01 Chipbond Technology Corp 凸塊製程及其結構
CN102800599B (zh) 2011-05-25 2015-03-25 颀邦科技股份有限公司 凸块工艺及其结构
JP6035714B2 (ja) * 2011-08-17 2016-11-30 ソニー株式会社 半導体装置、半導体装置の製造方法、及び、電子機器
US9978656B2 (en) 2011-11-22 2018-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming fine-pitch copper bump structures
JP6076020B2 (ja) 2012-02-29 2017-02-08 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
US9082764B2 (en) * 2012-03-05 2015-07-14 Corning Incorporated Three-dimensional integrated circuit which incorporates a glass interposer and method for fabricating the same
US9111817B2 (en) * 2012-09-18 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structure and method of forming same
TWM490108U (en) * 2014-07-25 2014-11-11 Chipbond Technology Corp Substrate with bump structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63224241A (ja) * 1987-03-12 1988-09-19 Toshiba Corp 半導体装置の製造方法
US20030030142A1 (en) * 2001-07-25 2003-02-13 Rohm Co., Ltd. Semiconductor device and method of manufacturing the same
CN101944496A (zh) * 2009-07-02 2011-01-12 台湾积体电路制造股份有限公司 柱状结构及其形成方法、倒装芯片接合结构
CN204067341U (zh) * 2014-07-25 2014-12-31 颀邦科技股份有限公司 具有凸块结构的基板

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108231728A (zh) * 2016-12-12 2018-06-29 英飞凌科技奥地利有限公司 半导体器件、电子组件及方法
US11380612B2 (en) 2016-12-12 2022-07-05 Infineon Technologies Austria Ag Semiconductor device, electronic component and method
CN107481988A (zh) * 2017-07-28 2017-12-15 永道无线射频标签(扬州)有限公司 一种未使用导电胶的覆晶芯片封装产品及其制作工艺
CN110310939A (zh) * 2018-03-27 2019-10-08 矽品精密工业股份有限公司 基板结构及其制法及导电凸块

Also Published As

Publication number Publication date
US9177830B1 (en) 2015-11-03
SG10201407629YA (en) 2016-02-26
JP2016032090A (ja) 2016-03-07
TWI488244B (zh) 2015-06-11
KR20160012857A (ko) 2016-02-03
CN204067341U (zh) 2014-12-31
CN105280508B (zh) 2018-11-16
TW201604979A (zh) 2016-02-01

Similar Documents

Publication Publication Date Title
CN105280508A (zh) 具有凸块结构的基板及其制造方法
JP5525140B2 (ja) 均一な無電解メッキ厚さを得ることができる半導体素子の製造方法
CN102054790B (zh) 半导体元件及其制造方法
CN102201351B (zh) 半导体器件和形成用于无铅凸块连接的双ubm结构的方法
US10797011B2 (en) Method of forming solder bumps
TWI478255B (zh) 回銲前銲料凸塊之清除
KR101108784B1 (ko) 도전성 전극 패턴 및 이를 구비하는 태양전지
CN102222647A (zh) 半导体裸片及形成导电元件的方法
CN102790009B (zh) 降低铜电镀工艺中边缘效应的方法及铜互连结构制造方法
TW200849422A (en) Wafer structure and method for fabricating the same
CN102034721B (zh) 芯片封装方法
CN104681454A (zh) 用于新型指纹锁器件的封装工艺
US11923287B2 (en) Method for manufacturing semiconductor device having chip stacked and molded
JP5248627B2 (ja) 半導体のマイクロパッド形成方法
CN105140140B (zh) 一种晶圆级焊锡微凸点的制作方法
TWI478300B (zh) 覆晶式封裝基板及其製法
US10609813B2 (en) Capacitive interconnect in a semiconductor package
CN105374775B (zh) 焊盘、半导体器件和半导体器件的制造工艺
US10008478B2 (en) Fabricating method for wafer-level packaging
JP3194419U (ja) 基板
JP2011129669A (ja) 半導体チップ及び該半導体チップを備えた半導体装置
US11398408B2 (en) Semiconductor substrate with trace connected to via at a level within a dielectric layer
US20230027674A1 (en) Semiconductor device and method of manufacturing the same
KR101663854B1 (ko) 무전해도금을 이용한 터치패널 형성 방법
CN107482048A (zh) 包括通孔的电子器件及其形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant