CN107481988A - 一种未使用导电胶的覆晶芯片封装产品及其制作工艺 - Google Patents

一种未使用导电胶的覆晶芯片封装产品及其制作工艺 Download PDF

Info

Publication number
CN107481988A
CN107481988A CN201710628819.6A CN201710628819A CN107481988A CN 107481988 A CN107481988 A CN 107481988A CN 201710628819 A CN201710628819 A CN 201710628819A CN 107481988 A CN107481988 A CN 107481988A
Authority
CN
China
Prior art keywords
chip
copper
substrate
aluminium
unused
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710628819.6A
Other languages
English (en)
Other versions
CN107481988B (zh
Inventor
李宗庭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yongdao Radio Frequency Technology Co.,Ltd.
Original Assignee
ARIZON RFID TECHNOLOGY (YANGZHOU) Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARIZON RFID TECHNOLOGY (YANGZHOU) Co Ltd filed Critical ARIZON RFID TECHNOLOGY (YANGZHOU) Co Ltd
Priority to CN201710628819.6A priority Critical patent/CN107481988B/zh
Publication of CN107481988A publication Critical patent/CN107481988A/zh
Application granted granted Critical
Publication of CN107481988B publication Critical patent/CN107481988B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L21/603Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81007Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053Bonding environment
    • H01L2224/81095Temperature settings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding

Abstract

一种未使用导电胶的覆晶芯片封装产品及其制作工艺,属于RFID技术领域。本发明用于芯片与基板的覆晶接合结构上,在基板上预长金属粒子(金属珠)做为IC芯片凸块接点或厚垫接点(即Bump或PAD),与基板接点形成电气导通的材料,取代以往使用的ACP(或ACF)内的导电粒子做为芯片与基板电气导通的材料;再使用一般不导电的结构胶(不含导电粒子,不导电材料,加热固化型的胶或UV固化的胶),取代以往使用的异方性导电胶(ACP or ACF);在工艺上,使用Flip chip bonding(覆晶封装),在热压时使用140℃‑360℃的温度。

Description

一种未使用导电胶的覆晶芯片封装产品及其制作工艺
技术领域
本发明涉及一种未使用导电胶的覆晶芯片封装产品结构及其制作工艺,属于芯片封装技术领域。
背景技术
金凸块覆晶封装是芯片的线路面朝向基板的金属线路面接合,其中芯片线路面的接点上有硬度约30-120HV的金凸块(芯片上的金属凸块接点,Bump), 其中芯片是指未封装的积体电路(IC)。而介于芯片与天线之间接合二者的是异方性导电胶(ACP,只在异方性导电胶的上下方向导通,其他方向绝缘的胶), 这ACP内掺有导电粒子及热固胶。接合时,由较Bump硬的导电粒子嵌在Bump与天线的金属箔之间形成导通,而ACP内的热固胶填充于芯片与天线之间形成接合力(如图1所示)。
上述做法其缺点如下:
1)ACP是热固胶掺入粒径极均匀的导电粒子,且要求均匀分布, 这材料成本很贵;2)ACP内有导电粒子,接合时, 芯片Bump与天线金属引脚必须精密对准, 若上下对准稍有偏差, Bump将透过导电粒子与另一个天线引脚短路(如图2所示);
3)芯片上的Bump是纯金,厚度大,成本高。
发明内容
本发明的目的是针对上述现有技术的不足,提供一种未使用导电胶的覆晶芯片封装产品及其制作工艺。本发明用于芯片与基板的覆晶接合结构上,在基板上预长金属粒子(金属珠)做为IC芯片凸块接点或厚垫接点(即Bump或PAD,),与基板接点形成电气导通的材料,取代以往使用的ACP(或ACF)内的导电粒子做为芯片与基板电气导通的材料;再使用一般不导电的结构胶(不含导电粒子,不导电材料,加热固化型的胶或UV固化的胶),取代以往使用的的异方性导电胶(ACP or ACF);在工艺上,使用Flip chip bonding (覆晶封装),在热压时使用140℃-360℃的温度。
本发明的技术方案是:一种未使用导电胶的覆晶芯片封装产品,包括覆晶封装的芯片、基板,其特征是,所述基板上的金属箔经过加热熔融成金属珠,该金属珠分布在基板接点上,在芯片与基板之间填塞不导电的结构胶,使基板上金属珠接触或嵌入芯片的Bump或芯片的PAD上。
进一步地,所述基板上的金属箔及金属珠为铝、铜、银、锡、铜镀金、铜镀锡、铜镀镍金或铜镀锡铅材质。
进一步地,所述不导电的结构胶为热固胶或UV胶。
进一步地,所述基板为PET+铝软性基板、PET+铜软性基板、PI+铝软性基板、PI+铜软性基板、FR4+铜载板、FR4+铝载板、BT+铜载板或BT+铝载板。
进一步地,所述芯片上的Bump或PAD 材料为金、银、铜、铝、锡、铜镀金、铜镀锡、铜镀镍金或铜镀锡铅。
进一步地,所述芯片上的Bump或PAD材料覆盖一层0.1um-5um厚的防氧化树脂薄膜。
上述一种未使用导电胶的覆晶芯片封装产品的制作工艺,其特征是,包括以下步骤:
1)覆晶封装的芯片与基板接合结构上,采用激光或等离子细微热加工方法,对基板的金属箔做加工,使之形成与基板金属熔接一起的金属珠,做为芯片与天线基板之间的电气接点,金属珠分布在基板接点上,并与基板接点连接;
2)在芯片与基板之间填塞不导电的结构胶,以提供芯片与基板的结合力,使基板上金属珠接触或嵌入芯片Bump或芯片PAD,所述不导电的结构胶为热固胶或UV胶;
3)若使用热固胶,在热压时使用140℃-360℃的温度,使基板上金属珠接触或嵌入芯片的金属Bump或PAD上,同时热固胶固化后提供黏结力及结构强度来保护芯片与天线基板的接合。
进一步地,所述芯片上的Bump或PAD 材料是金、银、铜、铝、锡、铜镀金、铜镀锡、铜镀镍金或铜镀锡铅。
进一步地,所述芯片上的Bump或PAD材料上覆盖一层0.1um-5um厚的防氧化树脂薄膜,在芯片与基板热压时,基板上的金属珠在热及压应力下刺破树脂薄膜,与Bump或PAD上的金属接触导通。
进一步地,所述基板的线路金属是铝、铜、银、锡、铜镀金、铜镀锡、铜镀镍金或铜镀锡铅;所述基板为PET+铝软性基板、PET+铜软性基板、PI+铝软性基板、PI+铜软性基板、FR4+铜载板、FR4+铝载板、BT+铜载板或BT+铝载板。
本发明的优点在于:
1)使用多颗预先加工好且固定位置的金属珠来做为导电媒介, 取代位置散乱的导电粒子,bonding时对准稍有偏差也不会因导电粒子介于其间而与邻近引脚短路,可容许芯片Bonding时较大的对准误差, 或使用更小天线引脚间距,这代表可用更小的芯片, 这对降低芯片成本有很大效益;
2)使用绝缘的热固胶取代异方性导电胶,可大幅降低成本;
3)应用在RFID天线与芯片的封装制程上,与现有成熟的工艺及设备可直接兼容,实用性高。
附图说明
图1为背景技术中芯片bonding截面图;
图2为背景技术中覆晶芯片bonding下视图;
图3(a)为本发明中基板上视图;
图3(b)为本发明中基板截面图;
图4为本发明中芯片bonding截面图。
具体实施方式
一种未使用导电胶的覆晶芯片封装产品,包括覆晶封装的芯片、基板,基板上的金属箔经过加热熔融成金属珠,该金属珠分布在基板接点上,在芯片与基板之间填塞不导电的结构胶(热固胶或UV胶),使基板上金属珠接触或嵌入芯片的Bump或芯片的PAD上。
上述金属珠为铝、铜、银、锡、铜镀金、铜镀锡、铜镀镍金或铜镀锡铅材质。
上述基板为PET+铝软性基板、PET+铜软性基板、PI+铝软性基板、PI+铜软性基板、FR4+铜载板、FR4+铝载板、BT+铜载板或BT+铝载板。
上述芯片上的Bump或PAD 材料为金、银、铜、铝、锡、铜镀金、铜镀锡、铜镀镍金或铜镀锡铅。
上述芯片上的Bump或PAD材料覆盖一层0.1um-5um厚的防氧化树脂薄膜。
一种未使用导电胶的覆晶芯片封装产品的制作工艺,包括以下步骤:在覆晶封装的芯片与基板接合结构上,
1)在基板金属上以以激光(Laser)或等离子(Plasma)等细微热加工方法,对基板的金属箔做加工,使之形成熔融的金属珠(铝铢、铜铢、银珠等)。以此金属珠取代ACP中的导电粒子,做为芯片与天线之间的电气接点(如图3(a))。
2)金属珠由基板上的金属热融化后形成,分布在基板接点上与基板接点已连接(如图3(b))。
3)芯片与基板之间填塞不导电的结构胶(例如环氧树脂,UV胶)取代以往的ACP或ACF来提供芯片与基板的结合力,使基板上金属珠接触或嵌入芯片Bump(或芯片PAD)(如图4)。
4)在工艺上,仍可以使用Flip chip bonding (覆晶封装),在热压时仍使用140℃-360℃的温度(使用热固胶时),使基板上金属珠接触或嵌入芯片的金属Bump或PAD上,同时热固胶固化后提供黏结力及结构强度来保护芯片与天线的接合,基本上实现可使用行业内既有的bonding机器设备导入本发明。
基板的线路金属是铝,铜,银,锡 或铜镀金,铜镀锡,铜镀镍金,铜镀锡铅。基板可以是PET+铝, PET+铜, PI+铝,PI+铜等软性基板或FR4,BT载板,或其他高密度载板。
芯片上的Bump或PAD 材料可以是金,银,铜,铝,锡 或铜镀金,铜镀锡,铜镀镍金,铜镀锡铅。芯片上的Bump或PAD材料可以是以上金属并覆盖一层0.1um-5um厚的防氧化树脂薄膜,在芯片与基板热压时,基板上的金属珠在热及压应力下刺破树脂薄膜与Bump上的金属接触导通。
本发明的优点是:加工基板金属熔融为金属珠,以此取代ACP或ACF中的导电粒子,做为芯片与天线之间的电气接点;使用一般不导电的热固化胶或UV胶 取代以往的异方性导电胶(ACP or ACF)填在芯片与天线之间提供结合强度。

Claims (10)

1.一种未使用导电胶的覆晶芯片封装产品,包括覆晶封装的芯片、基板,其特征是,所述基板上的金属箔经过加热熔融成金属珠,该金属珠分布在基板接点上,在芯片与基板之间填塞不导电的结构胶,使基板上金属珠接触或嵌入芯片的Bump或芯片的PAD上。
2.根据权利要求1所述的一种未使用导电胶的覆晶芯片封装产品,其特征是,所述基板上的金属箔及金属珠为铝、铜、银、锡、铜镀金、铜镀锡、铜镀镍金或铜镀锡铅材质。
3.根据权利要求1所述的一种未使用导电胶的覆晶芯片封装产品,其特征是,所述不导电的结构胶为热固胶或UV胶。
4.根据权利要求1所述的一种未使用导电胶的覆晶芯片封装产品,其特征是,所述基板为PET+铝软性基板、PET+铜软性基板、PI+铝软性基板、PI+铜软性基板、FR4+铜载板、FR4+铝载板、BT+铜载板或BT+铝载板。
5. 根据权利要求1所述的一种未使用导电胶的覆晶芯片封装产品,其特征是,所述芯片上的Bump或PAD 材料为金、银、铜、铝、锡、铜镀金、铜镀锡、铜镀镍金或铜镀锡铅。
6.根据权利要求1所述的一种未使用导电胶的覆晶芯片封装产品,其特征是,所述芯片上的Bump或PAD材料覆盖一层0.1um-5um厚的防氧化树脂薄膜。
7.根据权利要求1-6中任一项所述的一种未使用导电胶的覆晶芯片封装产品的制作工艺,其特征是,包括以下步骤:
1)覆晶封装的芯片与基板接合结构上,采用激光或等离子细微热加工方法,对基板的金属箔做加工,使之形成与基板金属熔接一起的金属珠,做为芯片与天线基板之间的电气接点,金属珠分布在基板接点上,并与基板接点连接;
2)在芯片与基板之间填塞不导电的结构胶,以提供芯片与基板的结合力,使基板上金属珠接触或嵌入芯片Bump或芯片PAD,所述不导电的结构胶为热固胶或UV胶;
3)若使用热固胶,在热压时使用140℃-360℃的温度,使基板上金属珠接触或嵌入芯片的金属Bump或PAD上,同时热固胶固化后提供黏结力及结构强度来保护芯片与天线基板的接合。
8. 根据权利要求7所述的一种未使用导电胶的覆晶芯片封装产品的制作工艺,其特征是,所述芯片上的Bump或PAD 材料是金、银、铜、铝、锡、铜镀金、铜镀锡、铜镀镍金或铜镀锡铅。
9.根据权利要求8所述的一种未使用导电胶的覆晶芯片封装产品的制作工艺,其特征是,所述芯片上的Bump或PAD材料上覆盖一层0.1um-5um厚的防氧化树脂薄膜,在芯片与基板热压时,基板上的金属珠在热及压应力下刺破树脂薄膜,与Bump或PAD上的金属接触导通。
10.根据权利要求7所述的一种未使用导电胶的覆晶芯片封装产品的制作工艺,其特征是,所述基板的线路金属是铝、铜、银、锡、铜镀金、铜镀锡、铜镀镍金或铜镀锡铅;所述基板为PET+铝软性基板、PET+铜软性基板、PI+铝软性基板、PI+铜软性基板、FR4+铜载板、FR4+铝载板、BT+铜载板或BT+铝载板。
CN201710628819.6A 2017-07-28 2017-07-28 一种未使用导电胶的覆晶芯片封装产品及其制作工艺 Active CN107481988B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710628819.6A CN107481988B (zh) 2017-07-28 2017-07-28 一种未使用导电胶的覆晶芯片封装产品及其制作工艺

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710628819.6A CN107481988B (zh) 2017-07-28 2017-07-28 一种未使用导电胶的覆晶芯片封装产品及其制作工艺

Publications (2)

Publication Number Publication Date
CN107481988A true CN107481988A (zh) 2017-12-15
CN107481988B CN107481988B (zh) 2020-09-01

Family

ID=60597137

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710628819.6A Active CN107481988B (zh) 2017-07-28 2017-07-28 一种未使用导电胶的覆晶芯片封装产品及其制作工艺

Country Status (1)

Country Link
CN (1) CN107481988B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108878678A (zh) * 2018-06-14 2018-11-23 武汉华星光电半导体显示技术有限公司 导电胶结构制作方法、导电胶结构及显示面板组件
CN112820843A (zh) * 2021-01-20 2021-05-18 合肥维信诺科技有限公司 柔性显示面板及显示装置
CN114170925A (zh) * 2021-12-07 2022-03-11 Tcl华星光电技术有限公司 显示模组及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1313631A (zh) * 2000-03-13 2001-09-19 华泰电子股份有限公司 覆晶件晶片的结合方法
CN1812080A (zh) * 2005-01-12 2006-08-02 台湾薄膜电晶体液晶显示器产业协会 覆晶构装的装置
CN101483210A (zh) * 2008-01-09 2009-07-15 林原 发光二极管的基板结构
CN103855043A (zh) * 2014-03-12 2014-06-11 南通富士通微电子股份有限公司 半导体封装倒装焊接方法
TW201517181A (zh) * 2013-09-25 2015-05-01 Nitto Denko Corp 半導體裝置之製造方法
CN105280508A (zh) * 2014-07-25 2016-01-27 颀邦科技股份有限公司 具有凸块结构的基板及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1313631A (zh) * 2000-03-13 2001-09-19 华泰电子股份有限公司 覆晶件晶片的结合方法
CN1812080A (zh) * 2005-01-12 2006-08-02 台湾薄膜电晶体液晶显示器产业协会 覆晶构装的装置
CN101483210A (zh) * 2008-01-09 2009-07-15 林原 发光二极管的基板结构
TW201517181A (zh) * 2013-09-25 2015-05-01 Nitto Denko Corp 半導體裝置之製造方法
CN103855043A (zh) * 2014-03-12 2014-06-11 南通富士通微电子股份有限公司 半导体封装倒装焊接方法
CN105280508A (zh) * 2014-07-25 2016-01-27 颀邦科技股份有限公司 具有凸块结构的基板及其制造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108878678A (zh) * 2018-06-14 2018-11-23 武汉华星光电半导体显示技术有限公司 导电胶结构制作方法、导电胶结构及显示面板组件
CN112820843A (zh) * 2021-01-20 2021-05-18 合肥维信诺科技有限公司 柔性显示面板及显示装置
CN114170925A (zh) * 2021-12-07 2022-03-11 Tcl华星光电技术有限公司 显示模组及其制作方法

Also Published As

Publication number Publication date
CN107481988B (zh) 2020-09-01

Similar Documents

Publication Publication Date Title
CN100473255C (zh) 倒装芯片连接用电路板及其制造方法
CN102148179B (zh) 粘结薄膜的使用方法
CN102047404B (zh) 半导体装置和倒装芯片安装方法及倒装芯片安装装置
JP2002198394A (ja) 基板へのフリップチップ実装方法
WO2000045431A1 (en) Method of packaging semiconductor device using anisotropic conductive adhesive
JP4180206B2 (ja) 半導体装置の製造方法
KR20090051721A (ko) 전기 부품의 접속 방법
CN107112253B (zh) 凸点形成用膜、半导体装置及其制造方法以及连接构造体
CN102215639A (zh) 半导体芯片内置配线基板及其制造方法
JP6303597B2 (ja) 電子部品モジュールの製造方法
KR20170016550A (ko) 반도체 패키지의 제조 방법
CN107481988A (zh) 一种未使用导电胶的覆晶芯片封装产品及其制作工艺
CN100485895C (zh) 内埋式晶片封装结构及其工艺
TWI658518B (zh) 電路零件的製造方法及電路零件
CN107454741B (zh) 导电粒子、电路部件的连接材料、连接构造以及连接方法
JP2016131246A (ja) 多層基板
CN102194707B (zh) 制造半导体结构的方法
KR100874540B1 (ko) 이방 도전성 접착 캡슐
JPH08202844A (ja) 電子機器及びその製造方法
CN107424966B (zh) 一种覆晶芯片与软性基板封装的结构及方法
JPH11163048A (ja) 半導体チップの実装方法
JP5608504B2 (ja) 接続方法及び接続構造体
JP4441090B2 (ja) プリント配線基板に半導体チップを装着する方法
MX2008012339A (es) Metodos para sujetar un montaje de circuito integrado de un chip invertido a un sustrato.
CN100474574C (zh) 芯片封装体

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: 225009 No. 88 Wuzhou East Road, Yangzhou Economic Development Zone, Jiangsu

Patentee after: Yongdao Radio Frequency Technology Co.,Ltd.

Address before: 225009 No. 88 Wuzhou East Road, Yangzhou Economic Development Zone, Jiangsu

Patentee before: ARIZON RFID TECHNOLOGY (YANGZHOU) Co.,Ltd.

CP01 Change in the name or title of a patent holder