CN1313631A - 覆晶件晶片的结合方法 - Google Patents

覆晶件晶片的结合方法 Download PDF

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CN1313631A
CN1313631A CN00103473A CN00103473A CN1313631A CN 1313631 A CN1313631 A CN 1313631A CN 00103473 A CN00103473 A CN 00103473A CN 00103473 A CN00103473 A CN 00103473A CN 1313631 A CN1313631 A CN 1313631A
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wafer
substrate
projection
metallic conductor
brazing metal
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谢文乐
庄永成
黄宁
陈慧萍
蒋华文
张衷铭
涂丰昌
黄富裕
张轩睿
胡嘉杰
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HUATAI ELECTRONICS CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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Abstract

一种覆晶件晶片的结合方法。为提供一种缩短晶片结合时间、提高生产效率及提高产品质量的半导体元件覆晶技术,提出本发明,它包括在晶圆上预设金属导体凸块,并切割形成晶片、在基板上形成与晶片上金属导体凸块相对应的金属焊料凸块;在基板上涂布封胶材料;将晶片翻转,使其上金属导体凸块面朝下,并对正基板上形成的金属焊料凸块;以晶片上的金属导体凸块与基板上金属焊料凸块接触,并施以压合加热。

Description

覆晶件晶片的结合方法
本发明属于半导体元件覆晶技术，特别是一种覆晶件晶片的结合方法。
如图1、图2、图3、图4所示，习用的覆晶件(flip chip)包括晶片(die)10及基板(substrate)12。其上晶片10的结合方法包括如下步骤：
第一步骤
如图1所示，在从晶圆厂生产制造完成的晶圆(wafer)上预先设置为金凸块(Au-Bump)或高温铅凸块(Solder-Bump)的金属导体凸块11，并切割成适当大小形成晶片(die)10；
第二步骤
如图2所示，在基板上涂布封胶材料13，并在晶片10的金属导体凸块11上沾设导电胶14；
第三步骤
如图3所示，将晶片10翻转，使其上金属导体凸块11面朝下；
第四步骤
如图4所示，以晶片10上沾有导电胶14的金属导体凸块11与基板12接触构成接触点进行加热结合。
上述使用的覆晶技术虽不再使用传统的打线(wire bond)及引脚技术，直接把晶片10贴到基板12上，而在贴晶片10时，必须先在晶片10的金属导体凸块11上沾导电胶14，并在基板12上涂布封胶材料(underfil)13，再将晶片10翻转后贴到基板12的相对位置上，使晶片10的的金属导体凸块11与基板12胶合，而由于使用沾胶方式，以导电胶14来胶合凸块11与基板12，必须先进行一道沾胶工序、且胶固的时间过于冗长，不符合大量生间的经济效益，且存在有胶合的黏固力不佳、易脱落或造成黏合不牢、结合度不足等缺点。即习知覆晶技术中须在晶片10导体凸块11上沾导电胶14、在基板12上涂布封胶材料13，并与基板12压合加热结合，此种方法导致在晶片10结合时，必须等约24小时待导电胶14胶固后，方能使晶片10与基板12确实结合，从而影响后续加工制作流程的时间。
本发明的目的是提供一种缩短晶片结合时间、提高生产效率及提高产品质量的覆晶件晶片的结合方法。
本发明包括如下步骤：
第一步骤
在从晶圆厂生产制造完成的晶圆上预先设置金属导体凸块，并切割成适当大小形成晶片；在基板上与晶片结合的预留位置上，形成与晶片上金属导体凸块相对应的金属焊料凸块；第二步骤
在基板上涂布封胶材料；
第三步骤
将晶片翻转，使其上金属导体凸块面朝下，并对正基板上形成的金属焊料凸块；
第四步骤
以晶片上的金属导体凸块与基板上金属焊料凸块接触，并施以压合加热，使晶片上金属导体凸块藉由基板上加热融熔后再硬化焊固的金属焊料凸块牢固地焊接结合于基板上。
其中：
基板上的金属焊料凸块以印刷方式形成。
基板上的金属焊料凸块以电镀方式形成。
基板上的金属焊料凸块具备较高温融焊特性。
由于本发明包括在晶圆上预设金属导体凸块，并切割形成晶片、在基板上形成与晶片上金属导体凸块相对应的金属焊料凸块；在基板上涂布封胶材料；将晶片翻转，使其上金属导体凸块面朝下，并对正基板上形成的金属焊料凸块；以晶片上的金属导体凸块与基板上金属焊料凸块接触，并施以压合加热。由于金属焊料凸块具备较高温融焊特性，以经第四步骤压合加热后，待温度降低后即可焊固，可很快进行后续加工制作流程，缩短晶片结合时间，大幅度提高生产效率；避免了习知覆晶技术中须在晶片导体凸块上沾导电胶、在基板上涂布封胶材料，并与基板压合加热结合，从而导致在晶片结合时，必须等约24小时待导电胶胶固后，方能使晶片与基板确实结合的情形，不仅缩短晶片结合时间、提高生产效率，而且提高产品质量，从而达到本发明的目的。
图1、为习用的晶片结合方法示意图(第一步骤)。
图2、为习用的晶片结合方法示意图(第二步骤)。
图3、为习用的晶片结合方法示意图(第三步骤)。
图4、为习用的晶片结合方法示意图(第四步骤)。
图5、为本发明示意图(第一步骤)。
图6、为本发明示意图(第二步骤)。
图7、为本发明示意图(第三步骤)。
图8、为本发明示意图(第四步骤)。
图9、为图8中A部局部放大图。
下面结合附图对本发明进一步详细阐述。
如图5所示，本发明制作的覆晶件包括晶片20及基板22。
本发明包括如下步骤：
第一步骤
如图5所示，在从晶圆厂生产制造完成的晶圆(wafer)上预先设置为金凸块或高温铅凸块的金属导体凸块21，并切割成适当大小形成晶片20；在基板22上与晶片20结合的预留位置上，以印刷或电镀方式形成与晶片20上金属导体凸块21相对应的金属焊料凸块24；金属焊料凸块24具备较高温融焊特性；
第二步骤
如图6所示，在基板22上涂布封胶材料23(underfill)；
第三步骤
如图7所示，将晶片20翻转，使其上金属导体凸块21面朝下，并对正基板22上形成的金属焊料凸块24；
第四步骤
如图8、图9所示，以晶片20上的金属导体凸块21与基板22上金属焊料凸块24接触，并施以压合加热，使晶片20上金属导体凸块21藉由基板22上加热融熔后再硬化焊固的金属焊料凸块24牢固地焊接结合于基板22上。
由于金属焊料凸块24具备较高温融焊特性，以经第四步骤压合加热后，待温度降低后即可焊固，可很快进行后续加工制作流程，缩短晶片20结合时间，大幅度提高生产效率。

Claims (4)

1、一种覆晶件晶片的结合方法，它包括如下步骤：
第一步骤
在从晶圆厂生产制造完成的晶圆上预先设置金属导体凸块，并切割成适当大小形成晶片；
第二步骤
在基板上涂布封胶材料；
第三步骤
将晶片翻转，使其上金属导体凸块面朝下；
第四步骤
以晶片上的金属导体凸块与基板接触，进行加热结合；
其特征在于所述的
第一步骤中还包括在基板上与晶片结合的预留位置上，形成与晶片上金属导体凸块相对应的金属焊料凸块；
第三步骤中使晶片上的金属导体凸块对正基板上形成的金属焊料凸块；
第四步骤中晶片上的金属导体凸块与基板上金属焊料凸块接触，并施以压合加热，使晶片上金属导体凸块藉由基板上加热融熔后再硬化焊固的金属焊料凸块牢固地焊接结合于基板上。
2、根据权利要求1所述的覆晶件晶片的结合方法，其特征在于所述的基板上的金属焊料凸块以印刷方式形成。
3、根据权利要求1所述的覆晶件晶片的结合方法，其特征在于所述的基板上的金属焊料凸块以电镀方式形成。
4、根据权利要求2或3所述的覆晶件晶片的结合方法，其特征在于所述的基板上的金属焊料凸块具备较高温融焊特性。
CN00103473A 2000-03-13 2000-03-13 覆晶件晶片的结合方法 Pending CN1313631A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107481988A (zh) * 2017-07-28 2017-12-15 永道无线射频标签(扬州)有限公司 一种未使用导电胶的覆晶芯片封装产品及其制作工艺

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107481988A (zh) * 2017-07-28 2017-12-15 永道无线射频标签(扬州)有限公司 一种未使用导电胶的覆晶芯片封装产品及其制作工艺
CN107481988B (zh) * 2017-07-28 2020-09-01 永道无线射频标签(扬州)有限公司 一种未使用导电胶的覆晶芯片封装产品及其制作工艺

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