CN108807322A - 封装结构及其制造方法 - Google Patents

封装结构及其制造方法 Download PDF

Info

Publication number
CN108807322A
CN108807322A CN201711014931.7A CN201711014931A CN108807322A CN 108807322 A CN108807322 A CN 108807322A CN 201711014931 A CN201711014931 A CN 201711014931A CN 108807322 A CN108807322 A CN 108807322A
Authority
CN
China
Prior art keywords
layer
weld pad
protective coating
metal coupling
encapsulating structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201711014931.7A
Other languages
English (en)
Inventor
林柏均
朱金龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanya Technology Corp
Original Assignee
Nanya Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanya Technology Corp filed Critical Nanya Technology Corp
Publication of CN108807322A publication Critical patent/CN108807322A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03622—Manufacturing methods by patterning a pre-deposited material using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391—Forming a passivation layer after forming the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05562—On the entire exposed surface of the internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05563—Only on parts of the surface of the internal layer
    • H01L2224/05564—Only on the bonding interface of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05575—Plural external layers
    • H01L2224/0558—Plural external layers being stacked
    • H01L2224/05583—Three-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05671—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/1191—Forming a passivation layer after forming the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13561—On the entire surface of the core, i.e. integral coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1356—Disposition
    • H01L2224/13563—Only on parts of the surface of the core, i.e. partial coating
    • H01L2224/13564—Only on the bonding interface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/1357—Single coating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开了一种封装结构及其制造方法，封装结构包含：半导体基板；焊垫设置于半导体基板之上；导电层设置于焊垫之上；保护涂层；以及金属凸块设置于导电层之上，且保护涂层覆盖金属凸块，借以避免金属凸块的氧化。本发明能够满足减少回流工艺要求，并降低成本。

Description

封装结构及其制造方法
技术领域
本发明是有关于封装结构及其制造方法。
背景技术
回流焊接是使用焊膏(粉状焊料和焊剂的粘性混合物)将一个或多个电气部件附接到其接触焊盘的过程，然后整个组件受到受控的热，以熔化焊料，永久连接接头。加热可以通过将组件通过回流炉或红外线或通过用热气铅焊接各个接头来实现。
随着封装结构的发展，进行了越来越多的回流工艺，从而增加了成本。相关领域莫不费尽心思来谋求解决之道，但长久以来一直未见适用的方式被发展完成。为了满足减少回流工艺的要求，需要先进的封装形成方法和结构。
发明内容
本发明的目的在于提出一种创新的封装结构及其制造方法，以解决先前技术的困境。
在本发明的一实施例中，一种封装结构包含：半导体基板；焊垫设置于半导体基板之上；导电层设置于焊垫之上；保护涂层；以及金属凸块设置于导电层之上，且保护涂层覆盖金属凸块，以避免金属凸块的氧化。
在本发明的一实施例中，封装结构还包含：钝化层，设置于半导体基板之上，其中焊垫设置于钝化层之中，钝化层具有开口以部分暴露焊垫的表面，且导电层连接于焊垫的表面以及钝化层。
在本发明的一实施例中，金属凸块具有平坦表面，背离半导体基板。
在本发明的一实施例中，金属凸块具有非圆形状。
在本发明的一实施例中，金属凸块由铜形成。
在本发明的一实施例中，导电层为凸块下金属层。
在本发明的一实施例中，保护涂层为有机保焊剂层。
在本发明的一实施例中，封装结构还包含：焊料层，设置于保护涂层之上，且位于金属凸块的正上方。
在本发明的一实施例中，焊料层由锡形成。
在本发明的一实施例中，钝化层由二氧化硅形成。
在本发明的另一实施例中，一种封装结构的制造方法包含：提供半导体基板；在半导体基板之上形成焊垫；在焊垫之上形成导电层；在导电层之上形成金属凸块；以及在金属凸块之上形成保护涂层，使得保护涂层覆盖金属凸块，以避免金属凸块的氧化。
在本发明的一实施例中，制造方法还包含：在焊垫以及半导体基板之上形成钝化层；以及在钝化层中形成开口，以部分暴露焊垫的表面。
在本发明的一实施例中，在焊垫之上形成导电层，包含：形成导电层连接于焊垫的表面以及钝化层。
在本发明的一实施例中，制造方法还包含：在保护涂层之上且在金属凸块的正上方形成焊料层。
在本发明的一实施例中，制造方法还包含：在形成焊料层以后，对封装结构执行表面焊接技术，以移除保护涂层。
在本发明的一实施例中，保护涂层为有机保焊剂层，在表面焊接技术执行以后，有机保焊剂层被蒸发。
在本发明的又一实施例中，一种封装结构的制造方法包含：提供半导体基板；在半导体基板之上形成焊垫；在焊垫以及半导体基板之上形成钝化层；在钝化层中形成开口，以部分暴露焊垫的表面；形成导电层连接于焊垫的表面以及钝化层；在导电层之上形成金属凸块；在保护涂层之上且在金属凸块的正上方形成焊料层；以及执行回焊工艺，将焊料层形成为焊锡凸块，并移除保护涂层。
在本发明的又一实施例中，保护涂层为有机保焊剂层。
在本发明的又一实施例中，在回焊工艺执行后，有机保焊剂层被蒸发。
在本发明的又一实施例中，在保护涂层之上且在金属凸块的正上方形成焊料层的过程中，无需额外的回焊工艺。
综上所述，本发明的技术方案与现有技术相比具有明显的能够满足减少回流工艺要求，并降低成本的有益效果。以下将以实施方式对上述的说明作详细的描述，并对本发明的技术方案提供更进一步的解释。
附图说明
为让本发明的上述和其他目的、特征、优点与实施例能更明显易懂，现结合附图说明如下：
图1～图6是依照本发明实施例绘示的封装结构的制造程序。
具体实施方式
为了使本发明的叙述更加详尽与完备，可参照所附的附图及以下所述各种实施例，附图中相同的号码代表相同或相似的元件。另一方面，众所周知的元件与步骤并未描述在实施例中，以避免对本发明造成不必要的限制。
在实施方式与申请专利范围中，涉及“电性连接”的描述，其可泛指一个元件通过其他元件而间接电气耦合至另一个元件，或是一个元件无须通过其他元件而直接电气连结至另一个元件。
在实施方式与申请专利范围中，除非内文中对于冠词有所特别限定，否则“一”与“该”可泛指单一个或复数个。
图1～图6是依照本发明实施例绘示的封装结构的制造程序。应了解到，在本实施例中所提及的步骤，除特别叙明其顺序者外，均可依实际需要调整其前后顺序，甚至可同时或部分同时执行。
如图1所示，提供了半导体基板110。半导体基板110具有彼此相对的第一表面111和第二表面112。例如，半导体基板110是硅基板或其它合适的半导体基板。工艺从半导体基板110的第一表面111开始，其中焊垫120形成在半导体基板110上。
在结构上，焊垫120设置在半导体基板110上。焊垫120电连接到半导体基板110。例如，在半导体基板110的表面上或上方形成焊垫120。焊垫120用作在半导体基板110的表面中提供的焊料和电互连之间的界面。
在半导体基板110的表面上形成焊垫120(例如，接合焊垫或接触焊垫)之后，通过沉积钝化层130在焊垫120的表面上方，使焊垫120被钝化和电绝缘。在钝化层130沉积和图案化之后，在钝化层130中形成开口132并与焊垫120对齐。
在结构上，钝化层130设置在焊垫120和半导体基板110上。换句话说，焊垫120设置在钝化层130中，并且钝化层130被凹入以形成用于部分暴露的焊口120的表面122的开口132。在一些实施例中，钝化层130由二氧化硅形成，使得该结构可以具有高的成形精度和窄间距能力。在各种实施例中，钝化层130由聚酰亚胺形成。
参考图2，导电层140形成在焊垫120和钝化层130上，并且导电层140电连接到焊垫120。特别地，导电层140连接于焊垫120的表面122和钝化层130。在一些实施例中，导电层140是凸块下金属层。例如，凸块下金属层(该层可以是金属的复合层，如铬，随后是铜，随后是金，以促进改善的附着力(与铬)并形成扩散阻挡层或防止氧化(铜上的金))形成在钝化层130上并在钝化层130中形成的开口132内。
参考图3，金属凸块150形成在导电层140上，并且导电层140的冗余部分从钝化层130的表面移除。在图3中，金属凸块150设置在导电层140上，导电层140电连接到金属凸块150。在一些实施例中，金属凸块150由铜形成。
在结构上，金属凸块具有非圆形状(例如，矩形形状)，并且金属凸块150具有背离半导体基板110的平坦表面152(例如，顶表面)。以这种方式，如图5所示，金属凸块150的平坦表面152可以用于承载焊料层170。
参照图4，形成保护涂层160。在结构中，金属凸块150被保护涂层160覆盖，以避免金属凸块150的氧化。应该注意的是，如果保护涂层160被省略，则在金属凸块150的表面处暴露于密封前的空气，容易发生金属氧化。
在一些实施例中，保护涂层160是有机保焊剂层。有机保焊剂层具有成本低，界面平整，接合强度高，污染少，易制造的优点。
参考图5，焊料层170设置在保护涂层160上，并且焊料层170直接位在金属凸块150的正上方。在一些实施例中，焊料层170由锡形成。
在一些对照实验中，保护涂层160被省略，焊料层170直接形成在金属凸块150上，导致需要附加的回焊工艺(例如，红外回焊)。
与上述对照实验相比，在本实施例中，焊接层170形成在保护涂层160上，在此期间不需要额外的回焊工艺(例如，红外回焊)。
参考图6，在形成焊料层170之后，对封装结构进行表面焊接技术。然后，保护涂层160从封装结构中移除。焊料凸块172由焊料层170形成，并且焊料凸块172在金属凸块150处连接。以这种方式，焊料凸块172可用于与诸如晶片，基板，载体等的其它物体连接。
在表面焊接技术中，执行回焊工艺(例如，SMT回焊)以将焊料层170形成为焊料凸块172以及同时移除保护涂层160。在一些实施例中，保护涂层160是有机保焊剂层。回焊工艺后，有机保焊剂层蒸发。此外，有机保焊剂层的蒸发也可以清理封装结构。
虽然本发明已以实施方式公开如上，然其并非用以限定本发明，任何本领域的一般技术人员，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视权利要求所界定的为准。

Claims (20)

1.一种封装结构，其特征在于，包含：
半导体基板；
焊垫，设置于所述半导体基板之上；
导电层，设置于所述焊垫之上；
保护涂层；以及
金属凸块，设置于所述导电层之上，且所述保护涂层覆盖所述金属凸块，以避免所述金属凸块的氧化。
2.如权利要求1所述的封装结构，其特征在于，还包含：
钝化层，设置于所述半导体基板之上，
其中所述焊垫设置于所述钝化层中，所述钝化层具有开口以部分暴露所述焊垫的表面，且所述导电层连接于所述焊垫的所述表面以及所述钝化层。
3.如权利要求1所述的封装结构，其特征在于，所述金属凸块具有平坦表面，背离所述半导体基板。
4.如权利要求1所述的封装结构，其特征在于，所述金属凸块具有非圆形状。
5.如权利要求1所述的封装结构，其特征在于，所述金属凸块由铜形成。
6.如权利要求1所述的封装结构，其特征在于，所述导电层为凸块下金属层。
7.如权利要求1所述的封装结构，其特征在于，所述保护涂层为有机保焊剂层。
8.如权利要求1所述的封装结构，其特征在于，还包含：
焊料层，设置于所述保护涂层之上，且位于所述金属凸块的正上方。
9.如权利要求8所述的封装结构，其特征在于，所述焊料层由锡形成。
10.如权利要求1所述的封装结构，其特征在于，所述钝化层由二氧化硅形成。
11.一种封装结构的制造方法，其特征在于，所述制造方法包含：
提供半导体基板；
在所述半导体基板之上形成焊垫；
在所述焊垫之上形成导电层；
在所述导电层之上形成金属凸块；以及
在所述金属凸块之上形成保护涂层，使得所述保护涂层覆盖所述金属凸块，以避免所述金属凸块的氧化。
12.如权利要求11所述的制造方法，其特征在于，还包含：
在所述焊垫以及所述半导体基板之上形成钝化层；以及
在所述钝化层中形成开口，以部分暴露所述焊垫的表面。
13.如权利要求12所述的制造方法，其特征在于，所述导电层形成于所述焊垫之上，包含：
形成所述导电层连接于所述焊垫的所述表面以及所述钝化层。
14.如权利要求12所述的制造方法，其特征在于，还包含：
在所述保护涂层之上且在所述金属凸块的正上方形成焊料层。
15.如权利要求11所述的制造方法，其特征在于，还包含：
在形成所述焊料层以后，对所述封装结构执行表面焊接技术，以移除所述保护涂层。
16.如权利要求15所述的制造方法，其特征在于，所述保护涂层为有机保焊剂层，在所述表面焊接技术执行以后，所述有机保焊剂层被蒸发。
17.一种封装结构的制造方法，其特征在于，所述制造方法包含：
提供半导体基板；
在所述半导体基板之上形成焊垫；
在所述焊垫以及所述半导体基板之上形成钝化层；
在所述钝化层中形成开口，以部分暴露所述焊垫的一表面；
形成导电层连接于所述焊垫的所述表面以及所述钝化层；
在所述导电层之上形成金属凸块；
在所述保护涂层之上且在所述金属凸块的正上方形成焊料层；以及
执行回焊工艺，将所述焊料层形成为焊锡凸块，并移除所述保护涂层。
18.如权利要求17所述的制造方法，其特征在于，所述保护涂层为有机保焊剂层。
19.如权利要求18所述的制造方法，其特征在于，在所述回焊工艺执行后，所述有机保焊剂层被蒸发。
20.如权利要求17所述的制造方法，其特征在于，在所述保护涂层之上且在所述金属凸块的正上方形成所述焊料层的过程中，无需额外的回焊工艺。
CN201711014931.7A 2017-04-26 2017-10-25 封装结构及其制造方法 Pending CN108807322A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/497,227 2017-04-26
US15/497,227 US20180315725A1 (en) 2017-04-26 2017-04-26 Package structure having bump with protective anti-oxidation coating

Publications (1)

Publication Number Publication Date
CN108807322A true CN108807322A (zh) 2018-11-13

Family

ID=63916797

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711014931.7A Pending CN108807322A (zh) 2017-04-26 2017-10-25 封装结构及其制造方法

Country Status (3)

Country Link
US (1) US20180315725A1 (zh)
CN (1) CN108807322A (zh)
TW (1) TWI644409B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10319695B2 (en) * 2017-06-29 2019-06-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and bump formation process
CN111463181B (zh) * 2020-03-31 2021-07-06 厦门通富微电子有限公司 一种晶圆单元凸块防脱落的方法及晶圆单元
WO2021231307A1 (en) 2020-05-12 2021-11-18 Lam Research Corporation Controlled degradation of a stimuli-responsive polymer film
KR20230062791A (ko) * 2020-09-10 2023-05-09 램 리써치 코포레이션 저온 직접 금속-금속 본딩 (metal-metal bonding) 시 옥사이드 방지를 위한 임시 캡핑 재료 (temporary capping material)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101131949A (zh) * 2006-08-22 2008-02-27 日月光半导体制造股份有限公司 形成金属凸块的方法
CN101290917A (zh) * 2007-04-17 2008-10-22 南亚电路板股份有限公司 焊接垫结构
CN101540310A (zh) * 2008-03-14 2009-09-23 日月光半导体制造股份有限公司 半导体封装及其制作方法
CN102804364A (zh) * 2009-06-26 2012-11-28 英特尔公司 封装体堆叠装置中的层叠芯片封装体及其组装方法、以及包含该层叠芯片封装体的系统
CN103000542A (zh) * 2011-09-16 2013-03-27 南茂科技股份有限公司 半导体封装结构焊帽凸块与其制作方法
CN103811355A (zh) * 2012-11-02 2014-05-21 台湾积体电路制造股份有限公司 用于叠层封装器件的模制底部填充物
CN104425462A (zh) * 2013-08-26 2015-03-18 精材科技股份有限公司 电感结构及其制作方法
CN106887420A (zh) * 2015-12-16 2017-06-23 敦南科技股份有限公司 凸块构造与其构成的内连结构

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI395310B (zh) * 2010-04-29 2013-05-01 Advanced Semiconductor Eng 基板及應用其之半導體封裝件與其製造方法
TWI453837B (zh) * 2011-06-13 2014-09-21 Advanced Semiconductor Eng 具有非導電層的半導體封裝及其製造方法
US8912651B2 (en) * 2011-11-30 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) structure including stud bulbs and method

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101131949A (zh) * 2006-08-22 2008-02-27 日月光半导体制造股份有限公司 形成金属凸块的方法
CN101290917A (zh) * 2007-04-17 2008-10-22 南亚电路板股份有限公司 焊接垫结构
CN101540310A (zh) * 2008-03-14 2009-09-23 日月光半导体制造股份有限公司 半导体封装及其制作方法
CN102804364A (zh) * 2009-06-26 2012-11-28 英特尔公司 封装体堆叠装置中的层叠芯片封装体及其组装方法、以及包含该层叠芯片封装体的系统
CN103000542A (zh) * 2011-09-16 2013-03-27 南茂科技股份有限公司 半导体封装结构焊帽凸块与其制作方法
CN103811355A (zh) * 2012-11-02 2014-05-21 台湾积体电路制造股份有限公司 用于叠层封装器件的模制底部填充物
CN104425462A (zh) * 2013-08-26 2015-03-18 精材科技股份有限公司 电感结构及其制作方法
CN106887420A (zh) * 2015-12-16 2017-06-23 敦南科技股份有限公司 凸块构造与其构成的内连结构

Also Published As

Publication number Publication date
US20180315725A1 (en) 2018-11-01
TW201839944A (zh) 2018-11-01
TWI644409B (zh) 2018-12-11

Similar Documents

Publication Publication Date Title
CN108807322A (zh) 封装结构及其制造方法
US5439162A (en) Direct chip attachment structure and method
US7148086B2 (en) Semiconductor package with controlled solder bump wetting and fabrication method therefor
US11424170B2 (en) Method for mounting an electrical component in which a hood is used, and a hood that is suitable for use in this method
JP2016213426A (ja) 半導体のパッケージング方法
CN101030546B (zh) 电容安装方法
KR20080038028A (ko) 기판에 전자 부품을 탑재하는 방법 및 솔더면을 형성하는방법
US20060242825A1 (en) Method of making a circuitized substrate
US8296940B2 (en) Method of forming a micro pin hybrid interconnect array
CN100552927C (zh) 具有加固件的覆晶封装结构及其封装方法
TWI478257B (zh) 封裝結構及封裝製程
US10998201B2 (en) Semiconductor encapsulation structure
TW201411793A (zh) 半導體裝置及其製造方法
TWI647769B (zh) 電子封裝件之製法
AU653945B2 (en) Attaching integrated circuits to circuit boards
CN108364920A (zh) 倒装芯片组件、倒装芯片封装结构及制备方法
US20200176311A1 (en) Arrangement method and arrangement structure of conductive material, and led display thereof
JPH05136146A (ja) 半導体装置の電極と検査方法
US10897822B2 (en) Electronic device comprising an electronic component mounted on a support substrate and assembly method
TWI239086B (en) Circuit board structure integrated with semiconductor chip and method for fabricating the same
US8604356B1 (en) Electronic assembly having increased standoff height
CN104981092A (zh) 表面镀层和包括该表面镀层的半导体封装件
KR100871067B1 (ko) 구리 포스트 형성을 통한 고강도 솔더범프 제조방법
JP2633745B2 (ja) 半導体装置の実装体
CN103855043A (zh) 半导体封装倒装焊接方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20181113