CN101030546B - 电容安装方法 - Google Patents

电容安装方法 Download PDF

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CN101030546B
CN101030546B CN2007100850843A CN200710085084A CN101030546B CN 101030546 B CN101030546 B CN 101030546B CN 2007100850843 A CN2007100850843 A CN 2007100850843A CN 200710085084 A CN200710085084 A CN 200710085084A CN 101030546 B CN101030546 B CN 101030546B
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electric capacity
substrate
pad
solder flux
tube core
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CN101030546A (zh
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卢威耀
冯志成
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NXP USA Inc
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Freescale Semiconductor Inc
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Abstract

本申请涉及一种将电容(112)安装到基片(100)上的方法，包括将焊剂(108)应用于基片(100)上的各个电容焊盘(104，106)。将电容(112)放在经焊剂处理的电容焊盘(104，106)上以及在电容(112)和基片(100)上执行回流操作，使得在电容(112)和基片(100)之间形成金属间互联(128)。

Description

电容安装方法
技术领域
本发明涉及集成电路(IC)的封装，并且更具体地涉及将电容安装到基片上的方法。
背景技术
焊膏，焊剂介质中一种高级焊料合金粉末微粒的特别混合膏剂，通常用于电容到基片的安装。图1示出包括将电容安装到基片的形成半导体封装的传统方法10。在第一步骤12中，将焊膏涂到基片上的特定位置，并且在步骤14，使用焊膏将电容安装到基片上。在步骤16，将焊剂涂到基片上的受控塌陷芯片连接(controlled collapse chipconnection，C4)焊盘上，并且在步骤18将凸块集成电路(IC)管芯放在经焊剂处理的C4焊盘上。在步骤20执行回流操作。回流操作熔化焊膏，在电容和基片之间形成焊点。在步骤22，将底层填料涂到基片与凸块IC管芯之间的缝隙中，从而形成半导体封装器件。
但是，在用于将电容装配到基片表面上的当前焊料安装工艺中遇到了若干问题。包括焊料结球、竖碑效应和焊料过多。这些问题中的每一个都是使半导体单元成为废品的原因。
焊料结球是一种焊接缺陷，其特征在于存在沿焊点的外围边缘存留的微小的焊料球。图2中示出了焊料结球缺陷的实例。在图2中，示出具有第一末端端子32和第二末端端子34的电容30。电容30的第一和第二末端端子32和34通过各自的第一和第二焊点42和44分别安装到基片40上的第一电容焊盘36和第二电容焊盘38。可以看出，在第一焊点42的表面上形成了焊料球46。许多这种焊料球46的存在经常导致电容短路。
竖碑效应是元件一端从基片抬起而元件另一端仍与基片结合的一种现象。图3中示出了竖碑效应缺陷的实例。图3示出具有第一末端端子52和第二末端端子54的电容50。电容50的第一末端端子52通过由焊接材料62构成的连接点60结合到基片58上的第一电容焊盘56。如可见的，电容50的第二末端端子54升起并且从基片58上的第二电容焊盘64分离。图3中所示的竖碑效应缺陷可由第一和第二电容焊盘56和64上沉积的焊接材料62体积不同而造成。
现在参考图4，描述焊料过多的实例。图4示出具有第一末端端子72和第二末端端子74的电容70。电容70的第一末端端子72和第二末端端子74通过各自的第一和第二焊点82和84分别安装到基片80上的第一电容焊盘76和第二电容焊盘78。但是，由于过多焊料的存在，第一和第二焊点82和84具有凸起的外形90和92(图4中实线所勾画的)，而不是所需的凹陷外形86和88(图4中虚线所勾画的)。焊料过多是不好的，因为太多的焊料会导致桥接缺陷，这将导致电短路。
除了丢弃具有焊接问题的半导体单元所造成的损失，当在电容安装工艺中使用焊膏时也发生材料、人力和机器的成本。所有这些都增加整个制造成本。
考虑到上述问题，需要一种不使用焊膏而将电容安装到基片的方法。
发明内容
本发明提供了一种将电容安装到基片的方法。该方法本质上仅包括：将焊剂应用于基片上金(Au)或镀金的电容焊盘；将电容放在经焊剂处理的电容焊盘上；以及执行回流操作。电容端子优选地是锡(Sn)或镀锡的。
本发明还提供了一种形成封装的半导体器件的方法，主要步骤本质上仅包括：提供基片；将焊剂应用于基片上的受控塌陷芯片连接(C4)焊盘和各自的金或镀金的电容焊盘；将一个或多个电容放在各自的电容焊盘上并将一个或多个集成电路(IC)管芯放在基片上的C4焊盘上；以及在电容、IC管芯和基片上执行回流操作。优选地，电容端子由锡或镀锡形成。
本发明还提供了一种形成多芯片组件(MCM)的方法，包括步骤：提供基片；将焊剂应用于基片上各个金(Au)或镀金的电容焊盘和各个C4焊盘；将具有锡或镀锡端子的多个电容放在各自的电容焊盘上并且将多个集成电路(IC)管芯放在各自的C4焊盘上；以及在电容、IC管芯和基片上执行回流操作，使得金-锡(Au-Sn)金属间互联形成在基片电容焊盘和各个电容端子之间。将底层填料涂到基片和各个IC管芯之间的多个缝隙中。最后，电容和IC管芯以多个盖子中各自的一个密封，从而形成多芯片组件。
附图说明
当结合附图阅读时将更好地理解以下对本发明优选实施例的具体描述。本发明以实例的方式示出并且不受附图限制，附图中相似的参考标号指示相似的元件。应理解，附图不是按比例绘制，并且为了便于理解本发明而进行了简化。
图1是描述形成封装的半导体器件的传统方法的流程图；
图2是在电容和基片之间的焊点表面上形成的焊料球的放大横截面图；
图3是一端从基片抬起并且另一端与基片结合的电容的放大横截面图；
图4是在电容和基片之间各个焊点中过多的焊料的放大横截面图；
图5A是根据本发明实施例将焊剂应用于基片上的电容焊盘的放大横截面图；
图5B是将电容放在图5A的经焊剂处理的电容焊盘上的放大横截面图；
图5C是将集成电路(IC)管芯放在图5B的基片上的放大横截面图；
图5D是在图5C的基片、电容和IC管芯上执行回流操作的放大横截面图；
图5E是涂到图5D的基片与各个IC管芯之间的缝隙中的底层填料的放大横截面图；
图5F是根据本发明的实施例形成的多芯片组件(multi-chipmodule，MCM)的放大横截面图；
图6是说明根据本发明实施例形成封装的半导体器件方法的流程图；
图7是金-锡(Au-Sn)系统的相图。
具体实施方式
以下结合附图进行的具体描述旨在作为本发明的当前优选实施例的描述，并且不旨在代表本发明可以实践的唯一形式。应理解，可以由旨在包括在本发明的精神和范围内的不同的实施例实现相同或等价的功能。在附图中，遍及附图使用相似的标号指示相似的元件。
现在参考图5A到5F和图6，描述根据本发明形成封装的半导体器件的方法。
图5A示出基片100，其上形成有金属化层102。金属化层102包括一个或多个第一和第二电容焊盘104和106以及多个受控塌陷芯片连接(C4)焊盘(未示出)。第一和第二电容焊盘104和106被镀以金属。通过喷嘴110将焊剂108应用于基片100上的第一和第二电容焊盘104和106。在作为形成封装的半导体器件的工艺150的流程图的图6中，步骤152表示基片100的提供，并且步骤154指示将焊剂108应用于基片100上的各个电容焊盘104和106。
基片100优选是比如多层陶瓷(MLC)的陶瓷基片。这种基片在本领域中是已知的并且可从商业途径获得。使用已知的电镀工艺在基片100上形成金属化层102。金属化层102可包括铜(Cu)、锡(Sn)、金(Au)、镍(Ni)、锡-铅(Sn-Pb)焊料或本领域中技术人员所知的其它适合的金属或合金。第一和第二电容焊盘104和106优选地镀有铜(Au)。在一个实施例中，金属化层102与第一和第二电容焊盘镀上Au以到大约0.1微米(μm)的厚度。虽然如此，但本领域的技术人员将理解，本发明不应被用于形成金属化层102的金属或合金、金属化层102的厚度、或第一和第二焊盘104和106的厚度限制到特定类型的基片100。
尽管图5A中未示出，焊剂108也应用于基片100上的C4焊盘。图6中的步骤156指出焊剂108应用于C4焊盘。焊剂108将氧化物从第一和第二电容焊盘104和106以及C4焊盘除去以帮助其上的金属间结合的形成。依照IPC-J-STD-004标准对焊接焊剂的要求，焊剂108优选是松香类焊剂，比如，松香(R)焊剂或中度活性松香(RMA)焊剂。如可从图5A所见的，在此特定实施例中通过喷射将焊剂108应用于第一和第二电容焊盘104和106。尽管如此，本领域的技术人员应理解，本发明不受焊剂的应用方法的限制。例如，焊剂108也可以通过点涂应用于第一和第二电容焊盘104和106以及C4焊盘。另一替代方案是将电容蘸入焊剂池并且将带有焊剂的电容移至基片，带有焊剂的电容端子接触各自的电容焊盘104和106。本发明不同于现有技术方法(图1)之处在于不对电容焊盘104和106应用焊膏。
现在参考图5B和图6，具有各自的第一和第二末端端子114和116的一个或多个电容112在步骤158放在各自的第一和第二电容焊盘104和106上。更具体地，每个电容112横跨一对第一和第二电容焊盘104和106而放置，使得第一末端端子114接触第一电容焊盘104并且第二末端端子116接触第二电容焊盘106。
电容112是比如多层陶瓷电容(MLCC)的片上电容。这种电容112在本领域中是公知的并且可从商业途径获得。第一和第二末端端子114和116为电容112中各自的传导元件提供电端子。可以通过将电容112的每个末端蘸入比如银(Ag)墨水的厚膜膏料，然后以例如镍(Ni)和锡(Sn)的金属和合金中的一种或多种固化和电镀电容112的末端，而形成第一和第二末端端子114和116。因此，在一个实施例中，第一和第二末端端子114和116包括具有再镀Sn的镀镍银。在另一实施例中，电容端子114、116是仅镀锡的银端子。可以手动或者通过自动装置将电容112放在基片100上。在如图5B中所示的实施例中，使用标准拾-放机器的放置头118将电容112放在基片100上。通过将粘性焊剂108应用于第一和第二电容焊盘104和106使得电容112在后续的工艺步骤中保持在适当位置。
现在参考图5C和图6，在步骤160将一个或多个集成电路(IC)管芯120放在各自的C4焊盘上。所示实施例中的IC管芯120是在其底面124上具有凸块连接122的倒装芯片管芯。将IC管芯120放在基片100上使得IC管芯120的凸块连接122接触基片100上的各自的一个C4焊盘。可以通过自动拾-放或通过手动放置将IC管芯120放在基片100上。在所示实施例中，使用标准拾-放机器的放置头118将IC管芯120放在基片100上。
IC管芯120可以是任何类型的电路，比如数字信号处理器(DSP)或专用功能电路。IC管芯120不受比如CMOS，或得自任何特定晶片技术的特定技术的限制。此外，本发明可适合各种尺寸的IC管芯120；例如，IC管芯120可以是大约10毫米(mm)乘大约10mm的尺寸。凸块连接122由比如金、铜、或金属合金的传导金属制成，并且使用已知的晶片凸起形成工艺在IC管芯120上形成。本领域的技术人员已知这种倒装芯片凸起管芯120，对于完整理解本发明不需要进一步的解释。
现在参考图5D和图6，在步骤162，通过让基片100通过回流炉而在基片100、电容112和IC管芯120上上执行回流操作。回流炉优选装有运输带。可以使用比如红外线(IR)回流、汽相回流和空气对流回流的回流安装的已知方法执行回流操作。优选地在高于大约300℃的温度下回流基片100、电容112和IC管芯120。在一个实施例中，在大约360℃的温度下回流基片100、电容112和IC管芯120。
回流炉中的热量熔化第一和第二电容焊盘104和106以及凸块连接122。熔化的第一和第二电容焊盘104和106浸润电容112上的各自的第一和第二末端端子114和116，而熔化的凸块连接122浸润基片100上的C4焊盘。
现在参考图5E，在冷却的基片100上，在基片100和各个电容112之间形成金属间互联128，而在基片100和各个IC管芯120之间形成受控塌陷芯片连接(C4)互联130。金属间互联128优选是包括大约20重量百分比(wt％)的Au和大约80wt％的Sn的金-锡(Au-Sn)金属间互联。现在参考图7，示出了金-锡(Au-Sn)系统的相图。如从图7中可见的，在大约280℃和大约300℃之间的温度下形成具有大约20wt％的Au和大约80wt％的Sn的成分的稳定的Au-Sn金属间互联。尽管如此，本领域技术人员应理解，上述的工艺温度和成分仅是示例性的。本领域的技术人员应理解，本发明不受回流工艺的温度、金属间互联128的成分或形成金属间互联128的温度的限制。而是，工艺温度和成分取决于形成和电镀第一和第二电容焊盘104和106的金属或合金的类型。
再参考图5E，将底层填料132涂到基片100和各个IC管芯120之间的多个缝隙134中。在图6中，步骤164指示将底层填料132涂到缝隙134。底层填料132通过降低由基片100和IC管芯120之间的热膨胀系数(CTE)不匹配引起的C4连接130上的张力而为C4连接130提供机械支撑。底层填料132可以包括已熟知的可从商业途径获得的底层填充材料，比如环氧树脂。在一个实施例中，通过使用针沿各个IC管芯120的边缘涂底层填充材料而对IC管芯120进行底层填充。在这个实施例中，通过毛细管作用向内吸底层填料132，直到基片100和各个IC管芯120之间的缝隙134被填满。然后将底层填料132固化。尽管如此，应理解本发明不受底层填料132的成分或上述的底层填充工艺所限制。在另一实施例中，可以使用本领域技术人员已知的其它底层填充工艺对IC管芯120进行底层填充。
现在参考图5F和图6，在步骤166，电容122和IC管芯120以多个盖子136或帽中各自的一个密封，盖子136或帽增强了散热通路并且提供对电容和管芯的保护以防外部磨损。更具体地，每个盖子136放在一个或多个电容112上以及各个IC管芯120上，然后以盖子安装材料140安装到基片100上以形成多个真空密封的多芯片组件138。盖子136可以由陶瓷或金属制成。盖子安装材料140对于陶瓷盖子136可以是环氧树脂或硅树脂，或者当盖子136由金属制成时可以是焊接材料。在步骤168可以将多个导电球144安装到基片100的下侧146。导电球144可以是受控塌陷芯片连接(C4)焊料球并且使用已知的焊料球安装工艺安装到基片100。
尽管图5D到5F示出三个(3)IC管芯120安装到基片100，应理解，更多和更少的IC管芯120可以安装到基片100，这取决于基片100的尺寸、IC管芯120的尺寸、以及最终半导体封装器件的所需功能。
与比如图1所描述的传统电容安装方法不同，本发明不需要使用焊膏。而是，电容直接放在基片的经焊剂处理的电容焊盘上，然后在电容和基片之间形成金属间互联。通过不使用焊膏，实现了显著的材料、人力和机器成本的节约，从而降低整个封装成本。另外，可根除当使用焊膏时遇到的问题，例如焊料结球、竖碑效应和焊料过多。
已出于说明和描述的目的进行了本发明优选实施例的描述，但是该描述不旨在成为无遗漏的详尽描述或将本发明限制到所公开的形式。本领域技术人员将意识到，可以不脱离其广泛的发明概念而对上述实施例进行变更。因此应理解，本发明不限于所公开的特定实施例，而是覆盖在所附权利要求定义的本发明的精神和范围内的修改。

Claims (20)

1.一种将电容安装到基片的方法，包括：
将焊剂应用于基片上的各个电容焊盘；
将电容放在经焊剂处理的电容焊盘上，使得电容的端子接触各自的一个所述经焊剂处理的电容焊盘；以及
在电容和基片上执行回流操作。
2.如权利要求1所述的将电容安装到基片的方法，其中，该基片电容焊盘被镀以金(Au)。
3.如权利要求2所述的将电容安装到基片的方法，其中，电容的端子被镀以锡(Sn)。
4.如权利要求3所述的将电容安装到基片的方法，其中，在电容端子和基片电容焊盘之间形成金-锡(Au-Sn)金属间互联。
5.如权利要求4所述的将电容安装到基片的方法，其中，该Au-Sn金属间互联包括20重量百分比(wt％)的Au和80wt％的Sn。
6.如权利要求5所述的将电容安装到基片的方法，其中，在280℃和300℃之间的温度下形成该Au-Sn金属间互联。
7.如权利要求6所述的将电容安装到基片的方法，其中，在大于300℃的温度下回流电容和基片。
8.如权利要求1所述的将电容安装到基片的方法，其中，该焊剂包括松香焊剂和中度活性松香焊剂之一。
9.如权利要求1所述的将电容安装到基片的方法，其中，通过喷射和点涂之一应用焊剂。
10.如权利要求1所述的将电容安装到基片的方法，其中，该焊剂将氧化物从基片上的电容焊盘除去。
11.如权利要求1所述的将电容安装到基片的方法，其中，该焊剂将电容保持在适当位置。
12.一种形成封装的半导体器件的方法，包括：
提供基片；
将焊剂应用于基片上的各个电容焊盘；
将一个或多个电容放在各自的电容焊盘上，其中电容的端子接触各自的一个基片电容焊盘；
将一个或多个集成电路(IC)管芯放在基片上的各自的受控塌陷芯片连接(C4)焊盘上；以及
在一个或多个电容、一个或多个IC管芯和基片上执行回流操作。
13.如权利要求12所述的形成封装的半导体器件的方法，其中，在基片电容焊盘和各自的一个或多个电容的端子之间形成金-锡(Au-Sn)金属间互联。
14.如权利要求12所述的形成封装的半导体器件的方法，还包括将焊剂应用于基片上的各个C4焊盘。
15.如权利要求12所述的形成封装的半导体器件的方法，还包括将底层填料涂到基片和各个一个或多个IC管芯之间的一个或多个缝隙中。
16.如权利要求15所述的形成封装的半导体器件的方法，还包括密封该一个或多个电容以及该一个或多个IC管芯。
17.如权利要求16所述的形成封装的半导体器件的方法，其中，该一个或多个IC管芯以及该一个或多个电容以一个或多个盖子中的各自的一个密封。
18.如权利要求16所述的形成封装的半导体器件的方法，还包括将多个导电球安装到基片的下侧。
19.如权利要求12所述的形成封装的半导体器件的方法，其中，在大于300℃的温度下回流基片、一个或多个电容以及一个或多个IC管芯。
20.一种形成多芯片组件的方法，包括步骤：
提供具有镀金的电容焊盘的基片；
将焊剂应用于基片上各个电容焊盘和各个受控塌陷芯片连接(C4)焊盘；
将多个电容放在各自的经焊剂处理的电容焊盘上，其中电容具有镀锡端子；
将多个集成电路(IC)管芯放在各自的经焊剂处理的C4焊盘上；
在基片、电容和IC管芯上执行回流操作，使得金-锡(Au-Sn)金属间互联形成在基片电容焊盘和各个电容的端子端之间；
将底层填料涂到基片和各个IC管芯之间的多个缝隙中；以及
以多个盖子中各自的一个密封电容和IC管芯，从而形成多芯片组件。
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